slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2023-01-07	Merge tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu into s...	Peter Maydell
2023-01-06	Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem...	Peter Maydell
2023-01-06	Merge tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu into staging	Peter Maydell
2023-01-06	Merge tag 'pull-hex-20230105' of https://github.com/quic/qemu into staging	Peter Maydell
2023-01-06	hw/intc/loongarch_pch: Change default irq number of pch irq controller	Tianrui Zhao
2023-01-06	hw/intc/loongarch_pch_pic: add irq number property	Tianrui Zhao
2023-01-06	hw/intc/loongarch_pch_msi: add irq number property	Tianrui Zhao
2023-01-06	hw/intc: sifive_plic: Fix the pending register range check	Bin Meng
2023-01-06	hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization	Bin Meng
2023-01-06	hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0	Bin Meng
2023-01-06	hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb	Bin Meng
2023-01-06	hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"	Bin Meng
2023-01-06	hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC	Bin Meng
2023-01-06	hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC	Bin Meng
2023-01-06	hw/intc: sifive_plic: Update "num-sources" property default value	Bin Meng
2023-01-06	hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in ...	Bin Meng
2023-01-06	hw/intc: sifive_plic: Improve robustness of the PLIC config parser	Bin Meng
2023-01-06	hw/intc: sifive_plic: Drop PLICMode_H	Bin Meng
2023-01-06	hw/riscv: spike: Remove misleading comments	Bin Meng
2023-01-06	hw/riscv: Sort machines Kconfig options in alphabetical order	Bin Meng
2023-01-06	hw/riscv: Fix opentitan dependency to SIFIVE_PLIC	Bin Meng
2023-01-06	hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers	Bin Meng
2023-01-06	hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC	Bin Meng
2023-01-06	RISC-V: Add Zawrs ISA extension support	Christoph Muellner
2023-01-06	target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+	Bin Meng
2023-01-06	target/riscv: Simplify helper_sret() a little bit	Bin Meng
2023-01-06	target/riscv: Set pc_succ_insn for !rvc illegal insn	Richard Henderson
2023-01-06	target/riscv: Fix mret exception cause when no pmp rule is configured	Bin Meng
2023-01-06	hw/intc: sifive_plic: fix out-of-bound access of source_priority array	Jim Shu
2023-01-06	hw/{misc, riscv}: pfsoc: add system controller as unimplemented	Conor Dooley
2023-01-06	hw/riscv: pfsoc: add missing FICs as unimplemented	Conor Dooley
2023-01-06	hw/misc: pfsoc: add fabric clocks to ioscb	Conor Dooley
2023-01-06	target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()	Bin Meng
2023-01-06	target/riscv: support cache-related PMU events in virtual mode	Jim Shu
2023-01-06	hw/riscv: virt: Remove the redundant ipi-id property	Atish Patra
2023-01-06	target/riscv: Typo fix in sstc() predicate	Anup Patel
2023-01-06	hw/intc: sifive_plic: Renumber the S irqs for numa support	Frédéric Pétrot
2023-01-06	target/riscv: Add itrigger_enabled field to CPURISCVState	LIU Zhiwei
2023-01-06	target/riscv: Enable native debug itrigger	LIU Zhiwei
2023-01-06	target/riscv: Add itrigger support when icount is enabled	LIU Zhiwei
2023-01-06	target/riscv: Add itrigger support when icount is not enabled	LIU Zhiwei
2023-01-06	target/riscv: generate virtual instruction exception	Mayuresh Chitale
2023-01-06	target/riscv: smstateen check for h/s/envcfg	Mayuresh Chitale
2023-01-06	target/riscv: Add smstateen support	Mayuresh Chitale
2023-01-06	hw/riscv/opentitan: add aon_timer base unimpl	Wilfred Mallawa
2023-01-06	hw/riscv/opentitan: bump opentitan	Wilfred Mallawa
2023-01-06	tcg/riscv: Fix base register for user-only qemu_ld/st	Richard Henderson
2023-01-06	tcg/riscv: Fix reg overlap case in tcg_out_addsub2	Richard Henderson
2023-01-06	tcg/riscv: Fix range matched by TCG_CT_CONST_M12	Richard Henderson
2023-01-06	target/riscv: Fix PMP propagation for tlb	LIU Zhiwei