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2022-01-12target/ppc: Set the correct endianness for powernv memory dumpsFabiano Rosas
We use the endianness of interrupts to determine which endianness to use for the guest kernel memory dump. For machines that support HILE (powernv8 and up) we have been always generating big endian dump files. This patch uses the HILE support recently added to ppc_interrupts_little_endian to fix the endianness of the dumps for powernv machines. Here are two dumps created at different moments: $ file skiboot.dump skiboot.dump: ELF 64-bit MSB core file, 64-bit PowerPC ... $ file kernel.dump kernel.dump: ELF 64-bit LSB core file, 64-bit PowerPC ... Suggested-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12target/ppc: Introduce a wrapper for powerpc_excpFabiano Rosas
Next patches will split powerpc_excp in multiple family specific handlers. This patch adds a wrapper to make the transition clearer. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12target/ppc: Use ppc_interrupts_little_endian in powerpc_excpFabiano Rosas
The ppc_interrupts_little_endian function is now suitable for determining the endianness of interrupts for all CPUs. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12target/ppc: Add MSR_ILE support to ppc_interrupts_little_endianFabiano Rosas
Some CPUs set ILE via an MSR bit. We can make ppc_interrupts_little_endian handle that case as well. Now we have a centralized way of determining the endianness of interrupts. This change has no functional impact. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12target/ppc: Add HV support to ppc_interrupts_little_endianFabiano Rosas
The ppc_interrupts_little_endian function could be used for interrupts delivered in Hypervisor mode, so add support for powernv8 and powernv9 to it. Also drop the comment because it is inaccurate, all CPUs that can run little endian can have interrupts in little endian. The point is whether they can take interrupts in an endianness different from MSR_LE. This change has no functional impact. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12target/ppc: powerpc_excp: Group unimplemented exceptionsFabiano Rosas
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107222601.4101511-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12target/ppc: powerpc_excp: Keep 60x/7x5 soft MMU logs activeFabiano Rosas
Remove the compile time definition and make the logging be controlled by the `-d mmu` option in the cmdline. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12target/ppc: powerpc_excp: Extract software TLB logging into a functionFabiano Rosas
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107222601.4101511-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12docs: Clarifications and formatting changes in ppc docs.Leonardo Garcia
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <3b228af4785241c7fb4a2c70f0c495d2a9adea83.1641405872.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12MAINTAINERS: Improve the PowerPC machines sectionThomas Huth
Add some documentation files to the corresponding machine sections and mention the machine names in the section titles where it is not so obvious (e.g. that "taihu" is a 405 machine). Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220105104800.407570-1-thuth@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12docs/system/ppc: Merge the PEF information into the pseries pageThomas Huth
The Protected Execution Facility is only available with the pseries machine, so let's merge the old ASCII text into the new RST file now. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220105103232.405204-1-thuth@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12target/ppc: Add extra float instructions to POWER5P processorsCédric Le Goater
ISA v2.03 introduced Floating Round to Integer instructions : frin, friz, frip, and frim. Add them to POWER5+. The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal Estimate) instruction which was introduced in ISA v2.0x. The architecture document says its optional and that might be the reason why it has been kept under the PPC_FLOAT_EXT flag. This means 970 CPUs can not use it under QEMU, which doesn't seem to be a problem. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12spapr: Fix support of POWER5+ processorsCédric Le Goater
POWER5+ (ISA v2.03) processors are supported by the pseries machine but they do not have Altivec instructions. Do not advertise support for it in the DT. To be noted that this test is in contradiction with the assert in cap_vsx_apply(). Signed-off-by: Cédric Le Goater <clg@kaod.org> Tested-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220105095142.3990430-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12target/ppc: Add popcntb instruction to POWER5+ processorsCédric Le Goater
popcntb instruction was added in ISA v2.02. Add support for POWER5+ processors since they implement ISA v2.03. PPC970 CPUs implement v2.01 and do not support popcntb. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220105095142.3990430-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12Merge tag 'qemu-slof-20220110' of github.com:aik/qemu into ppc-7.0Cédric Le Goater
* tag 'qemu-slof-20220110' of github.com:aik/qemu: pseries: Update SLOF firmware image Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-11Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' ↵Peter Maydell
into staging Python pull request Fixes for the tests that broke during vacation, plus a simple syntax fix for a python script. # gpg: Signature made Mon 10 Jan 2022 23:24:47 GMT # gpg: using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full] # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * remotes/jsnow-gitlab/tags/python-pull-request: simplebench: Fix Python syntax error (reported by LGTM) python: update type hints for mypy 0.930 Python/aqmp: fix type definitions for mypy 0.920 python/aqmp: use absolute import statement Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-01-11Merge remote-tracking branch 'remotes/philmd/tags/sdmmc-20220108' into stagingPeter Maydell
SD/MMC patches queue - Add SDHC support for SD card SPI-mode (Frank Chang) # gpg: Signature made Sat 08 Jan 2022 21:56:02 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/sdmmc-20220108: hw/sd: Add SDHC support for SD card SPI-mode hw/sd/sdcard: Rename Write Protect Group variables Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-01-11Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
virtio: revert config interrupt changes Lots of fallout from config interrupt changes. Author wants to rework the patches. Let's revert quickly so others don't suffer meanwhile. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 10 Jan 2022 21:03:44 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: Revert "virtio: introduce macro IRTIO_CONFIG_IRQ_IDX" Revert "virtio-pci: decouple notifier from interrupt process" Revert "virtio-pci: decouple the single vector from the interrupt process" Revert "vhost: introduce new VhostOps vhost_set_config_call" Revert "vhost-vdpa: add support for config interrupt" Revert "virtio: add support for configure interrupt" Revert "vhost: add support for configure interrupt" Revert "virtio-net: add support for configure interrupt" Revert "virtio-mmio: add support for configure interrupt" Revert "virtio-pci: add support for configure interrupt" Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-01-10simplebench: Fix Python syntax error (reported by LGTM)Stefan Weil
Fixes: b2fcb0c5754c2554b8406376e99a75e9e0a6b7bd Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 20220107153019.504124-1-sw@weilnetz.de Signed-off-by: John Snow <jsnow@redhat.com>
2022-01-10python: update type hints for mypy 0.930John Snow
Mypy 0.930, released Dec 22, changes the way argparse objects are considered. Crafting a definition that works under Python 3.6 and an older mypy alongside newer versions simultaneously is ... difficult, so... eh. Stub it out with an 'Any' definition to get the CI moving again. Oh well. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Beraldo Leal <bleal@redhat.com> Message-id: 20220110191349.1841027-4-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2022-01-10Python/aqmp: fix type definitions for mypy 0.920John Snow
0.920 (Released 2021-12-15) is not entirely happy with the way that I was defining _FutureT: qemu/aqmp/protocol.py:601: error: Item "object" of the upper bound "Optional[Future[Any]]" of type variable "_FutureT" has no attribute "done" Update it with something a little mechanically simpler that works better across a wider array of mypy versions. Signed-off-by: John Snow <jsnow@redhat.com> Message-id: 20220110191349.1841027-3-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2022-01-10python/aqmp: use absolute import statementJohn Snow
pylint's dependency astroid appears to have bugs in 2.9.1 and 2.9.2 (Dec 31 and Jan 3) that appear to erroneously expect the qemu namespace to have an __init__.py file. astroid 2.9.3 (Jan 9) avoids that problem, but appears to not understand a relative import within a namespace package. Update the relative import - it was worth changing anyway, because these packages will eventually be packaged and distributed separately. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Beraldo Leal <bleal@redhat.com> Message-id: 20220110191349.1841027-2-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2022-01-10Revert "virtio: introduce macro IRTIO_CONFIG_IRQ_IDX"Michael S. Tsirkin
This reverts commit bf1d85c166c19af95dbd27b1faba1d2909732323. Fixes: bf1d85c166 ("virtio: introduce macro IRTIO_CONFIG_IRQ_IDX") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-01-10Revert "virtio-pci: decouple notifier from interrupt process"Michael S. Tsirkin
This reverts commit e3480ef81f6fb61cc9c04e3b5be8b7e84484fc05. Fixes: e3480ef81f ("virtio-pci: decouple notifier from interrupt process") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-01-10Revert "virtio-pci: decouple the single vector from the interrupt process"Michael S. Tsirkin
This reverts commit 316011b8a74e777eb3ba03171cd701a291c28867. Fixes: 316011b8a7 ("virtio-pci: decouple the single vector from the interrupt process") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-01-10Revert "vhost: introduce new VhostOps vhost_set_config_call"Michael S. Tsirkin
This reverts commit 88062372340d33090b7f089ed3b1a00f530a8914. Fixes: 8806237234 ("vhost: introduce new VhostOps vhost_set_config_call") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-01-10Revert "vhost-vdpa: add support for config interrupt"Michael S. Tsirkin
This reverts commit 634f7c89fbd78f57d00d5d6b39c0ade9df1fe27f. Fixes: 634f7c89fb ("vhost-vdpa: add support for config interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-01-10Revert "virtio: add support for configure interrupt"Michael S. Tsirkin
This reverts commit 081f864f56307551f59c5e934e3f30a7290d0faa. Fixes: 081f864f56 ("virtio: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-01-10Revert "vhost: add support for configure interrupt"Michael S. Tsirkin
This reverts commit f7220a7ce21604a4bc6260ccca4dc9068c1f27f2. Fixes: f7220a7ce2 ("vhost: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-01-10Revert "virtio-net: add support for configure interrupt"Michael S. Tsirkin
This reverts commit 497679d51087090d5a22fd265d1b96cf92d49d9d. Fixes: 497679d510 ("virtio-net: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-01-10Revert "virtio-mmio: add support for configure interrupt"Michael S. Tsirkin
This reverts commit d48185f1a40d4e4ed2fa2873a42b2a5eb8748256. Fixes: d48185f1a4 ("virtio-mmio: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-01-10Revert "virtio-pci: add support for configure interrupt"Michael S. Tsirkin
This reverts commit d5d24d859c3957ea1674d0e102f96439cdbfe93a. Fixes: d5d24d859c ("virtio-pci: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-01-10Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-7.0-pull-request' ↵Peter Maydell
into staging M68k pull request 20220109 Add virt compat machine type for 7.0 fix q800 -bios parameter fix VRAM refresh fix M68K_FEATURE_UNALIGNED_DATA feature # gpg: Signature made Sun 09 Jan 2022 11:41:19 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-7.0-pull-request: target/m68k: don't word align SP in stack frame if M68K_FEATURE_UNALIGNED_DATA feature enabled macfb: fix VRAM dirty memory region logging q800: fix segfault with invalid MacROM hw: m68k: Add virt compat machine type for 7.0 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-01-10pseries: Update SLOF firmware imageAlexey Kardashevskiy
The only change is that SLOF is compiled with -mcpu=power5 to make it work on PPC970 too. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
2022-01-09target/m68k: don't word align SP in stack frame if ↵Mark Cave-Ayland
M68K_FEATURE_UNALIGNED_DATA feature enabled Commit a9431a03f7 ("target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature") added a new feature for processors from the 68020 onwards which do not require data accesses to be word aligned. Unfortunately the original commit missed an additional case whereby the SP is still word aligned when setting up an additional format 1 stack frame so add the necessary M68K_FEATURE_UNALIGNED_DATA feature guard. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Fixes: a9431a03f7 ("target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature") Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220108180453.18680-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-09macfb: fix VRAM dirty memory region loggingMark Cave-Ayland
The macfb VRAM memory region was configured with coalescing rather than dirty memory logging enabled, causing some areas of the screen not to redraw after a full screen update. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Fixes: 8ac919a065 ("hw/m68k: add Nubus macfb video card") Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220108164147.30813-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-09q800: fix segfault with invalid MacROMLaurent Vivier
"qemu-system-m68k -M q800 -bios /dev/null" crashes with a segfault in q800_init(). This happens because the code doesn't check that rom_ptr() returned a non-NULL pointer . To avoid NULL pointer, don't allow 0 sized file and use bios_size with rom_ptr(). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/756 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220107105049.961489-1-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-09hw: m68k: Add virt compat machine type for 7.0Laurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20211218114340.1856757-1-laurent@vivier.eu>
2022-01-08Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu into stagingRichard Henderson
bsd-user: arm (32-bit) support This series of patches brings in 32-bit arm support for bsd-user. It implements all the bits needed to do image activation, signal handling, stack management and threading. This allows us to get to the "Hello World" level. The arm and x86 code are now the same as in the bsd-user fork. For full context, the fork is at https://github.com/qemu-bsd-user/qemu-bsd-user/tree/blitz (though the the recent sig{bus,segv} needed updates are incomplete). v5 changes: o Moved to using the CPUArchState typedef and move set_sigtramp_args, get_mcontext, set_mcontext, and get_ucontext_sigreturn prototypes to bsd-user/freebsd/target_os_ucontext.h o Fix issues with arm's set_mcontext related to masking and remove an unnecessary check. We're down to only one hunk needing review: bsd-user/arm/target_arch_signal.c: arm set_mcontext Warnings that should be ignored: o make checkpatch has a couple of complaints about the comments for the signal trampoline, since it's a false positive IMHO. WARNING: Block comments use a leading /* on a separate line + /* 8 */ sys_sigreturn, WARNING: Block comments use a leading /* on a separate line + /* 9 */ sys_exit # gpg: Signature made Fri 07 Jan 2022 11:36:37 PM PST # gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100 # gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown] # gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown] # gpg: aka "Warner Losh <imp@freebsd.org>" [unknown] # gpg: aka "Warner Losh <imp@village.org>" [unknown] # gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100 * tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu: (37 commits) bsd-user: add arm target build bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE bsd-user/arm/signal.c: arm get_ucontext_sigreturn bsd-user/arm/signal.c: arm set_mcontext bsd-user/arm/signal.c: arm get_mcontext bsd-user/arm/signal.c: arm set_sigtramp_args bsd-user/arm/target_arch_signal.h: Define size of *context_t bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signals bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl bsd-user/arm/target_arch_elf.h: arm get hwcap bsd-user/arm/target_arch_elf.h: arm defines for ELF bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space bsd-user/arm/target_arch_reg.h: Implement core dump register copying bsd-user/arm/target_arch_cpu.h: Implement system call dispatch bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into ↵Richard Henderson
staging Second RISC-V PR for QEMU 7.0 - Fix illegal instruction when PMP is disabled - SiFive PDMA 64-bit support - SiFive PLIC cleanups - Mark Hypervisor extension as non experimental - Enable Hypervisor extension by default - Support 32 cores on the virt machine - Corrections for the Vector extension - Experimental support for 128-bit CPUs - stval and mtval support for illegal instructions # gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits) target/riscv: Implement the stval/mtval illegal instruction target/riscv: Fixup setting GVA target/riscv: Set the opcode in DisasContext target/riscv: actual functions to realize crs 128-bit insns target/riscv: modification of the trans_csrxx for 128-bit support target/riscv: helper functions to wrap calls to 128-bit csr insns target/riscv: adding high part of some csrs target/riscv: support for 128-bit M extension target/riscv: support for 128-bit arithmetic instructions target/riscv: support for 128-bit shift instructions target/riscv: support for 128-bit U-type instructions target/riscv: support for 128-bit bitwise instructions target/riscv: accessors to registers upper part and 128-bit load/store target/riscv: moving some insns close to similar insns target/riscv: setup everything for rv64 to support rv128 execution target/riscv: array for the 64 upper bits of 128-bit registers target/riscv: separation of bitwise logic and arithmetic helpers target/riscv: additional macros to check instruction support qemu/int128: addition of div/rem 128-bit operations exec/memop: Adding signed quad and octo defines ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user: add arm target buildWarner Losh
CC: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Acked-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZEWarner Losh
Now that all architecutres define TARGET_[MU]CONTEXT_SIZE, enforce requiring them and always check the sizeof target_{u,m}context_t sizes. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/signal.c: arm get_ucontext_sigreturnWarner Losh
Update ucontext to implement sigreturn. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/signal.c: arm set_mcontextWarner Losh
Move the machine context to the CPU state. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/signal.c: arm get_mcontextWarner Losh
Get the machine context from the CPU state. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/signal.c: arm set_sigtramp_argsWarner Losh
Implement set_sigtramp_args to setup the arguments to the sigtramp calls. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_signal.h: Define size of *context_tWarner Losh
Define the native sizes of mcontext_t and ucontext_t so that the tests in target_os_ucontext.h ensure the size of arm's version of these structures is correct. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signalsWarner Losh
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_signal.h: arm specific signal registers and stackWarner Losh
Defines for registers and stack layout related to signals. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_elf.h: arm get_hwcap2 implWarner Losh
Implement the extended HW capabilities for HWCAP2. Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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