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2021-08-26qapi: add 'not' condition operationMarc-André Lureau
For the sake of completeness, introduce the 'not' condition. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210804083105.97531-10-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Long line broken in tests/qapi-schema/qapi-schema-test.json] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-08-26qapi: Use 'if': { 'any': ... } where appropriateMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Tested-by: John Snow <jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210804083105.97531-9-marcandre.lureau@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-08-26qapi: add 'any' conditionMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210804083105.97531-8-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-08-26qapi: replace if condition list with dict {'all': [...]}Marc-André Lureau
Replace the simple list sugar form with a recursive structure that will accept other operators in the following commits (all, any or not). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210804083105.97531-7-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Accidental code motion undone. Degenerate :forms: comment dropped. Helper _check_if() moved. Error messages tweaked. ui.json updated. Accidental changes to qapi-schema-test.json dropped.] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-08-26qapidoc: introduce QAPISchemaIfCond.docgen()Marc-André Lureau
Instead of building the condition documentation from a list of string, use the result generated from QAPISchemaIfCond.docgen(). This changes the generated documentation from: - COND1, COND2... (where COND1, COND2 are Literal nodes, and ',' is Text) to: - COND1 and COND2 (the whole string as a Literal node) This will allow us to generate more complex conditions in the following patches, such as "(COND1 and COND2) or COND3". Adding back the differentiated formatting is left to the wish list. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210804083105.97531-6-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [TODO comment added] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-08-26qapi: introduce QAPISchemaIfCond.cgen()Marc-André Lureau
Instead of building prepocessor conditions from a list of string, use the result generated from QAPISchemaIfCond.cgen() and hide the implementation details. Note: this patch introduces a minor regression, generating a redundant pair of parenthesis. This is mostly fixed in a later patch in this series ("qapi: replace if condition list with dict [..]") Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210804083105.97531-5-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Commit message tweaked] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-08-26qapi: add QAPISchemaIfCond.is_present()Marc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210804083105.97531-4-marcandre.lureau@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-08-26qapi: wrap Sequence[str] in an objectMarc-André Lureau
Mechanical change, except for a new assertion in QAPISchemaEntity.ifcond(). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210804083105.97531-3-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Rebased with obvious conflicts, commit message adjusted] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-08-26docs: update the documentation upfront about schema configurationMarc-André Lureau
Update the documentation describing the changes in this series. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Tested-by: John Snow <jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210804083105.97531-2-marcandre.lureau@redhat.com> [Rebased with straightforward conflicts] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-08-26qapi: Fix crash on redefinition with a different conditionMarkus Armbruster
QAPISchema._make_implicit_object_type() asserts that when an implicit object type is used multiple times, @ifcond is the same for all uses. It will be for legitimate uses, i.e. simple union branch wrapper types. A comment explains this. The assertion fails when a command or event is redefined with a different condition. The redefinition is an error, but it's flagged only later. Fixing the assertion would complicate matters further. Not worthwhile, drop it instead. We really need to get rid of simple unions. Tweak test case redefined-event to cover redefinition with a different condition. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210806120510.2367124-1-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2021-08-25Merge remote-tracking branch 'remotes/philmd/tags/mips-20210825' into stagingPeter Maydell
MIPS patches queue - minor simplifications in PREF / JR opcodes - merge 32-bit/64-bit Release6 decodetree definitions - converted NEC Vr54xx extension opcodes to decodetree - housekeeping in gen_helper() macros - replace TARGET_WORDS_BIGENDIAN #ifdef'ry by cpu_is_bigendian() - allow Loongson 3A1000 to use up to 48-bit VAddr # gpg: Signature made Wed 25 Aug 2021 12:04:31 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/mips-20210825: (28 commits) target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian() target/mips: Store CP0_Config0 in DisasContext target/mips: Replace GET_LMASK64() macro by get_lmask(64) function target/mips: Replace GET_LMASK() macro by get_lmask(32) function target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers target/mips: Define gen_helper() macros in translate.h target/mips: Use tcg_constant_i32() in generate_exception_err() target/mips: Inline gen_helper_0e0i() target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros target/mips: Simplify gen_helper() macros by using tcg_constant_i32() target/mips: Use tcg_constant_i32() in gen_helper_0e2i() target/mips: Remove gen_helper_1e2i() target/mips: Remove gen_helper_0e3i() target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr target/mips: Document Loongson-3A CPU definitions target/mips: Convert Vr54xx MSA* opcodes to decodetree target/mips: Convert Vr54xx MUL* opcodes to decodetree target/mips: Convert Vr54xx MACC* opcodes to decodetree target/mips: Introduce decodetree structure for NEC Vr54xx extension ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-25Merge remote-tracking branch ↵Peter Maydell
'remotes/thuth-gitlab/tags/pull-request-2021-08-25' into staging * Various updates for the documentation # gpg: Signature made Wed 25 Aug 2021 11:27:27 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/pull-request-2021-08-25: docs: make sphinx-build be quiet by default docs: split the CI docs into two files docs/about/removed-features: Move some CLI options to the right location docs/about: Add the missing release record in the subject docs/about: Unify the subject format docs/about: Remove the duplicated doc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-25target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()Philippe Mathieu-Daudé
Add the inlined cpu_is_bigendian() function in "translate.h". Replace the TARGET_WORDS_BIGENDIAN #ifdef'ry by calls to cpu_is_bigendian(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210818164321.2474534-6-f4bug@amsat.org>
2021-08-25target/mips: Store CP0_Config0 in DisasContextPhilippe Mathieu-Daudé
Most TCG helpers only have access to a DisasContext pointer, not CPUMIPSState. Store a copy of CPUMIPSState::CP0_Config0 in DisasContext so we can access it from TCG helpers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210818164321.2474534-5-f4bug@amsat.org>
2021-08-25target/mips: Replace GET_LMASK64() macro by get_lmask(64) functionPhilippe Mathieu-Daudé
The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. Replace the GET_LMASK() macro by an inlined get_lmask() function, passing CPUMIPSState and the word size as argument. We can remove another use of the TARGET_WORDS_BIGENDIAN definition. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210818215517.2560994-4-f4bug@amsat.org>
2021-08-25target/mips: Replace GET_LMASK() macro by get_lmask(32) functionPhilippe Mathieu-Daudé
The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. Replace the GET_LMASK() macro by an inlined get_lmask() function, passing CPUMIPSState and the word size as argument. We can remove one use of the TARGET_WORDS_BIGENDIAN definition. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210818215517.2560994-3-f4bug@amsat.org>
2021-08-25target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpersPhilippe Mathieu-Daudé
The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. As a first step, inline the GET_OFFSET() macro, calling cpu_is_bigendian() to get the 'direction' of the offset. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210818215517.2560994-2-f4bug@amsat.org>
2021-08-25target/mips: Define gen_helper() macros in translate.hPhilippe Mathieu-Daudé
To be able to split some code calling the gen_helper() macros out of the huge translate.c, we need to define them in the 'translate.h' local header. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-9-f4bug@amsat.org>
2021-08-25target/mips: Use tcg_constant_i32() in generate_exception_err()Philippe Mathieu-Daudé
excp/err are temporaries input, so we can replace tcg_const_i32() calls by tcg_constant_i32() equivalent. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-8-f4bug@amsat.org>
2021-08-25target/mips: Inline gen_helper_0e0i()Philippe Mathieu-Daudé
gen_helper_0e0i() is one-line long and is only used twice: simply inline it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-7-f4bug@amsat.org>
2021-08-25target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macrosPhilippe Mathieu-Daudé
gen_helper_1e1i() is one-line long and is used in one place: simply inline it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-6-f4bug@amsat.org>
2021-08-25target/mips: Simplify gen_helper() macros by using tcg_constant_i32()Philippe Mathieu-Daudé
In all call sites the last argument is always used as a read-only value, so we can replace tcg_const_i32() temporary by tcg_constant_i32(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-5-f4bug@amsat.org>
2021-08-25target/mips: Use tcg_constant_i32() in gen_helper_0e2i()Philippe Mathieu-Daudé
$rt register is used read-only, so we can replace tcg_const_i32() temporary by tcg_constant_i32(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-4-f4bug@amsat.org>
2021-08-25target/mips: Remove gen_helper_1e2i()Philippe Mathieu-Daudé
gen_helper_1e2i() is unused since commit 33a07fa2db6 ("target/mips: reimplement SC instruction emulation and use cmpxchg"), remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-3-f4bug@amsat.org>
2021-08-25target/mips: Remove gen_helper_0e3i()Philippe Mathieu-Daudé
gen_helper_0e3i() is unused since commit 895c2d04359 ("target-mips: switch to AREG0 free mode"), remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-2-f4bug@amsat.org>
2021-08-25target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXTPhilippe Mathieu-Daudé
We already call check_cp1_enabled() earlier in the "pre-conditions" checks for GSLWXC1 and GSLDXC1 in gen_loongson_lsdc2() prologue. Remove the duplicated calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Message-Id: <20210816001031.1720432-1-f4bug@amsat.org>
2021-08-25target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddrPhilippe Mathieu-Daudé
Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter 1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements 48 virtual address bits in each 64-bit segment, not 40. Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Message-Id: <20210813110149.1432692-3-f4bug@amsat.org>
2021-08-25target/mips: Document Loongson-3A CPU definitionsPhilippe Mathieu-Daudé
Document the cores on which each Loongson-3A CPU is based (see commit af868995e1b, "target/mips: Add Loongson-3 CPU definition"). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Message-Id: <20210813110149.1432692-2-f4bug@amsat.org>
2021-08-25target/mips: Convert Vr54xx MSA* opcodes to decodetreePhilippe Mathieu-Daudé
Convert the following Integer Multiply-Accumulate opcodes: * MSAC Multiply, negate, accumulate, and move LO * MSACHI Multiply, negate, accumulate, and move HI * MSACHIU Unsigned multiply, negate, accumulate, and move HI * MSACU Unsigned multiply, negate, accumulate, and move LO Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210808173018.90960-8-f4bug@amsat.org>
2021-08-25target/mips: Convert Vr54xx MUL* opcodes to decodetreePhilippe Mathieu-Daudé
Convert the following Integer Multiply-Accumulate opcodes: * MULHI Multiply and move HI * MULHIU Unsigned multiply and move HI * MULS Multiply, negate, and move LO * MULSHI Multiply, negate, and move HI * MULSHIU Unsigned multiply, negate, and move HI * MULSU Unsigned multiply, negate, and move LO Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210808173018.90960-7-f4bug@amsat.org>
2021-08-25target/mips: Convert Vr54xx MACC* opcodes to decodetreePhilippe Mathieu-Daudé
Convert the following Integer Multiply-Accumulate opcodes: * MACC Multiply, accumulate, and move LO * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO Since all opcodes are generated using the same pattern, we add the gen_helper_mult_acc_t typedef and MULT_ACC() macro to remove boilerplate code. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210808173018.90960-6-f4bug@amsat.org>
2021-08-25target/mips: Introduce decodetree structure for NEC Vr54xx extensionPhilippe Mathieu-Daudé
The decoder is called but doesn't decode anything. This will ease reviewing the next commit. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801235926.3178085-3-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.cPhilippe Mathieu-Daudé
Extract NEC Vr54xx helpers from op_helper.c to a new file: 'vr54xx_helper.c'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201120210844.2625602-14-f4bug@amsat.org>
2021-08-25target/mips: Extract NEC Vr54xx helper definitionsPhilippe Mathieu-Daudé
Extract the NEC Vr54xx helper definitions to 'vendor-vr54xx_helper.h'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201120210844.2625602-15-f4bug@amsat.org>
2021-08-25target/mips: Introduce generic TRANS() macro for decodetree helpersPhilippe Mathieu-Daudé
Plain copy/paste of the TRANS() macro introduced in the PPC commit f2aabda8ac9 ("target/ppc: Move D/DS/X-form integer loads to decodetree") to the MIPS target. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210808173018.90960-2-f4bug@amsat.org>
2021-08-25target/mips: Rename 'rtype' as 'r'Philippe Mathieu-Daudé
We'll soon have more opcode and decoded arguments, and 'rtype' is not very helpful. Naming it simply 'r' ease reviewing the .decode files when we have many opcodes. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-5-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Merge 32-bit/64-bit Release6 decodetree definitionsPhilippe Mathieu-Daudé
We don't need to maintain 2 sets of decodetree definitions. Merge them into a single file. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-4-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Decode vendor extensions before MIPS ISAsPhilippe Mathieu-Daudé
In commit ffc672aa977 ("target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree") we misplaced the decoder call. Move it to the correct place. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-3-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Simplify PREF opcodePhilippe Mathieu-Daudé
check_insn() checks for any bit in the set, and INSN_R5900 is just another bit added to the set. No need to special-case it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-2-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Remove JR opcode unused argumentsPhilippe Mathieu-Daudé
JR opcode (Jump Register) only takes 1 argument, $rs. JALR (Jump And Link Register) takes 3: $rs, $rd and $hint. Commit 6af0bf9c7c3 added their processing into decode_opc() as: case 0x08 ... 0x09: /* Jumps */ gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa); having both opcodes handled in the same function: gen_compute_branch. Per JR encoding, both $rd and $hint ('sa') are decoded as zero. Later this code got extracted to decode_opc_special(), commit 7a387fffce5 used definitions instead of magic values: case OPC_JR ... OPC_JALR: gen_compute_branch(ctx, op1, rs, rd, sa); Finally commit 0aefa33318b moved OPC_JR out of decode_opc_special, to a new 'decode_opc_special_legacy' function: @@ -15851,6 +15851,9 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) + case OPC_JR: + gen_compute_branch(ctx, op1, 4, rs, rd, sa); + break; @@ -15933,7 +15936,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) - case OPC_JR ... OPC_JALR: + case OPC_JALR: gen_compute_branch(ctx, op1, 4, rs, rd, sa); break; Since JR is now handled individually, it is pointless to decode and pass it unused arguments. Replace them by simple zero value to avoid confusion with this opcode. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210730225507.2642827-1-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20210825' into staging target-arm queue: * More MVE emulation work * Implement M-profile trapping on division by zero * kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route() * hw/char/pl011: add support for sending break * fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices * hw/dma/pl330: Add memory region to replace default * sbsa-ref: Rename SBSA_GWDT enum value * fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices * docs: Document how to use gdb with unix sockets # gpg: Signature made Wed 25 Aug 2021 11:34:50 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210825: (44 commits) docs: Document how to use gdb with unix sockets fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices sbsa-ref: Rename SBSA_GWDT enum value hw/dma/pl330: Add memory region to replace default fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices hw/char/pl011: add support for sending break target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route() target/arm: Implement M-profile trapping on division by zero target/arm: Re-indent sdiv and udiv helpers target/arm: Implement MVE interleaving loads/stores target/arm: Implement MVE scatter-gather immediate forms target/arm: Implement MVE scatter-gather insns target/arm: Implement MVE VCTP target/arm: Implement MVE VPNOT target/arm: Implement MVE VMOV to/from 2 general-purpose registers target/arm: Implement MVE VMAXA, VMINA target/arm: Implement MVE VQABS, VQNEG target/arm: Implement MVE saturating doubling multiply accumulates target/arm: Implement MVE VMLA target/arm: Implement MVE VMLADAV and VMLSLDAV ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-25docs: make sphinx-build be quiet by defaultDaniel P. Berrangé
The sphinx-build is fairly verbose spitting out pages of output to the console, which causes errors from other build commands to be scrolled off the top of the terminal. This can leave the mistaken impression that the build passed, when in fact there was a failure. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210812102427.4036399-1-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-25docs: split the CI docs into two filesDaniel P. Berrangé
This splits the CI docs into one file talking about job setup and usage and another file describing provisioning of custom runners. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210812180403.4129067-2-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-25docs/about/removed-features: Move some CLI options to the right locationThomas Huth
Some of the removed CLI options have been added to the wrong section in the "Removed features" chapter - they've been put into the "Related binaries" section instead. Move them now into the correct "System emulator command line arguments" section. Message-Id: <20210818112908.102205-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-08-25docs: Document how to use gdb with unix socketsSebastian Meyer
With gdb 9.0 and better it is possible to connect to a gdbstub over unix sockets, which is better than a TCP socket connection in some situations. The QEMU command line to set this up is non-obvious; document it. Signed-off-by: Sebastian Meyer <meyer@absint.com> Message-id: 162867284829.27377.4784930719350564918-0@git.sr.ht [PMM: Tweaked commit message; adjusted wording in a couple of places; fixed rST formatting issue; moved section up out of the 'advanced debugging options' subsection] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-25fsl-imx7: Instantiate SAI1/2/3 as unimplemented devicesGuenter Roeck
Instantiate SAI1/2/3 as unimplemented devices to avoid Linux kernel crashes such as the following. Unhandled fault: external abort on non-linefetch (0x808) at 0xd19b0000 pgd = (ptrval) [d19b0000] *pgd=82711811, *pte=308a0653, *ppte=308a0453 Internal error: : 808 [#1] SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.14.0-rc5 #1 ... [<c095e974>] (regmap_mmio_write32le) from [<c095eb48>] (regmap_mmio_write+0x3c/0x54) [<c095eb48>] (regmap_mmio_write) from [<c09580f4>] (_regmap_write+0x4c/0x1f0) [<c09580f4>] (_regmap_write) from [<c0959b28>] (regmap_write+0x3c/0x60) [<c0959b28>] (regmap_write) from [<c0d41130>] (fsl_sai_runtime_resume+0x9c/0x1ec) [<c0d41130>] (fsl_sai_runtime_resume) from [<c0942464>] (__rpm_callback+0x3c/0x108) [<c0942464>] (__rpm_callback) from [<c0942590>] (rpm_callback+0x60/0x64) [<c0942590>] (rpm_callback) from [<c0942b60>] (rpm_resume+0x5cc/0x808) [<c0942b60>] (rpm_resume) from [<c0942dfc>] (__pm_runtime_resume+0x60/0xa0) [<c0942dfc>] (__pm_runtime_resume) from [<c0d4231c>] (fsl_sai_probe+0x2b8/0x65c) [<c0d4231c>] (fsl_sai_probe) from [<c0935b08>] (platform_probe+0x58/0xb8) [<c0935b08>] (platform_probe) from [<c0933264>] (really_probe.part.0+0x9c/0x334) [<c0933264>] (really_probe.part.0) from [<c093359c>] (__driver_probe_device+0xa0/0x138) [<c093359c>] (__driver_probe_device) from [<c0933664>] (driver_probe_device+0x30/0xc8) [<c0933664>] (driver_probe_device) from [<c0933c88>] (__driver_attach+0x90/0x130) [<c0933c88>] (__driver_attach) from [<c0931060>] (bus_for_each_dev+0x78/0xb8) [<c0931060>] (bus_for_each_dev) from [<c093254c>] (bus_add_driver+0xf0/0x1d8) [<c093254c>] (bus_add_driver) from [<c0934a30>] (driver_register+0x88/0x118) [<c0934a30>] (driver_register) from [<c01022c0>] (do_one_initcall+0x7c/0x3a4) [<c01022c0>] (do_one_initcall) from [<c1601204>] (kernel_init_freeable+0x198/0x22c) [<c1601204>] (kernel_init_freeable) from [<c0f5ff2c>] (kernel_init+0x10/0x128) [<c0f5ff2c>] (kernel_init) from [<c010013c>] (ret_from_fork+0x14/0x38) Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20210810175607.538090-1-linux@roeck-us.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-25sbsa-ref: Rename SBSA_GWDT enum valueEduardo Habkost
The SBSA_GWDT enum value conflicts with the SBSA_GWDT() QOM type checking helper, preventing us from using a OBJECT_DEFINE* or DEFINE_INSTANCE_CHECKER macro for the SBSA_GWDT() wrapper. If I understand the SBSA 6.0 specification correctly, the signal being connected to IRQ 16 is the WS0 output signal from the Generic Watchdog. Rename the enum value to SBSA_GWDT_WS0 to be more explicit and avoid the name conflict. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-id: 20210806023119.431680-1-ehabkost@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-25hw/dma/pl330: Add memory region to replace defaultWen, Jianxian
Add property memory region which can connect with IOMMU region to support SMMU translate. Signed-off-by: Jianxian Wen <jianxian.wen@verisilicon.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 4C23C17B8E87E74E906A25A3254A03F4FA1FEC31@SHASXM03.verisilicon.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-25fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devicesGuenter Roeck
Instantiate SAI1/2/3 and ASRC as unimplemented devices to avoid random Linux kernel crashes, such as Unhandled fault: external abort on non-linefetch (0x808) at 0xd1580010 pgd = (ptrval) [d1580010] *pgd=8231b811, *pte=02034653, *ppte=02034453 Internal error: : 808 [#1] SMP ARM ... [<c095e974>] (regmap_mmio_write32le) from [<c095eb48>] (regmap_mmio_write+0x3c/0x54) [<c095eb48>] (regmap_mmio_write) from [<c09580f4>] (_regmap_write+0x4c/0x1f0) [<c09580f4>] (_regmap_write) from [<c095837c>] (_regmap_update_bits+0xe4/0xec) [<c095837c>] (_regmap_update_bits) from [<c09599b4>] (regmap_update_bits_base+0x50/0x74) [<c09599b4>] (regmap_update_bits_base) from [<c0d3e9e4>] (fsl_asrc_runtime_resume+0x1e4/0x21c) [<c0d3e9e4>] (fsl_asrc_runtime_resume) from [<c0942464>] (__rpm_callback+0x3c/0x108) [<c0942464>] (__rpm_callback) from [<c0942590>] (rpm_callback+0x60/0x64) [<c0942590>] (rpm_callback) from [<c0942b60>] (rpm_resume+0x5cc/0x808) [<c0942b60>] (rpm_resume) from [<c0942dfc>] (__pm_runtime_resume+0x60/0xa0) [<c0942dfc>] (__pm_runtime_resume) from [<c0d3ecc4>] (fsl_asrc_probe+0x2a8/0x708) [<c0d3ecc4>] (fsl_asrc_probe) from [<c0935b08>] (platform_probe+0x58/0xb8) [<c0935b08>] (platform_probe) from [<c0933264>] (really_probe.part.0+0x9c/0x334) [<c0933264>] (really_probe.part.0) from [<c093359c>] (__driver_probe_device+0xa0/0x138) [<c093359c>] (__driver_probe_device) from [<c0933664>] (driver_probe_device+0x30/0xc8) [<c0933664>] (driver_probe_device) from [<c0933c88>] (__driver_attach+0x90/0x130) [<c0933c88>] (__driver_attach) from [<c0931060>] (bus_for_each_dev+0x78/0xb8) [<c0931060>] (bus_for_each_dev) from [<c093254c>] (bus_add_driver+0xf0/0x1d8) [<c093254c>] (bus_add_driver) from [<c0934a30>] (driver_register+0x88/0x118) [<c0934a30>] (driver_register) from [<c01022c0>] (do_one_initcall+0x7c/0x3a4) [<c01022c0>] (do_one_initcall) from [<c1601204>] (kernel_init_freeable+0x198/0x22c) [<c1601204>] (kernel_init_freeable) from [<c0f5ff2c>] (kernel_init+0x10/0x128) [<c0f5ff2c>] (kernel_init) from [<c010013c>] (ret_from_fork+0x14/0x38) or Unhandled fault: external abort on non-linefetch (0x808) at 0xd19b0000 pgd = (ptrval) [d19b0000] *pgd=82711811, *pte=308a0653, *ppte=308a0453 Internal error: : 808 [#1] SMP ARM ... [<c095e974>] (regmap_mmio_write32le) from [<c095eb48>] (regmap_mmio_write+0x3c/0x54) [<c095eb48>] (regmap_mmio_write) from [<c09580f4>] (_regmap_write+0x4c/0x1f0) [<c09580f4>] (_regmap_write) from [<c0959b28>] (regmap_write+0x3c/0x60) [<c0959b28>] (regmap_write) from [<c0d41130>] (fsl_sai_runtime_resume+0x9c/0x1ec) [<c0d41130>] (fsl_sai_runtime_resume) from [<c0942464>] (__rpm_callback+0x3c/0x108) [<c0942464>] (__rpm_callback) from [<c0942590>] (rpm_callback+0x60/0x64) [<c0942590>] (rpm_callback) from [<c0942b60>] (rpm_resume+0x5cc/0x808) [<c0942b60>] (rpm_resume) from [<c0942dfc>] (__pm_runtime_resume+0x60/0xa0) [<c0942dfc>] (__pm_runtime_resume) from [<c0d4231c>] (fsl_sai_probe+0x2b8/0x65c) [<c0d4231c>] (fsl_sai_probe) from [<c0935b08>] (platform_probe+0x58/0xb8) [<c0935b08>] (platform_probe) from [<c0933264>] (really_probe.part.0+0x9c/0x334) [<c0933264>] (really_probe.part.0) from [<c093359c>] (__driver_probe_device+0xa0/0x138) [<c093359c>] (__driver_probe_device) from [<c0933664>] (driver_probe_device+0x30/0xc8) [<c0933664>] (driver_probe_device) from [<c0933c88>] (__driver_attach+0x90/0x130) [<c0933c88>] (__driver_attach) from [<c0931060>] (bus_for_each_dev+0x78/0xb8) [<c0931060>] (bus_for_each_dev) from [<c093254c>] (bus_add_driver+0xf0/0x1d8) [<c093254c>] (bus_add_driver) from [<c0934a30>] (driver_register+0x88/0x118) [<c0934a30>] (driver_register) from [<c01022c0>] (do_one_initcall+0x7c/0x3a4) [<c01022c0>] (do_one_initcall) from [<c1601204>] (kernel_init_freeable+0x198/0x22c) [<c1601204>] (kernel_init_freeable) from [<c0f5ff2c>] (kernel_init+0x10/0x128) [<c0f5ff2c>] (kernel_init) from [<c010013c>] (ret_from_fork+0x14/0x38) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20210810160318.87376-1-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-25hw/char/pl011: add support for sending breakJan Luebbe
Break events are currently only handled by chardev/char-serial.c, so we just ignore errors, which results in no behaviour change for other chardevs. Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Message-id: 20210806144700.3751979-1-jlu@pengutronix.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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