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2015-10-24ivshmem: improve debug messagesMarc-André Lureau
Some misc improvements to ivshmem debug. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: remove max_peer fieldMarc-André Lureau
max_peer isn't really useful, it tracks the maximum received VM id, but that quickly matches nb_peers, the size of the peers array. Since VM come and go, there might be sparse peers so it doesn't help much in general to have this value around. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: initialize max_peer to -1Marc-André Lureau
There is no peer when device is initialized, do not let doorbell for inexisting peer 0. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: remove useless ivshmem_update_irq() val argumentMarc-André Lureau
val isn't used in ivshmem_update_irq() function. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: allocate eventfds in resize_peers()Marc-André Lureau
It simplifies a bit the code to allocate the array when setting the number of peers instead of lazily when receiving the first vector. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: simplify around increase_dynamic_storage()Marc-André Lureau
Set the number of peers and array allocation in a single place. Rename to better reflect the function content. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: limit maximum number of peers to G_MAXUINT16Marc-André Lureau
Limit the maximum number of peers to MAXUINT16. This is more realistic and better matches the limit of the doorbell register. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: remove last exit(1)Marc-André Lureau
Failing to create a chardev shouldn't be fatal. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: more qdev conversionMarc-André Lureau
Use the latest qemu device modeling API, in particular, convert to realize to fix the error handling; right now a botched device_add ivhsmem command kills the VM. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: remove useless doorbell fieldMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: remove superflous ivshmem_attr fieldMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: remove unnecessary dup()Marc-André Lureau
qemu_chr_fe_get_msgfd() transfers ownership, there is no need to dup the fd. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: factor out the incoming fifo handlingMarc-André Lureau
Make a new function fifo_update_and_get() that can be reused by other functions (in next commits). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivshmem: fix number of bytes to push to fifoMarc-André Lureau
If the fifo has 0 bytes, and the read is of size 1, the call to fifo8_push_all() will copy off boundary data. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24ivhsmem: read do not accept more than sizeof(long)Marc-André Lureau
ivshmem_read() only reads sizeof(long) from the input buffer. Accepting more could lead to fifo8 abort() on 32bit systems if fifo is not empty. A following patch will change the protocol to 64-bit little-endian instead. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24msix: add VMSTATE_MSIX_TESTMarc-André Lureau
ivshmem is going to use MSIX state conditionally. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24char: add qemu_chr_free()Marc-André Lureau
If a chardev is allowed to be created outside of QMP, then it must be also possible to free it. This is useful for ivshmem that creates chardev anonymously and must be able to free them. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2015-10-24tests: Add ivshmem qtestAndreas Färber
Note that it launches two instances, as sharing memory is the purpose of ivshmem. Cc: Cam Macdonell <cam@cs.ualberta.ca> Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de> [ Remove Nahanni codename, add test to pci set - Marc-André ] Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
2015-10-24config: enable ivshmem on POSIXMarc-André Lureau
ivshmem doesn't actually require kvm, so enable it when POSIX is enabled. (it is required however when ioeventfd is enabled) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
2015-10-23Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell
staging X86 queue, 2015-10-23 # gpg: Signature made Fri 23 Oct 2015 16:30:58 BST using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" * remotes/ehabkost/tags/x86-pull-request: vl: trivial: minor tweaks to a max-cpu error msg target-i386: Use 1UL for bit shift target-i386: Add DE to TCG_FEATURES target-i386: Ensure always-1 bits on DR6 can't be cleared target-i386: Check CR4[DE] for processing DR4/DR5 target-i386: Handle I/O breakpoints target-i386: Optimize setting dr[0-3] target-i386: Move hw_*breakpoint_* functions target-i386: Ensure bit 10 on DR7 is never cleared target-i386: Re-introduce optimal breakpoint removal target-i386: Introduce cpu_x86_update_dr7 target-i386: Disable cache info passthrough by default target-i386: allow any alignment for SMBASE Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-23vl: trivial: minor tweaks to a max-cpu error msgAndrew Jones
Signed-off-by: Andrew Jones <drjones@redhat.com>
2015-10-23target-i386: Use 1UL for bit shiftEduardo Habkost
Fix undefined behavior detected by clang runtime check: qemu/target-i386/cpu.c:1494:15: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' While doing that, add extra parenthesis for clarity. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23target-i386: Add DE to TCG_FEATURESEduardo Habkost
Now DE is supported by TCG so it can be enabled in CPUID bits. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23target-i386: Ensure always-1 bits on DR6 can't be clearedEduardo Habkost
Bits 4-11 and 16-31 on DR6 are documented as always 1, so ensure they can't be cleared by software. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23target-i386: Check CR4[DE] for processing DR4/DR5Richard Henderson
Introduce helper_get_dr so that we don't have to put CR4[DE] into the scarce HFLAGS resource. At the same time, rename helper_movl_drN_T0 to helper_set_dr and set the helper flags. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23target-i386: Handle I/O breakpointsEduardo Habkost
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23target-i386: Optimize setting dr[0-3]Richard Henderson
If the debug register is not enabled, we need do nothing besides update the register. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23target-i386: Move hw_*breakpoint_* functionsRichard Henderson
They're only used from bpt_helper.c now. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23target-i386: Ensure bit 10 on DR7 is never clearedEduardo Habkost
Bit 10 of DR7 is documented as always set to 1, so ensure that's always the case. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23target-i386: Re-introduce optimal breakpoint removalRichard Henderson
Before the last patch, we had an efficient loop that disabled local breakpoints on task switch. Re-add that, but in a more general way that handles changes to the global enable bits too. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23target-i386: Introduce cpu_x86_update_dr7Richard Henderson
This moves the last of the iteration over breakpoints into the bpt_helper.c file. This also allows us to make several breakpoint functions static. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23target-i386: Disable cache info passthrough by defaultEduardo Habkost
The host cache information may not make sense for the guest if the VM CPU topology doesn't match the host CPU topology. To make sure we won't expose broken cache information to the guest, disable cache info passthrough by default, and add a new "host-cache-info" property that can be used to enable the old behavior for users that really need it. Cc: Benoît Canet <benoit@irqsave.net> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23target-i386: allow any alignment for SMBASEPaolo Bonzini
Processors up to the Pentium (says Bochs---I do not have old enough manuals) require a 32KiB alignment for the SMBASE, but newer processors do not need that, and Tiano Core will use non-aligned SMBASE values. Reported-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-23Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2015-10-23-tag' ↵Peter Maydell
into staging qemu-ga patch queue * unbreak qga-test unit test on travis-ci systems by not assuming a disk-based filesystem must be present # gpg: Signature made Fri 23 Oct 2015 15:01:47 BST using RSA key ID F108B584 # gpg: Good signature from "Michael Roth <flukshun@gmail.com>" # gpg: aka "Michael Roth <mdroth@utexas.edu>" # gpg: aka "Michael Roth <mdroth@linux.vnet.ibm.com>" * remotes/mdroth/tags/qga-pull-2015-10-23-tag: tests: test-qga, loosen assumptions about host filesystems Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-23tests: test-qga, loosen assumptions about host filesystemsMichael Roth
QGA skips pseudo-filesystems when querying filesystems via guest-get-fsinfo. On some hosts, such as travis-ci which uses containers with simfs filesystems, QGA might not report *any* filesystems. Our test case assumes there would be at least one, leading to false error messages in these situations. Instead, sanity-check values iff we get at least one filesystem. Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
2015-10-23Merge remote-tracking branch 'remotes/dgibson/tags/ppc-next-20151023' into ↵Peter Maydell
staging ppc patch queue - 2015-10-23 sPAPR highlights: * Allow VFIO devices on the spapr-pci-host-bridge * Allow virtio VGA * Safer handling of HTAB allocation * ibm,pa-features device tree property non-sPAPR highlights: * Categorization of many ppc specific devices in help output * Tweaks to MMU type constants # gpg: Signature made Fri 23 Oct 2015 07:27:56 BST using RSA key ID 20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-next-20151023: (21 commits) prep: do not use CPU_LOG_IOPORT, convert to tracepoints openpic: add to misc category macio-nvram: add to misc category macio: add to bridge category uninorth: add to bridge category macio-ide: add to storage category cuda: add to bridge category grackle: add to bridge category escc: add to input category cmd646: add to storage category adb: add to input category ppc/spapr: Add "ibm,pa-features" property to the device-tree ppc: Add mmu_model defines for arch 2.03 and 2.07 hw/scsi/spapr_vscsi: Remove superfluous memset spapr_pci: Allow VFIO devices to work on the normal PCI host bridge spapr_iommu: Provide a function to switch a TCE table to allowing VFIO spapr_iommu: Rename vfio_accel parameter spapr_pci: Allow PCI host bridge DMA window to be configured spapr: Add "slb-size" property to CPU device tree nodes spapr: Abort when HTAB of requested size isn't allocated ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-23Merge remote-tracking branch ↵Peter Maydell
'remotes/berrange/tags/qcrypto-fixes-pull-20151022-2' into staging Merge qcrypto-fixes 2015/10/22 # gpg: Signature made Thu 22 Oct 2015 19:03:45 BST using RSA key ID 15104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" * remotes/berrange/tags/qcrypto-fixes-pull-20151022-2: configure: avoid polluting global CFLAGS with tasn1 flags crypto: add sanity checking of plaintext/ciphertext length crypto: don't let builtin aes crash if no IV is provided crypto: allow use of nettle/gcrypt to be selected explicitly Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-23Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
vhost: build fix Fix build breakages when using older gcc. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Thu 22 Oct 2015 20:36:07 BST using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" * remotes/mst/tags/for_upstream: vhost-user: fix up rhel6 build Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-23prep: do not use CPU_LOG_IOPORT, convert to tracepointsPaolo Bonzini
These messages are disabled by default; a perfect usecase for tracepoints. Convert them over. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-23openpic: add to misc categoryLaurent Vivier
openpic is a programmable interrupt controller, so add it to the misc category. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-23macio-nvram: add to misc categoryLaurent Vivier
The macio nvram is a non volatile RAM, so add it the misc category. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-23macio: add to bridge categoryLaurent Vivier
macio is a bridge between the PCI bus and the Mac nvram, IDE controller and PIC, so add it to the bridge category. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-23uninorth: add to bridge categoryLaurent Vivier
Uninorth is the mac99 PCI host controller, so add it to the bridge category. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-23macio-ide: add to storage categoryLaurent Vivier
macio-ide is an IDE controller, so add it to the storage category. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-23cuda: add to bridge categoryLaurent Vivier
Cuda is a bridge between PowerMac system bus and the ADB controller, real-time clock, pram and the power management unit. So add it to the bridge category. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-23grackle: add to bridge categoryLaurent Vivier
Grackle is the PCI host controller of oldworld powermac, so add it to the bridge category. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-23escc: add to input categoryLaurent Vivier
ESCC is a serial port controller, so add it to the input category. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-23cmd646: add to storage categoryLaurent Vivier
cmd646 is an IDE controller, so add it to the storage category. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-23adb: add to input categoryLaurent Vivier
The Apple Desktop Bus is used to connect a keyboard and a mouse, so add it to the input category. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-23ppc/spapr: Add "ibm,pa-features" property to the device-treeBenjamin Herrenschmidt
LoPAPR defines a "ibm,pa-features" per-CPU device tree property which describes extended features of the Processor Architecture. This adds the property to the device tree. At the moment this is the copy of what pHyp advertises except "I=1 (cache inhibited) Large Pages" which is enabled for TCG and disabled when running under HV KVM host with 4K system page size. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [aik: rebased, changed commit log, moved ci_large_pages initialization, renamed pa_features arrays] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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