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2021-06-28pc-bios: Update the palcode-clipper imageRichard Henderson
Build a new palcode image with Jason Thorpe's patches to support NetBSD. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-28hw/alpha: Provide a PCI-ISA bridge device nodeJason Thorpe
- Move initialization of the ISA bus from typhoon_init() to clipper_init(); this apsect of device topology is really associated with the individual model, not the core logic chipset. typhoon_init() now returns the IRQ to use for the output of the ISA PIC. - In clipper_init(), instantiate an i82378 instance, and connect its PIC output to the ISA IRQ input provided by typhoon_init(). Remove the explicit instantiations of i8254 and i82374, as these devices are subsumed by the i82378. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Jason Thorpe <thorpej@me.com> Message-Id: <20210616141538.25436-1-thorpej@me.com> [rth: Remove direct dependencies on i82374, i8254, i8259.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-28hw/alpha: Provide console information to the PALcode at start-upJason Thorpe
Redefine the a2 register passed by Qemu at start-up to also include some configuration flags, in addition to the CPU count, and define a flag to mirror the "-nographic" option. Signed-off-by: Jason Thorpe <thorpej@me.com> Message-Id: <20210613211549.18094-5-thorpej@me.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-28hw/alpha: Set minimum PCI device ID to 1 to match Clipper IRQ mappingsJason Thorpe
Since we are emulating a Clipper device topology, we need to set the minimum PCI device ID to 1, as there is no IRQ mapping for a device at ID 0 (see sys_dp264.c:clipper_map_irq()). - Add a 'devfn_min' argument to typhoon_init(). Pass that argument along to pci_register_root_bus(). - In clipper_init(), pass PCI_DEVFN(1, 0) as the minimum PCI device ID/function. Signed-off-by: Jason Thorpe <thorpej@me.com> Message-Id: <20210613211549.18094-3-thorpej@me.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-28Merge remote-tracking branch 'remotes/philmd/tags/mips-20210625' into stagingPeter Maydell
MIPS patches queue Various fixes: - Potential integer overflow (CID 1452921) - Invalid emulation of nanoMIPS BPOSGE32 opcode - Missing exception when DINSV opcode used with DSP disabled - Do not abort but emit exception for invalid BRANCH opcodes - TCG temporary leaks Housekeeping: - Remove dead code / comments - Restrict few files to TCG, declarations to sysemu - Merge MSA32 and MSA64 decodetree definitions # gpg: Signature made Fri 25 Jun 2021 10:22:20 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/mips-20210625: target/mips: Merge msa32/msa64 decodetree definitions target/mips: Remove pointless gen_msa() target/mips: Optimize regnames[] arrays target/mips: Constify host_to_mips_errno[] target/mips: fix emulation of nanoMIPS BPOSGE32 instruction target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases target/mips: Remove SmartMIPS / MDMX unuseful comments target/mips: Restrict some system specific declarations to sysemu target/mips: Move translate.h to tcg/ sub directory target/mips: Move TCG trace events to tcg/ sub directory target/mips: Do not abort on invalid instruction target/mips: Raise exception when DINSV opcode used with DSP disabled target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insn target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn() target/mips: Fix potential integer overflow (CID 1452921) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-25Merge remote-tracking branch ↵Peter Maydell
'remotes/kraxel/tags/audio-20210624-pull-request' into staging audio: bugfixes # gpg: Signature made Thu 24 Jun 2021 13:16:16 BST # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/audio-20210624-pull-request: hw/audio/sb16: Restrict I/O sampling rate range for command 41h/42h coreaudio: Lock only the buffer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-25Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20210624-2' into staging Third RISC-V PR for 6.1 release - Fix MISA in the DisasContext - Fix GDB CSR XML generation - QOMify the SiFive UART - Add support for the OpenTitan timer # gpg: Signature made Thu 24 Jun 2021 13:00:26 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210624-2: hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer hw/timer: Initial commit of Ibex Timer hw/char/ibex_uart: Make the register layout private hw/char: QOMify sifive_uart hw/char: Consistent function names for sifive_uart target/riscv: gdbstub: Fix dynamic CSR XML generation target/riscv: Use target_ulong for the DisasContext misa Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-25Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2021-06-24' ↵Peter Maydell
into staging Block patch: - Fix Coverity complaint in block/snapshot.c # gpg: Signature made Thu 24 Jun 2021 12:42:28 BST # gpg: using RSA key 91BEB60A30DB3E8857D11829F407DB0061D5CF40 # gpg: issuer "mreitz@redhat.com" # gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full] # Primary key fingerprint: 91BE B60A 30DB 3E88 57D1 1829 F407 DB00 61D5 CF40 * remotes/maxreitz/tags/pull-block-2021-06-24: block/snapshot: Clarify goto fallback behavior Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-25Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-updates-250621-1' into staging A few miscellaneous fixes - tweak tcg/kvm based GIC tests - add header to MTTCG docs - cleanup checkpatch handling - GitLab feature and bug request templates - symbol resolution helper for plugin API - skip hppa/s390x signals test until fixes arrive # gpg: Signature made Fri 25 Jun 2021 10:10:57 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-updates-250621-1: plugins/api: expose symbol lookup to plugins tests/tcg: skip the signals test for hppa/s390x for now GitLab: Add "Feature Request" issue template. GitLab: Add "Bug" issue reporting template scripts/checkpatch: roll diff tweaking into checkpatch itself docs/devel: Add a single top-level header to MTTCG's doc tests/acceptance: tweak the tcg/kvm tests for virt Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-25plugins/api: expose symbol lookup to pluginsAlex Bennée
This is a quality of life helper for plugins so they don't need to re-implement symbol lookup when dumping an address. The strings are constant so don't need to be duplicated. One minor tweak is to return NULL instead of a zero length string to show lookup failed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Message-Id: <20210608040532.56449-2-ma.mandourr@gmail.com> Message-Id: <20210623102749.25686-8-alex.bennee@linaro.org>
2021-06-25tests/tcg: skip the signals test for hppa/s390x for nowAlex Bennée
There are fixes currently in flight but as this is getting in the way of a green CI we might as well skip for now. For reference the fix series are: linux-user: Move signal trampolines to new page 20210616011209.1446045-1-richard.henderson@linaro.org and linux-user: Load a vdso for x86_64 and hppa 20210619034329.532318-1-richard.henderson@linaro.org Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Cc: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210623102749.25686-7-alex.bennee@linaro.org>
2021-06-25GitLab: Add "Feature Request" issue template.John Snow
Based on Peter Krempa's libvirt template, feature.md. Signed-off-by: John Snow <jsnow@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> CC: Peter Krempa <pkrempa@redhat.com> Message-Id: <20210607153155.1760158-3-jsnow@redhat.com> Message-Id: <20210623102749.25686-6-alex.bennee@linaro.org>
2021-06-25GitLab: Add "Bug" issue reporting templateJohn Snow
Based loosely on libvirt's template, written by Peter Krempa. Signed-off-by: John Snow <jsnow@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> CC: Peter Krempa <pkrempa@redhat.com> Message-Id: <20210607153155.1760158-2-jsnow@redhat.com> Message-Id: <20210623102749.25686-5-alex.bennee@linaro.org>
2021-06-25scripts/checkpatch: roll diff tweaking into checkpatch itselfAlex Bennée
Rather than relying on external tweaks lets just do it inside checkpatch's direct commitish handling which is QEMU specific code anyway. Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20210623102749.25686-4-alex.bennee@linaro.org>
2021-06-25docs/devel: Add a single top-level header to MTTCG's docLuis Pires
Without a single top-level header in the .rst file, the index ended up linking to all of the top-level headers separately. Now the index links to the top-level header at the beginning of the document and any inner headers are correctly linked as sub-items in the index. Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210528123526.144065-1-luis.pires@eldorado.org.br> Message-Id: <20210623102749.25686-3-alex.bennee@linaro.org>
2021-06-25tests/acceptance: tweak the tcg/kvm tests for virtAlex Bennée
Really it's only TCG that can select which GIC model you want, KVM guests should always be using the "host" version of the GIC for which QEMU already provides a handy shortcut. Make the KVM test use this and split the TCG test into it's two versions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210623102749.25686-2-alex.bennee@linaro.org>
2021-06-25Merge remote-tracking branch 'remotes/kraxel/tags/ui-20210624-pull-request' ↵Peter Maydell
into staging ui: better cocoa integration (ui info + clipboard). ui: add lang1+lang2 keys, fixes, doc updates. # gpg: Signature made Thu 24 Jun 2021 09:32:36 BST # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20210624-pull-request: ui: Make the DisplayType enum entries conditional Add display suboptions to man pages input: Add lang1 and lang2 to QKeyCode ui/cocoa: Add clipboard support ui/cocoa: Set UI information Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-24target/mips: Merge msa32/msa64 decodetree definitionsPhilippe Mathieu-Daudé
We don't need to maintain 2 sets of decodetree definitions. Merge them into a single file. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174636.2902654-3-f4bug@amsat.org>
2021-06-24target/mips: Remove pointless gen_msa()Philippe Mathieu-Daudé
Only trans_MSA() calls gen_msa(), inline it to simplify. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174636.2902654-2-f4bug@amsat.org>
2021-06-24target/mips: Optimize regnames[] arraysPhilippe Mathieu-Daudé
Since all entries are no more than 3/4/6 bytes (including nul terminator), can save space and pie runtime relocations by declaring regnames[] as array of 3/4/6 const char. Inspired-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-10-f4bug@amsat.org>
2021-06-24target/mips: Constify host_to_mips_errno[]Philippe Mathieu-Daudé
Keep host_to_mips_errno[] in .rodata by marking the array const. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-9-f4bug@amsat.org>
2021-06-24target/mips: fix emulation of nanoMIPS BPOSGE32 instructionAleksandar Rikalo
Per the "MIPS® Architecture Extension: nanoMIPS32 DSP Technical Reference Manual — Revision 0.04" p. 88 "BPOSGE32C", offset argument (imm) should be left-shifted first. This change was tested against test_dsp_r1_bposge32.c DSP test. Reported-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Filip Vidojevic <filip.vidojevic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <VI1PR0302MB34869449EE56F226FC3C21129C309@VI1PR0302MB3486.eurprd03.prod.outlook.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-06-24target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful casesPhilippe Mathieu-Daudé
These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have been added commit 3c824109da0 ("target-mips: microMIPS ASE support"). More than 11 years later it is safe to assume there won't be added soon. The cases fall back to the default which generates a RESERVED INSTRUCTION, so it is safe to remove them. Functionally speaking, the patch is a no-op. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-8-f4bug@amsat.org>
2021-06-24target/mips: Remove SmartMIPS / MDMX unuseful commentsPhilippe Mathieu-Daudé
These placeholder comments for SmartMIPS and MDMX extensions have been added commit 3c824109da0 ("target-mips: microMIPS ASE support"). More than 11 years later it is safe to assume there won't be added soon, so remove these unuseful comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-7-f4bug@amsat.org>
2021-06-24target/mips: Restrict some system specific declarations to sysemuPhilippe Mathieu-Daudé
Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI and SAAR CP0 registers") declared itc_reconfigure() in public namespace, while it is restricted to system emulation. Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to system emulation, but forgot to restrict its declaration. To avoid polluting user-mode emulation with these declarations, restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ fields from CPUMIPSState. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-6-f4bug@amsat.org>
2021-06-24target/mips: Move translate.h to tcg/ sub directoryPhilippe Mathieu-Daudé
We moved various TCG source files in commit a2b0a27d33e ("target/mips: Move TCG source files under tcg/ sub directory") but forgot to move the header declaring their prototypes. Do it now, since all it declares is TCG specific. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-5-f4bug@amsat.org>
2021-06-24target/mips: Move TCG trace events to tcg/ sub directoryPhilippe Mathieu-Daudé
Commit a2b0a27d33e ("target/mips: Move TCG source files under tcg/ sub directory") forgot to move the trace-event file. As it only contains TCG events, move it for consistency. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-4-f4bug@amsat.org>
2021-06-24target/mips: Do not abort on invalid instructionPhilippe Mathieu-Daudé
On real hardware an invalid instruction doesn't halt the world, but usually triggers a RESERVED INSTRUCTION exception. TCG guest code shouldn't abort QEMU anyway. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-2-f4bug@amsat.org>
2021-06-24target/mips: Raise exception when DINSV opcode used with DSP disabledPhilippe Mathieu-Daudé
Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02, Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module": If the Module/ASE is not implemented, executing such an instruction must cause a Reserved Instruction Exception. The DINSV instruction lists the following exceptions: - Reserved Instruction - DSP Disabled If the MIPS core doesn't support the DSP module, or the DSP is disabled, do not handle the '$rt = $0' case as a no-op but raise the proper exception instead. Cc: Jia Liu <proljc@gmail.com> Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210529165443.1114402-1-f4bug@amsat.org>
2021-06-24target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insnPhilippe Mathieu-Daudé
Fix multiple TCG temporary leaks in gen_pool32a5_nanomips_insn(). Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part 1") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-3-f4bug@amsat.org>
2021-06-24target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn()Philippe Mathieu-Daudé
Fix a pair of TCG temporary leak when translating nanoMIPS SHILO opcode. Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210530094538.1275329-1-f4bug@amsat.org>
2021-06-24target/mips: Fix potential integer overflow (CID 1452921)Philippe Mathieu-Daudé
Use the BIT_ULL() macro to ensure we use 64-bit arithmetic. This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN): CID 1452921: Integer handling issues: Potentially overflowing expression "1 << w" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). Fixes: 074cfcb4dae ("target/mips: Implement hardware page table walker") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210505215119.1517465-1-f4bug@amsat.org>
2021-06-24Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20210624' into staging target-arm queue: * Don't require 'virt' board to be compiled in for ACPI GHES code * docs: Document which architecture extensions we emulate * Fix bugs in M-profile FPCXT_NS accesses * First slice of MVE patches * Implement MTE3 * docs/system: arm: Add nRF boards description # gpg: Signature made Thu 24 Jun 2021 14:59:16 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210624: (57 commits) docs/system: arm: Add nRF boards description target/arm: Implement MTE3 target/arm: Make VMOV scalar <-> gpreg beatwise for MVE target/arm: Implement MVE VADDV target/arm: Implement MVE VHCADD target/arm: Implement MVE VCADD target/arm: Implement MVE VADC, VSBC target/arm: Implement MVE VRHADD target/arm: Implement MVE VQDMULL (vector) target/arm: Implement MVE VQDMLSDH and VQRDMLSDH target/arm: Implement MVE VQDMLADH and VQRDMLADH target/arm: Implement MVE VRSHL target/arm: Implement MVE VSHL insn target/arm: Implement MVE VQRSHL target/arm: Implement MVE VQSHL (vector) target/arm: Implement MVE VQADD, VQSUB (vector) target/arm: Implement MVE VQDMULH, VQRDMULH (vector) target/arm: Implement MVE VQDMULL scalar target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) target/arm: Implement MVE VQADD and VQSUB ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-24docs/system: arm: Add nRF boards descriptionAlexandre Iooss
This adds the target guide for BBC Micro:bit. Information is taken from https://wiki.qemu.org/Features/MicroBit and from hw/arm/nrf51_soc.c. Signed-off-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20210621075625.540471-1-erdnaxe@crans.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-24target/arm: Implement MTE3Peter Collingbourne
MTE3 introduces an asymmetric tag checking mode, in which loads are checked synchronously and stores are checked asynchronously. Add support for it. Signed-off-by: Peter Collingbourne <pcc@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210616195614.11785-1-pcc@google.com [PMM: Add line to emulation.rst] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-24target/arm: Make VMOV scalar <-> gpreg beatwise for MVEPeter Maydell
In a CPU with MVE, the VMOV (vector lane to general-purpose register) and VMOV (general-purpose register to vector lane) insns are not predicated, but they are subject to beatwise execution if they are not in an IT block. Since our implementation always executes all 4 beats in one tick, this means only that we need to handle PSR.ECI: * we must do the usual check for bad ECI state * we must advance ECI state if the insn succeeds * if ECI says we should not be executing the beat corresponding to the lane of the vector register being accessed then we should skip performing the move Note that if PSR.ECI is non-zero then we cannot be in an IT block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-45-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VADDVPeter Maydell
Implement the MVE VADDV insn, which performs an addition across vector lanes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-44-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VHCADDPeter Maydell
Implement the MVE VHCADD insn, which is similar to VCADD but performs a halving step. This one overlaps with VADC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-43-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VCADDPeter Maydell
Implement the MVE VCADD insn, which performs a complex add with rotate. Note that the size=0b11 encoding is VSBC. The architecture grants some leeway for the "destination and Vm source overlap" case for the size MO_32 case, but we choose not to make use of it, instead always calculating all 16 bytes worth of results before setting the destination register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-42-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VADC, VSBCPeter Maydell
Implement the MVE VADC and VSBC insns. These perform an add-with-carry or subtract-with-carry of the 32-bit elements in each lane of the input vectors, where the carry-out of each add is the carry-in of the next. The initial carry input is either 1 or is from FPSCR.C; the carry out at the end is written back to FPSCR.C. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-41-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VRHADDPeter Maydell
Implement the MVE VRHADD insn, which performs a rounded halving addition. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-40-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQDMULL (vector)Peter Maydell
Implement the vector form of the MVE VQDMULL insn. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-39-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQDMLSDH and VQRDMLSDHPeter Maydell
Implement the MVE VQDMLSDH and VQRDMLSDH insns, which are like VQDMLADH and VQRDMLADH except that products are subtracted rather than added. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-38-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQDMLADH and VQRDMLADHPeter Maydell
Implement the MVE VQDMLADH and VQRDMLADH insns. These multiply elements, and then add pairs of products, double, possibly round, saturate and return the high half of the result. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-37-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VRSHLPeter Maydell
Implement the MVE VRSHL insn (vector form). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-36-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VSHL insnPeter Maydell
Implement the MVE VSHL insn (vector form). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-35-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQRSHLPeter Maydell
Implement the MV VQRSHL (vector) insn. Again, the code to perform the actual shifts is borrowed from neon_helper.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-34-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQSHL (vector)Peter Maydell
Implement the MVE VQSHL insn (encoding T4, which is the vector-shift-by-vector version). The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from the neon_helper.c code for qshl_u{8,16,32} and qshl_s{8,16,32}. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-33-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQADD, VQSUB (vector)Peter Maydell
Implement the vector forms of the MVE VQADD and VQSUB insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-32-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQDMULH, VQRDMULH (vector)Peter Maydell
Implement the vector forms of the MVE VQDMULH and VQRDMULH insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-31-peter.maydell@linaro.org
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