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2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
This change adds support for inserting virtual interrupts from M-mode into S-mode using mvien and mvip csrs. IRQ filtering is a use case of this change, i-e M-mode can stop delegating an interrupt to S-mode and instead enable it in MIE and receive those interrupts in M-mode and then selectively inject the interrupt using mvien and mvip. Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows M-mode to assert virtual interrupts to S-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "5.3 Interrupt filtering and virtual interrupts for supervisor level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231016111736.28721-6-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07target/riscv: Split interrupt logic from riscv_cpu_update_mip.Rajnesh Kanwal
This is to allow virtual interrupts to be inserted into S and VS modes. Given virtual interrupts will be maintained in separate mvip and hvip CSRs, riscv_cpu_update_mip will no longer be in the path and interrupts need to be triggered for these cases from rmw_hvip64 and rmw_mvip64 functions. Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231016111736.28721-5-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07target/riscv: Set VS* bits to one in mideleg when H-Ext is enabledRajnesh Kanwal
With H-Ext supported, VS bits are all hardwired to one in MIDELEG denoting always delegated interrupts. This is being done in rmw_mideleg but given mideleg is used in other places when routing interrupts this change initializes it in riscv_cpu_realize to be on the safe side. Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231016111736.28721-4-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.Rajnesh Kanwal
RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that async flag check is performed before invoking semihosting logic. Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231016111736.28721-3-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07target/riscv: Without H-mode mask all HS mode inturrupts in mie.Rajnesh Kanwal
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231016111736.28721-2-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07target/riscv: rename ext_icboz to ext_zicbozDaniel Henrique Barboza
Add a leading 'z' to improve grepping. When one wants to search for uses of zicboz they're more likely to do 'grep -i zicboz' than 'grep -i icboz'. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20231012164604.398496-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07target/riscv: rename ext_icbom to ext_zicbomDaniel Henrique Barboza
Add a leading 'z' to improve grepping. When one wants to search for uses of zicbom they're more likely to do 'grep -i zicbom' than 'grep -i icbom'. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20231012164604.398496-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza
Add a leading 'z' to improve grepping. When one wants to search for uses of zicsr they're more likely to do 'grep -i zicsr' than 'grep -i icsr'. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20231012164604.398496-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07target/riscv: rename ext_ifencei to ext_zifenceiDaniel Henrique Barboza
Add a leading 'z' to improve grepping. When one wants to search for uses of zifencei they're more likely to do 'grep -i zifencei' than 'grep -i ifencei'. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20231012164604.398496-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-06tcg/sparc64: Implement tcg_out_extrl_i64_i32Richard Henderson
Build fix for missing symbol. Cc: qemu-stable@nongnu.org Fixes: dad2f2f5af ("tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06tcg/optimize: Canonicalize sub2 with constants to add2Richard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231026013945.1152174-4-richard.henderson@linaro.org>
2023-11-06tcg/optimize: Canonicalize subi to addi during optimizationRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231026013945.1152174-3-richard.henderson@linaro.org>
2023-11-06tcg: Canonicalize subi to addi during opcode generationRichard Henderson
Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231026013945.1152174-2-richard.henderson@linaro.org>
2023-11-06tcg/optimize: Split out arg_new_constantRichard Henderson
Fixes a bug wherein raw uses of tcg_constant_internal do not have their TempOptInfo initialized. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06tcg: Eliminate duplicate env store operationsRichard Henderson
Notice when a constant is stored to the same location twice. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06tcg/optimize: Optimize env memory operationsRichard Henderson
Propagate stores to loads, loads to loads. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06tcg/optimize: Split out cmp_better_copyRichard Henderson
Compare two temps for "better", split out from finding the best from a whole list. Use TCGKind, which already gives the proper priority. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06tcg/optimize: Pipe OptContext into reset_tsRichard Henderson
Will be needed in the next patch. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06tcg: Don't free vector resultsRichard Henderson
Avoid reusing vector temporaries so that we may re-use them when propagating stores to loads. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}Richard Henderson
The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org>
2023-11-06tcg/loongarch64: Implement neg opcodesRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-6-richard.henderson@linaro.org>
2023-11-06tcg/mips: Implement neg opcodesRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-5-richard.henderson@linaro.org>
2023-11-06tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}Richard Henderson
The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-4-richard.henderson@linaro.org>
2023-11-06tcg/mips: Always implement movcondRichard Henderson
Expand as branch over move if not supported in the ISA. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-3-richard.henderson@linaro.org>
2023-11-06tcg/mips: Split out tcg_out_setcond_intRichard Henderson
Return the temp and a set of flags, to be used as a primitive for setcond, brcond, movcond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-2-richard.henderson@linaro.org>
2023-11-06tcg: Move tcg_temp_free_* out of lineRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-12-richard.henderson@linaro.org>
2023-11-06tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of lineRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-11-richard.henderson@linaro.org>
2023-11-06tcg: Move tcg_constant_* out of lineRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-10-richard.henderson@linaro.org>
2023-11-06tcg: Unexport tcg_gen_op*_{i32,i64}Richard Henderson
These functions are no longer used outside tcg-op.c. There are several that are completely unused, so remove them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-9-richard.henderson@linaro.org>
2023-11-06tcg: Move tcg_gen_opN declarations to tcg-internal.hRichard Henderson
These are used within tcg-op.c and tcg-op-ldst.c. There are no uses outside tcg/. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-8-richard.henderson@linaro.org>
2023-11-06tcg: Move vec_gen_* declarations to tcg-internal.hRichard Henderson
These are used within tcg-op-vec.c and tcg/host/tcg-target.c.inc. There are no uses outside tcg/. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-7-richard.henderson@linaro.org>
2023-11-06tcg: Move 64-bit expanders out of lineRichard Henderson
This one is more complicated, combining 32-bit and 64-bit expansion with C if instead of preprocessor #if. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-6-richard.henderson@linaro.org>
2023-11-06tcg: Move 32-bit expanders out of lineRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-5-richard.henderson@linaro.org>
2023-11-06tcg: Move generic expanders out of lineRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-4-richard.henderson@linaro.org>
2023-11-06tcg: Move tcg_gen_op* out of lineRichard Henderson
In addition to moving out of line, with CONFIG_DEBUG_TCG mark them all noinline. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-3-richard.henderson@linaro.org>
2023-11-06tcg: Mark tcg_gen_op* as noinlineRichard Henderson
Encourage the compiler to tail-call rather than inline across the dozens of opcode expanders. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-2-richard.henderson@linaro.org>
2023-11-06accel/tcg: Fix condition for store_atom_insert_al16Richard Henderson
Store bytes under a mask is fundamentally a cmpxchg, not a straight store. Use HAVE_CMPXCHG128 instead of HAVE_ATOMIC128_RW. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230916220151.526140-8-richard.henderson@linaro.org>
2023-11-06accel/tcg: Remove redundant case in store_atom_16Richard Henderson
We handled the HAVE_ATOMIC128_RW case with atomic16_set at the top of the function; the only thing left for a host without that support is to fall through to cpu_loop_exit_atomic. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230916220151.526140-7-richard.henderson@linaro.org>
2023-11-06host/include/loongarch64: Add atomic16 load and storeRichard Henderson
While loongarch64 does not have a 128-bit cmpxchg, it does have 128-bit atomic load and store via the vector unit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230916220151.526140-6-richard.henderson@linaro.org>
2023-11-06tcg/loongarch64: Use cpuinfo.hRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-5-richard.henderson@linaro.org>
2023-11-06util: Add cpuinfo for loongarch64Richard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-4-richard.henderson@linaro.org>
2023-11-06tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128Richard Henderson
Use new registers for the output, so that we never overlap the input address, which could happen for user-only. This avoids a "tmp = addr + 0" in that case. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-3-richard.henderson@linaro.org>
2023-11-06tcg: Add C_N2_I1Richard Henderson
Constraint with two outputs, both in new registers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-2-richard.henderson@linaro.org>
2023-11-06accel/tcg: Move HMP info jit and info opcount codeRichard Henderson
Move all of it into accel/tcg/monitor.c. This puts everything about tcg that is only used by the monitor in the same place. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06file-posix: fix over-writing of returning zone_append offsetNaohiro Aota
raw_co_zone_append() sets "s->offset" where "BDRVRawState *s". This pointer is used later at raw_co_prw() to save the block address where the data is written. When multiple IOs are on-going at the same time, a later IO's raw_co_zone_append() call over-writes a former IO's offset address before raw_co_prw() completes. As a result, the former zone append IO returns the initial value (= the start address of the writing zone), instead of the proper address. Fix the issue by passing the offset pointer to raw_co_prw() instead of passing it through s->offset. Also, remove "offset" from BDRVRawState as there is no usage anymore. Fixes: 4751d09adcc3 ("block: introduce zone append write for zoned devices") Signed-off-by: Naohiro Aota <naohiro.aota@wdc.com> Message-Id: <20231030073853.2601162-1-naohiro.aota@wdc.com> Reviewed-by: Sam Li <faithilikerun@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
2023-11-06block/file-posix: fix update_zones_wp() callerSam Li
When the zoned request fail, it needs to update only the wp of the target zones for not disrupting the in-flight writes on these other zones. The wp is updated successfully after the request completes. Fixed the callers with right offset and nr_zones. Signed-off-by: Sam Li <faithilikerun@gmail.com> Message-Id: <20230825040556.4217-1-faithilikerun@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> [hreitz: Rebased and fixed comment spelling] Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
2023-11-06qcow2: keep reference on zeroize with discard-no-unref enabledJean-Louis Dupond
When the discard-no-unref flag is enabled, we keep the reference for normal discard requests. But when a discard is executed on a snapshot/qcow2 image with backing, the discards are saved as zero clusters in the snapshot image. When committing the snapshot to the backing file, not discard_in_l2_slice is called but zero_in_l2_slice. Which did not had any logic to keep the reference when discard-no-unref is enabled. Therefor we add logic in the zero_in_l2_slice call to keep the reference on commit. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1621 Signed-off-by: Jean-Louis Dupond <jean-louis@dupond.be> Message-Id: <20231003125236.216473-2-jean-louis@dupond.be> [hreitz: Made the documentation change more verbose, as discussed on-list] Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
2023-11-06target/arm: Fix A64 LDRA immediate decodePeter Maydell
In commit be23a049 in the conversion to decodetree we broke the decoding of the immediate value in the LDRA instruction. This should be a 10 bit signed value that is scaled by 8, but in the conversion we incorrectly ended up scaling it only by 2. Fix the scaling factor. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1970 Fixes: be23a049 ("target/arm: Convert load (pointer auth) insns to decodetree") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231106113445.1163063-1-peter.maydell@linaro.org
2023-11-06hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0Peter Maydell
On the vexpress-a9 board we try to map both RAM and flash to address 0, as seen in "info mtree": address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-0000000003ffffff (prio 0, romd): alias vexpress.flashalias @vexpress.flash0 0000000000000000-0000000003ffffff 0000000000000000-0000000003ffffff (prio 0, ram): alias vexpress.lowmem @vexpress.highmem 0000000000000000-0000000003ffffff 0000000010000000-0000000010000fff (prio 0, i/o): arm-sysctl 0000000010004000-0000000010004fff (prio 0, i/o): pl041 (etc) The flash "wins" and the RAM mapping is useless (but also harmless). This happened as a result of commit 6ec1588e in 2014, which changed "we always map the RAM to the low addresses for vexpress-a9" to "we always map flash in the low addresses", but forgot to stop mapping the RAM. In real hardware, this low part of memory is remappable, both at runtime by the guest writing to a control register, and configurably as to what you get out of reset -- you can have the first flash device, or the second, or the DDR2 RAM, or the external AXI bus (which for QEMU means "nothing there"). In an ideal world we would support that remapping both at runtime and via a machine property to select the out-of-reset behaviour. Pending anybody caring enough to implement the full remapping behaviour: * remove the useless mapped-but-inaccessible lowram MR * document that QEMU doesn't support remapping of low memory Fixes: 6ec1588e ("hw/arm/vexpress: Alias NOR flash at 0 for vexpress-a9") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1761 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231103185602.875849-1-peter.maydell@linaro.org
2023-11-06io/channel-socket: qio_channel_socket_flush(): improve msg validationVladimir Sementsov-Ogievskiy
For SO_EE_ORIGIN_ZEROCOPY the 32-bit notification range is encoded as [ee_info, ee_data] inclusively, so ee_info should be less or equal to ee_data. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru> Message-id: 20231017125941.810461-7-vsementsov@yandex-team.ru Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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