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2023-10-30Merge tag 'pull-hex-20231018' of https://github.com/quic/qemu into stagingStefan Hajnoczi
hexagon: GETPC() fixes, shadowing fixes # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEPWaq5HRZSCTIjOD4GlSvuOVkbDIFAmUwjhYACgkQGlSvuOVk # bDK1Kw//fqzt62h+x182uOZz3XCr9co8mJGXAnu9cy8Jkmf7BGT6jNsjpQe5KjyH # FJNYsfx2dnzC6bqID4ioiBTA3Vgq5XyumpxORzCJTerda3bJr8Q3qt3yK80IIsdf # HkeYfxHFsOG57KqyRJYZenJQBeCq/CcPWfWrxLspFPa96RF4Ui34srucjS6QZp4R # l6jlkxmvkkEV0Cq3vwKkTlrOTUDWQ5dZw5GfVrE3D6WfpB6SzprzDrWAi4dBSG3S # ZNg1WU229A83n4hWw91brHzejE7KHbgjbhfGnlS05AHIqGrhAzDQIWXm4q1yMlca # /lGTBbKZzg6+RmFj6Rb5MzeaiVIQaQ75L4mJ72C03v+7ZHtV0m7nxTREEbZFsstZ # 7T8yutG/ljHHkb7xXL5kvJCIA5/UPv9qH3jYQebkVh0vgKSzZOPuPE1OVymTUmqb # tWKdWcoq0Dj+FWBg/Mnb6RrECA2Rn91nRv6byVkPZ4xRWUxjUMmFW0Mbpa5SO5z/ # pGQGhcnGOMfZQBCxdwDU17RVetXho3xr2JCmYMG/vjin7lqoY5D+AFl+R7UAm/0p # C4Pe/uqGRwXlEkL5lwO2RIoMp0bXRDZI9yQeeWVg6uBbWDKBlM2TmHiu6lyRofTl # 0/Go8nhumecT09xMTFMp5doQL8HSYKv0DnzqFjM8a5Tc5gQSFx4= # =1KeO # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 11:01:58 JST # gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32 # gpg: Good signature from "Brian Cain <bcain@kernel.org>" [unknown] # gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown] # gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown] # gpg: aka "bcain" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47 # Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32 * tag 'pull-hex-20231018' of https://github.com/quic/qemu: target/hexagon: fix some occurrences of -Wshadow=local target/hexagon: move GETPC() calls to top level helpers Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-30hw/ufs: Modify lu.c to share codes with SCSI subsystemJeuk Kim
This patch removes the code that ufs-lu was duplicating from scsi-hd and allows them to share code. It makes ufs-lu have a virtual scsi-bus and scsi-hd internally. This allows scsi related commands to be passed thorugh to the scsi-hd. The query request and nop command work the same as the existing logic. Well-known lus do not have a virtual scsi-bus and scsi-hd, and handle the necessary scsi commands by emulating them directly. Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
2023-10-30Merge tag 'pull-request-2023-10-27' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi
staging * Fix global variable shadowing in test code * Avoid recompiling libfdt in the FreeBSD VM * Mark old pc machine types as deprecated * Force IPv4 in the ipmi-bt-test # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmU7g+wRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWzIQ//WkiEtXAB4zn/b8H0KfRF283FoFMstBPu # xrF90WcXMidAPRK8iFhwlae0rVyo40V6A3+/0rntMZ6WPJ3pVvFhmM4zIQgX+1+F # HT8To7ngngeEey5gJNbOs9GdAFSmF8HwB+HWnEGf2fjWsUvIWgm458ikPUWvhXaJ # 08wH4V+bmEAKYgny8/ys70E1iFeMwfg+LKXHzVAavaQ8GjM9xFXOjRe8XEq2P7/8 # T99O+hn1iGJfrvZTdJ01awRuOUzA1YTKLCYNSzfRc/j0eYwI28CBm12/sZn4dUA8 # 4rV33ISPw55QmxdVLCfGhAJ6Ih0trOgf8eDBkhcgqWt26ymcKyVL/7kJHcuoY9Q2 # onaN3XT39lVz/HmcuTl9a0sePsZd4d7p0vRsccwTSisX8RpLDab8I8oU8Nvs3VQG # t23K3XLrdSyMbxsbi9b5BdXJVgkz4irEKG1dX8laIGMGD5zVi/LX2BWjP6QaIOZi # OyopRQN2uTi6cry5NmblpeLDNJwQdQVxJKlqcvDQQl8TjPXleNtIXL4dr+IpNC5T # Uo8GJ6+b+AzUI4EaNFybVDPAYHFMJKxvN/QUEjExKV1QTP3V2V9jCbGCF8nio8pp # ISo11Lo/Z4Z39NwDBH13UuSOdD1rlrU2uuq6LaiRTBfCOTYumzUMvlDTNYqGuSLr # +1q1GTGsHO0= # =A6CT # -----END PGP SIGNATURE----- # gpg: Signature made Fri 27 Oct 2023 18:33:32 JST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-10-27' of https://gitlab.com/thuth/qemu: ipmi-bt-test: force ipv4 tests/vm/freebsd: Add additional library paths for libfdt docs/about: Mark the old pc-i440fx-2.0 - 2.3 machine types as deprecated tests/coroutine: Clean up global variable shadowing tests/aio: Clean up global variable shadowing tests/npcm7xx_adc: Clean up global variable shadowing tests/rtl8139: Clean up global variable shadowing tests/cdrom-test: Clean up global variable shadowing in prepare_image() tests/virtio-scsi: Clean up global variable shadowing tests/throttle: Clean up global variable shadowing system/qtest: Clean up global variable shadowing in qtest_server_init() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-27hw/net/cadence_gem: enforce 32 bits variable size for CRCLuc Michel
The CRC was stored in an unsigned variable in gem_receive. Change it for a uint32_t to ensure we have the correct variable size here. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-12-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: perform PHY access on write onlyLuc Michel
The MDIO access is done only on a write to the PHYMNTNC register. A subsequent read is used to retrieve the result but does not trigger an MDIO access by itself. Refactor the PHY access logic to perform all accesses (MDIO reads and writes) at PHYMNTNC write time. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-11-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fieldsLuc Michel
Use the FIELD macro to describe the PHYMNTNC register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-10-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe DESCONF6 register fieldsLuc Michel
Use the FIELD macro to describe the DESCONF6 register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231017194422.4124691-9-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe IRQ register fieldsLuc Michel
Use de FIELD macro to describe the IRQ related register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-8-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fieldsLuc Michel
Use de FIELD macro to describe the TXSTATUS and RXSTATUS register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-7-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe DMACFG register fieldsLuc Michel
Use de FIELD macro to describe the DMACFG register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-6-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe NWCFG register fieldsLuc Michel
Use de FIELD macro to describe the NWCFG register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-5-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe NWCTRL register fieldsLuc Michel
Use the FIELD macro to describe the NWCTRL register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-4-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD for screening registersLuc Michel
Describe screening registers fields using the FIELD macros. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-3-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use REG32 macro for register definitionsLuc Michel
Replace register defines with the REG32 macro from registerfields.h in the Cadence GEM device. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-2-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27misc/led: LED state is set opposite of what is expectedGlenn Miles
Testing of the LED state showed that when the LED polarity was set to GPIO_POLARITY_ACTIVE_LOW and a low logic value was set on the input GPIO of the LED, the LED was being turn off when it was expected to be turned on. Fixes: ddb67f6402 ("hw/misc/led: Allow connecting from GPIO output") Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Message-id: 20231024191945.4135036-1-milesg@linux.vnet.ibm.com Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachablePhilippe Mathieu-Daudé
Prefer using a well known local first CPU rather than a global one. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231025065909.57344-1-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing itPhilippe Mathieu-Daudé
qbus_new(), called in i2c_init_bus(), should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20231020130331.50048-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20231020130331.50048-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/intc/pxa2xx: Pass CPU reference using QOM link propertyPhilippe Mathieu-Daudé
QOM objects shouldn't access each other internals fields except using the QOM API. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20231020130331.50048-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/intc/pxa2xx: Convert to Resettable interfacePhilippe Mathieu-Daudé
Factor reset code out of the DeviceRealize() handler. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20231020130331.50048-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231020130331.50048-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple()Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231020130331.50048-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/pcmcia/pxa2xx: Realize sysbus device before accessing itPhilippe Mathieu-Daudé
sysbus_mmio_map() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231020130331.50048-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/sd/pxa2xx: Do not open-code sysbus_create_simple()Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231020130331.50048-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/sd/pxa2xx: Realize sysbus device before accessing itPhilippe Mathieu-Daudé
sysbus_mmio_map() and sysbus_connect_irq() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231020130331.50048-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27target/arm: Fix syndrome for FGT traps on ERETPeter Maydell
In commit 442c9d682c94fc2 when we converted the ERET, ERETAA, ERETAB instructions to decodetree, the conversion accidentally lost the correct setting of the syndrome register when taking a trap because of the FEAT_FGT HFGITR_EL1.ERET bit. Instead of reporting a correct full syndrome value with the EC and IL bits, we only reported the low two bits of the syndrome, because the call to syn_erettrap() got dropped. Fix the syndrome values for these traps by reinstating the syn_erettrap() calls. Fixes: 442c9d682c94fc2 ("target/arm: Convert ERET, ERETAA, ERETAB to decodetree") Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024172438.2990945-1-peter.maydell@linaro.org
2023-10-27target/arm: Move ID_AA64DFR* feature tests togetherPeter Maydell
Move all the ID_AA64DFR* feature test functions together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-7-peter.maydell@linaro.org
2023-10-27target/arm: Move ID_AA64PFR* tests togetherPeter Maydell
Move all the ID_AA64PFR* feature test functions together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-6-peter.maydell@linaro.org
2023-10-27target/arm: Move ID_AA64ISAR* test functions togetherPeter Maydell
Move the feature test functions that test ID_AA64ISAR* fields together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-5-peter.maydell@linaro.org
2023-10-27target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2Peter Maydell
Move the ID_AA64MMFR0 feature test functions up so they are before the ones for ID_AA64MMFR1 and ID_AA64MMFR2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-4-peter.maydell@linaro.org
2023-10-27target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests togetherPeter Maydell
Our list of isar_feature functions is not in any particular order, but tests on fields of the same ID register tend to be grouped together. A few functions that are tests of fields in ID_AA64MMFR1 and ID_AA64MMFR2 are not in the same place as the rest; move them into their groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-3-peter.maydell@linaro.org
2023-10-27target/arm: Move feature test functions to their own headerPeter Maydell
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot of source files, most of which don't need these functions. Move the feature test functions to their own header file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org
2023-10-27target/arm: Implement Neoverse N2 CPU modelPeter Maydell
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A processor very similar to the Cortex-A710. The differences are: * no FEAT_EVT * FEAT_DGH (data gathering hint) * FEAT_NV (not yet implemented in QEMU) * Statistical Profiling Extension (not implemented in QEMU) * 48 bit physical address range, not 40 * CTR_EL0.DIC = 1 (no explicit icache cleaning needed) * PMCR_EL0.N = 6 (always 6 PMU counters, not 20) Because it has 48-bit physical address support, we can use this CPU in the sbsa-ref board as well as the virt board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org
2023-10-27target/arm: Correct minor errors in Cortex-A710 definitionPeter Maydell
Correct a couple of minor errors in the Cortex-A710 definition: * ID_AA64DFR0_EL1.DebugVer is 9 (indicating Armv8.4 debug architecture) * ID_AA64ISAR1_EL1.APA is 5 (indicating more PAuth support) * there is an IMPDEF CPUCFR_EL1, like that on the Neoverse-N1 Fixes: e3d45c0a89576 ("target/arm: Implement cortex-a710") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-2-peter.maydell@linaro.org
2023-10-27ipmi-bt-test: force ipv4Vladimir Sementsov-Ogievskiy
We open ipv4 listening socket. But "localhost" in qemu parameters may load to Qemu trying to connect with ipv6 and fail with "Connection refused". Force ipv4 by using ipv4 ip address. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Message-ID: <20231018191123.1176602-1-vsementsov@yandex-team.ru> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-27tests/vm/freebsd: Add additional library paths for libfdtThomas Huth
libfdt is installed in /usr/local on FreeBSD, and since this library does not have a pkg-config file, we have to specify the paths manually. This way we can avoid that Meson has to recompile the dtc subproject each time. Message-ID: <20231016161053.39150-1-thuth@redhat.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-27docs/about: Mark the old pc-i440fx-2.0 - 2.3 machine types as deprecatedThomas Huth
As we've seen in the past, it's useful for deprecating old machine types to finally be able to get of legacy code or do other clean-ups (see e.g. commit ea985d235b868047 that was used to drop the PCI code in the 128k bios binaries to free some precious space in those binaries). So let's continue deprecating the oldest pc machine types. QEMU 2.3 has been released 8 years ago, so that's plenty of time since such machine types have been used by default, thus deprecating pc-i440fx-2.0 up to pc-i440fx-2.3 should be fine nowadays. Message-ID: <20231006075247.403364-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-27tests/coroutine: Clean up global variable shadowingPhilippe Mathieu-Daudé
Rename the global variable to avoid: tests/unit/test-coroutine.c:430:11: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] bool *done = opaque; ^ tests/unit/test-coroutine.c:438:10: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] bool done = false; ^ tests/unit/test-coroutine.c:198:12: note: previous declaration is here static int done; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231009100251.56019-11-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-27tests/aio: Clean up global variable shadowingPhilippe Mathieu-Daudé
Rename the argument to fix: tests/unit/test-aio.c:130:44: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void set_event_notifier(AioContext *ctx, EventNotifier *notifier, ^ tests/unit/test-aio.c:22:20: note: previous declaration is here static AioContext *ctx; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231009100251.56019-9-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-10-27tests/npcm7xx_adc: Clean up global variable shadowingPhilippe Mathieu-Daudé
Rename the global 'adc' variable in order to avoid: tests/qtest/npcm7xx_adc-test.c:98:58: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static uint32_t adc_read_con(QTestState *qts, const ADC *adc) ^ tests/qtest/npcm7xx_adc-test.c:103:55: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value) ^ tests/qtest/npcm7xx_adc-test.c:108:59: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static uint32_t adc_read_data(QTestState *qts, const ADC *adc) ^ tests/qtest/npcm7xx_adc-test.c:119:53: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void adc_qom_set(QTestState *qts, const ADC *adc, ^ tests/qtest/npcm7xx_adc-test.c:135:57: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void adc_write_input(QTestState *qts, const ADC *adc, ^ tests/qtest/npcm7xx_adc-test.c:144:56: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value) ^ tests/qtest/npcm7xx_adc-test.c:162:59: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static uint32_t adc_prescaler(QTestState *qts, const ADC *adc) ^ tests/qtest/npcm7xx_adc-test.c:175:64: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] static void adc_wait_conv_finished(QTestState *qts, const ADC *adc, ^ tests/qtest/npcm7xx_adc-test.c:196:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:207:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:235:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:267:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:293:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:311:16: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const ADC *adc = adc_p; ^ tests/qtest/npcm7xx_adc-test.c:93:5: note: previous declaration is here ADC adc = { ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231009100251.56019-8-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
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