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2021-10-30linux-user: Reorg handling for SIGSEGVRichard Henderson
Add stub host-signal.h for all linux-user hosts. Add new code replacing cpu_signal_handler. Full migration will happen one host at a time. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-30configure: Merge riscv32 and riscv64 host architecturesRichard Henderson
The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-30accel/tcg: Fold cpu_exit_tb_from_sighandler into callerRichard Henderson
Remove the comment about siglongjmp. We do use sigsetjmp in the main cpu loop, but we do not save the signal mask as most exits from the cpu loop do not require them. Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-30accel/tcg: Split out handle_sigsegv_accerr_writeRichard Henderson
This is the major portion of handle_cpu_signal which is specific to tcg, handling the page protections for the translations. Most of the rest will migrate to linux-user/ shortly. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Pass guest address to handle_sigsegv_accerr_write.
2021-10-30accel/tcg: Move clear_helper_retaddr to cpu loopRichard Henderson
Currently there are only two places that require we reset this value before exiting to the main loop, but that will change. Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-30accel/tcg: Split out adjust_signal_pcRichard Henderson
Split out a function to adjust the raw signal pc into a value that could be passed to cpu_restore_state. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Adjust pc in place; return MMUAccessType.
2021-10-29Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-10-29' into ↵Richard Henderson
staging QAPI patches patches for 2021-10-29 # gpg: Signature made Fri 29 Oct 2021 12:28:53 PM PDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] * remotes/armbru/tags/pull-qapi-2021-10-29: qapi: Extend -compat to set policy for unstable interfaces qapi: Factor out compat_policy_input_ok() qapi: Generalize enum member policy checking qapi: Generalize command policy checking qapi: Generalize struct member policy checking qapi: Tools for sets of special feature flags in generated code qapi: Eliminate QCO_NO_OPTIONS for a slight simplification qapi: Mark unstable QMP parts with feature 'unstable' qapi: New special feature flag "unstable" Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-29Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' ↵Richard Henderson
into staging x86 queue, 2021-10-29 Bug fixes: * Remove core-capability in Snowridge CPU model # gpg: Signature made Fri 29 Oct 2021 12:05:14 PM PDT # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] * remotes/ehabkost/tags/x86-next-pull-request: target/i386: Remove core-capability in Snowridge CPU model Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-29qapi: Extend -compat to set policy for unstable interfacesMarkus Armbruster
New option parameters unstable-input and unstable-output set policy for unstable interfaces just like deprecated-input and deprecated-output set policy for deprecated interfaces (see commit 6dd75472d5 "qemu-options: New -compat to set policy for deprecated interfaces"). This is intended for testing users of the management interfaces. It is experimental. For now, this covers only syntactic aspects of QMP, i.e. stuff tagged with feature 'unstable'. We may want to extend it to cover semantic aspects, or the command line. Note that there is no good way for management application to detect presence of these new option parameters: they are not visible output of query-qmp-schema or query-command-line-options. Tolerable, because it's meant for testing. If running with -compat fails, skip the test. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: John Snow <jsnow@redhat.com> Message-Id: <20211028102520.747396-10-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> [Doc comments fixed up]
2021-10-29qapi: Factor out compat_policy_input_ok()Markus Armbruster
The code to check policy for handling deprecated input is triplicated. Factor it out into compat_policy_input_ok() before I mess with it in the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211028102520.747396-9-armbru@redhat.com> [Policy code moved from qmp-dispatch.c to qapi-util.c to make visitors link without qmp-dispatch.o]
2021-10-29target/i386: Remove core-capability in Snowridge CPU modelChenyi Qiang
Because core-capability releated features are model-specific and KVM won't support it, remove the core-capability in CPU model to avoid the warning message. Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Message-Id: <20210827064818.4698-3-chenyi.qiang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2021-10-29Merge remote-tracking branch ↵Richard Henderson
'remotes/alistair23/tags/pull-riscv-to-apply-20211029-1' into staging Fifth RISC-V PR for QEMU 6.2 - Use a shared PLIC config helper function - Fixup the OpenTitan PLIC configuration - Add support for the experimental J extension - Update the fmin/fmax handling - Fixup VS interrupt forwarding # gpg: Signature made Fri 29 Oct 2021 12:03:47 AM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] * remotes/alistair23/tags/pull-riscv-to-apply-20211029-1: target/riscv: change the api for RVF/RVD fmin/fmax softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin target/riscv: remove force HS exception target/riscv: fix VS interrupts forwarding to HS target/riscv: Allow experimental J-ext to be turned on target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions target/riscv: Print new PM CSRs in QEMU logs target/riscv: Add J extension state description target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode target/riscv: Add CSR defines for RISC-V PM extension target/riscv: Add J-extension into RISC-V hw/riscv: opentitan: Fixup the PLIC context addresses hw/riscv: virt: Use the PLIC config helper function hw/riscv: microchip_pfsoc: Use the PLIC config helper function hw/riscv: sifive_u: Use the PLIC config helper function hw/riscv: boot: Add a PLIC config string function hw/riscv: virt: Don't use a macro for the PLIC configuration Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-29qapi: Generalize enum member policy checkingMarkus Armbruster
The code to check enumeration value policy can see special feature flag 'deprecated' in QEnumLookup member flags[value]. I want to make feature flag 'unstable' visible there as well, so I can add policy for it. Instead of extending flags[], replace it by @special_features (a bitset of QapiSpecialFeature), because that's how special features get passed around elsewhere. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: John Snow <jsnow@redhat.com> Message-Id: <20211028102520.747396-8-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-10-29qapi: Generalize command policy checkingMarkus Armbruster
The code to check command policy can see special feature flag 'deprecated' as command flag QCO_DEPRECATED. I want to make feature flag 'unstable' visible there as well, so I can add policy for it. To let me make it visible, add member @special_features (a bitset of QapiSpecialFeature) to QmpCommand, and adjust the generator to pass it through qmp_register_command(). Then replace "QCO_DEPRECATED in @flags" by QAPI_DEPRECATED in @special_features", and drop QCO_DEPRECATED. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: John Snow <jsnow@redhat.com> Message-Id: <20211028102520.747396-7-armbru@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2021-10-29qapi: Generalize struct member policy checkingMarkus Armbruster
The generated visitor functions call visit_deprecated_accept() and visit_deprecated() when visiting a struct member with special feature flag 'deprecated'. This makes the feature flag visible to the actual visitors. I want to make feature flag 'unstable' visible there as well, so I can add policy for it. To let me make it visible, replace these functions by visit_policy_reject() and visit_policy_skip(), which take the member's special features as an argument. Note that the new functions have the opposite sense, i.e. the return value flips. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20211028102520.747396-6-armbru@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> [Unbreak forward visitor]
2021-10-29Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211028' into stagingRichard Henderson
Improvements to qemu/int128 Fixes for 128/64 division. Cleanup tcg/optimize.c Optimize redundant sign extensions # gpg: Signature made Thu 28 Oct 2021 09:06:00 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * remotes/rth/tags/pull-tcg-20211028: (60 commits) softmmu: fix for "after access" watchpoints softmmu: remove useless condition in watchpoint check softmmu: fix watchpoint processing in icount mode tcg/optimize: Propagate sign info for shifting tcg/optimize: Propagate sign info for bit counting tcg/optimize: Propagate sign info for setcond tcg/optimize: Propagate sign info for logical operations tcg/optimize: Optimize sign extensions tcg/optimize: Use fold_xx_to_i for rem tcg/optimize: Use fold_xi_to_x for div tcg/optimize: Use fold_xi_to_x for mul tcg/optimize: Use fold_xx_to_i for orc tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values tcg: Extend call args using the correct opcodes tcg/optimize: Sink commutative operand swapping into fold functions tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies tcg/optimize: Split out fold_masks tcg/optimize: Split out fold_ix_to_i tcg/optimize: Split out fold_xi_to_x ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-29qapi: Tools for sets of special feature flags in generated codeMarkus Armbruster
New enum QapiSpecialFeature enumerates the special feature flags. New helper gen_special_features() returns code to represent a collection of special feature flags as a bitset. The next few commits will put them to use. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-Id: <20211028102520.747396-5-armbru@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-10-29qapi: Eliminate QCO_NO_OPTIONS for a slight simplificationMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-Id: <20211028102520.747396-4-armbru@redhat.com>
2021-10-29qapi: Mark unstable QMP parts with feature 'unstable'Markus Armbruster
Add special feature 'unstable' everywhere the name starts with 'x-', except for InputBarrierProperties member x-origin and MemoryBackendProperties member x-use-canonical-path-for-ramblock-id, because these two are actually stable. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Acked-by: John Snow <jsnow@redhat.com> Message-Id: <20211028102520.747396-3-armbru@redhat.com>
2021-10-29qapi: New special feature flag "unstable"Markus Armbruster
By convention, names starting with "x-" are experimental. The parts of external interfaces so named may be withdrawn or changed incompatibly in future releases. The naming convention makes unstable interfaces easy to recognize. Promoting something from experimental to stable involves a name change. Client code needs to be updated. Occasionally bothersome. Worse, the convention is not universally observed: * QOM type "input-barrier" has properties "x-origin", "y-origin". Looks accidental, but it's ABI since 4.2. * QOM types "memory-backend-file", "memory-backend-memfd", "memory-backend-ram", and "memory-backend-epc" have a property "x-use-canonical-path-for-ramblock-id" that is documented to be stable despite its name. We could document these exceptions, but documentation helps only humans. We want to recognize "unstable" in code, like "deprecated". So support recognizing it the same way: introduce new special feature flag "unstable". It will be treated specially by the QAPI generator, like the existing feature flag "deprecated", and unlike regular feature flags. This commit updates documentation and prepares tests. The next commit updates the QAPI schema. The remaining patches update the QAPI generator and wire up -compat policy checking. Management applications can then use query-qmp-schema and -compat to manage or guard against use of unstable interfaces the same way as for deprecated interfaces. docs/devel/qapi-code-gen.txt no longer mandates the naming convention. Using it anyway might help writers of programs that aren't full-fledged management applications. Not using it can save us bothersome renames. We'll see how that shakes out. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-Id: <20211028102520.747396-2-armbru@redhat.com>
2021-10-29target/riscv: change the api for RVF/RVD fmin/fmaxChih-Min Chao
The sNaN propagation behavior has been changed since cd20cee7 in https://github.com/riscv/riscv-isa-manual. In Priv spec v1.10, RVF is v2.0. fmin.s and fmax.s are implemented with IEEE 754-2008 minNum and maxNum operations. In Priv spec v1.11, RVF is v2.2. fmin.s and fmax.s are amended to implement IEEE 754-2019 minimumNumber and maximumNumber operations. Therefore, to prevent the risk of having too many version variables. Instead of introducing an extra *fext_ver* variable, we tie RVF version to Priv version. Though it's not completely accurate but is close enough. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211021160847.2748577-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-29softfloat: add APIs to handle alternative sNaN propagation for fmax/fminChih-Min Chao
For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, The original logic: Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan. The alternative path: Set invalid flag if ft1 == sNaN || ft2 == sNaN. Return NaN only if ft1 == NaN && ft2 == NaN. The IEEE 754 spec allows both implementation and some architecture such as riscv choose different defintions in two spec versions. (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to alternative) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211021160847.2748577-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-29target/riscv: remove force HS exceptionJose Martins
There is no need to "force an hs exception" as the current privilege level, the state of the global ie and of the delegation registers should be enough to route the interrupt to the appropriate privilege level in riscv_cpu_do_interrupt. The is true for both asynchronous and synchronous exceptions, specifically, guest page faults which must be hardwired to zero hedeleg. As such the hs_force_except mechanism can be removed. Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211026145126.11025-3-josemartins90@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins
VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when not delegated in hideleg (which was not being taken into account). This was mainly because hs level sie was not always considered enabled when it should. The spec states that "Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode." and also "For purposes of interrupt global enables, HS-mode is considered more privileged than VS-mode, and VS-mode is considered more privileged than VU-mode". Also, vs-level interrupts were not being taken into account unless V=1, but should be unless delegated. Finally, there is no need for a special case for to handle vs interrupts as the current privilege level, the state of the global ie and of the delegation registers should be enough to route all interrupts to the appropriate privilege level in riscv_cpu_do_interrupt. Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211026145126.11025-2-josemartins90@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211028' into stagingRichard Henderson
Followup to replace more tcg_const_* with tcg_constant_tl* Fix bug to delay writes to USR until packet commit # gpg: Signature made Thu 28 Oct 2021 08:59:24 PM PDT # gpg: using RSA key 7B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * remotes/quic/tags/pull-hex-20211028: Hexagon (target/hexagon) put writes to USR into temp until commit Hexagon (target/hexagon) more tcg_constant_* Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28softmmu: fix for "after access" watchpointsPavel Dovgalyuk
Watchpoints that should fire after the memory access break an execution of the current block, try to translate current instruction into the separate block, which then causes debug interrupt. But cpu_interrupt can't be called in such block when icount is enabled, because interrupts muse be allowed explicitly. This patch sets CF_LAST_IO flag for retranslated block, allowing interrupt request for the last instruction. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <163542169727.2127597.8141772572696627329.stgit@pasha-ThinkPad-X280> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28softmmu: remove useless condition in watchpoint checkPavel Dovgalyuk
cpu_check_watchpoint function checks cpu->watchpoint_hit at the entry. But then it also does the same in the middle of the function, while this field can't change. That is why this patch removes this useless condition. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <163542169094.2127597.8801843697434113110.stgit@pasha-ThinkPad-X280> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28softmmu: fix watchpoint processing in icount modePavel Dovgalyuk
Watchpoint processing code restores vCPU state twice: in tb_check_watchpoint and in cpu_loop_exit_restore/cpu_restore_state. Normally it does not affect anything, but in icount mode instruction counter is incremented twice and becomes incorrect. This patch eliminates unneeded CPU state restore. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <163542168516.2127597.8781375223437124644.stgit@pasha-ThinkPad-X280> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28tcg/optimize: Propagate sign info for shiftingRichard Henderson
For constant shifts, we can simply shift the s_mask. For variable shifts, we know that sar does not reduce the s_mask, which helps for sequences like ext32s_i64 t, in sar_i64 t, t, v ext32s_i64 out, t allowing the final extend to be eliminated. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28tcg/optimize: Propagate sign info for bit countingRichard Henderson
The results are generally 6 bit unsigned values, though the count leading and trailing bits may produce any value for a zero input. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28tcg/optimize: Propagate sign info for setcondRichard Henderson
The result is either 0 or 1, which means that we have a 2 bit signed result, and thus 62 bits of sign. For clarity, use the smask_from_zmask function. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28tcg/optimize: Propagate sign info for logical operationsRichard Henderson
Sign repetitions are perforce all identical, whether they are 1 or 0. Bitwise operations preserve the relative quantity of the repetitions. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28tcg/optimize: Optimize sign extensionsRichard Henderson
Certain targets, like riscv, produce signed 32-bit results. This can lead to lots of redundant extensions as values are manipulated. Begin by tracking only the obvious sign-extensions, and converting them to simple copies when possible. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28tcg/optimize: Use fold_xx_to_i for remRichard Henderson
Recognize the constant function for remainder. Suggested-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28tcg/optimize: Use fold_xi_to_x for divRichard Henderson
Recognize the identity function for division. Suggested-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28tcg/optimize: Use fold_xi_to_x for mulRichard Henderson
Recognize the identity function for low-part multiply. Suggested-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28tcg/optimize: Use fold_xx_to_i for orcRichard Henderson
Recognize the constant function for or-complement. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit valuesRichard Henderson
This "garbage" setting pre-dates the addition of the type changing opcodes INDEX_op_ext_i32_i64, INDEX_op_extu_i32_i64, and INDEX_op_extr{l,h}_i64_i32. So now we have a definitive points at which to adjust z_mask to eliminate such bits from the 32-bit operands. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28tcg: Extend call args using the correct opcodesRichard Henderson
Pretending that the source is i64 when it is in fact i32 is incorrect; we have type-changing opcodes that must be used. This bug trips up the subsequent change to the optimizer. Fixes: 4f2331e5b67a Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-28Hexagon (target/hexagon) put writes to USR into temp until commitTaylor Simpson
Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead of hex_gpr[HEX_REG_USR]. Then, we need code to mark the instructions that can set implicitly set USR - Macros added to hex_common.py - A_FPOP added in translate.c Test case added in tests/tcg/hexagon/overflow.c Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-10-28Hexagon (target/hexagon) more tcg_constant_*Taylor Simpson
Change additional tcg_const_tl to tcg_constant_tl Note that gen_pred_cancal had slot_mask initialized with tcg_const_tl. However, it is not constant throughout, so we initialize it with tcg_temp_new and replace the first use with the constant value. Inspired-by: Richard Henderson <richard.henderson@linaro.org> Inspired-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-10-28target/riscv: Allow experimental J-ext to be turned onAlexey Baturo
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211025173609.2724490-9-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28target/riscv: Implement address masking functions required for RISC-V ↵Anatoly Parshintsev
Pointer Masking extension Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211025173609.2724490-8-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of ↵Alexey Baturo
instructions Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211025173609.2724490-7-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28target/riscv: Print new PM CSRs in QEMU logsAlexey Baturo
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211025173609.2724490-6-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28target/riscv: Add J extension state descriptionAlexey Baturo
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211025173609.2724490-5-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the ↵Alexey Baturo
h-mode Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211025173609.2724490-4-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211025173609.2724490-3-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28target/riscv: Add J-extension into RISC-VAlexey Baturo
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211025173609.2724490-2-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28hw/riscv: opentitan: Fixup the PLIC context addressesAlistair Francis
Fixup the PLIC context address to correctly support the threshold and claim register. Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build") Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211025040657.262696-1-alistair.francis@opensource.wdc.com
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-17 17:36:20 +0000