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2023-07-07ppc4xx_pci: Rename QOM type name defineBALATON Zoltan
Rename the TYPE_PPC4xx_PCI_HOST_BRIDGE define and its string value to match each other and other similar types and to avoid confusion with "ppc4xx-host-bridge" type defined in same file. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <c59c28ef440633dbd1de0bda0a93b7862ef91104.1688641673.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440_pcix: Stop using system io region for PCI busBALATON Zoltan
Reduce the iomem region to 64K and use it for the PCI io space and map it directly from the board without an intermediate alias that is not really needed. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <f4ad9af42197a92dd1d0b56c21316dbdad240ee4.1688641673.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440_pcix: Don't use iomem for regsBALATON Zoltan
The iomem memory region is better used for the PCI IO space but currently used for registers. Stop using it for that to allow this to be cleaned up in the next patch. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <3def68f200edd4540393d6b3b03baabe15d649f2.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/sam460ex: Remove address_space_mem local variableBALATON Zoltan
Some places already use get_system_memory() directly so replace the remaining uses and drop the local variable. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <d134d64f13258d1f157b445fedb1e86cf3abb606.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Remove ppc460ex_pcie_init legacy init functionBALATON Zoltan
After previous changes we can now remove the legacy init function and move the device creation to board code. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <29aafeea9f1c871c739600a7b093c5456e8a1dc8.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Add busnum property to PCIe controller modelBALATON Zoltan
Instead of guessing controller number from dcrn_base add a property so the device does not need knowledge about where it is used. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <fdb84344025e00fadf74d0be95665fcb0ac1e039.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Stop using system io region for PCIe busesBALATON Zoltan
Add separate memory regions for the mem and io spaces of the PCIe bus to avoid different buses using the same system io region. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <b631c3a61729eee2166d899b8888164ebeb71574.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Rename local variable in dcr_read_pcie()BALATON Zoltan
Rename local variable storing state struct in dcr_read_pcie() for brevity and consistency with other functions. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <7b6f0033ada74075fc094b1397deb406e1a05741.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Rename parent field of PPC460EXPCIEState to match code styleBALATON Zoltan
QOM prefers to call the parent field parent_obj, change PPC460EXPCIEState ro match that convention. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <6995f28215d2a489a661b7d91a1783048829d467.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Add a macro to shorten PCIe controller DCR registrationBALATON Zoltan
It is shorter and more readable to wrap the complex call to ppc_dcr_register() in a macro than to repeat it several times. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <4dec5ef8115791dc67253afdff9a703eb816a2a8.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Add cpu link property to PCIe controller modelBALATON Zoltan
The PCIe controller model uses PPC DCRs but cannot be modeled with TYPE_PPC4xx_DCR_DEVICE as it derives from TYPE_PCIE_HOST_BRIDGE. Add a cpu link property to it similar to other DCR devices to allow registering DCRs from the device model. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <a79796654deaa81a6a1c71efc874e4d88c4cafd4.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Change ppc460ex_pcie_init() parameter typeBALATON Zoltan
Change parameter of ppc460ex_pcie_init() from env to cpu to allow further refactoring. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <1695d7cc1a9f1070ab498c078916e2389d6e9469.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07tests/avocado: Add powernv machine test scriptNicholas Piggin
This copies ppc_pseries.py to start a set of powernv tests, including a Linux boot test for the newly added SMT mode. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-5-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: SMT support for powernvNicholas Piggin
Set the TIR default value with the SMT thread index, and place some standard limits on SMT configurations. Now powernv is able to boot skiboot and Linux with a SMT topology, including booting a KVM guest. There are several SPRs and other features (e.g., broadcast msgsnd) that are not implemented, but not used by OPAL or Linux and can be added incrementally. Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-4-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: SMT support for the HID SPRNicholas Piggin
HID is a per-core shared register, skiboot sets this (e.g., setting HILE) on one thread and that must affect all threads of the core. Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-3-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Add LPAR-per-core vs per-thread mode flagNicholas Piggin
The Power ISA has the concept of sub-processors: Hardware is allowed to sub-divide a multi-threaded processor into "sub-processors" that appear to privileged programs as multi-threaded processors with fewer threads. POWER9 and POWER10 have two modes, either every thread is a sub-processor or all threads appear as one multi-threaded processor. In the user manuals these are known as "LPAR per thread" / "Thread LPAR", and "LPAR per core" / "1 LPAR", respectively. The practical difference is: in thread LPAR mode, non-hypervisor SPRs are not shared between threads and msgsndp can not be used to message siblings. In 1 LPAR mode, some SPRs are shared and msgsndp is usable. Thrad LPAR allows multiple partitions to run concurrently on the same core, and is a requirement for KVM to run on POWER9/10 (which does not gang-schedule an LPAR on all threads of a core like POWER8 KVM). Traditionally, SMT in PAPR environments including PowerVM and the pseries QEMU machine with KVM acceleration behaves as in 1 LPAR mode. In OPAL systems, Thread LPAR is used. When adding SMT to the powernv machine, it is therefore preferable to emulate Thread LPAR. To account for this difference between pseries and powernv, an LPAR mode flag is added such that SPRs can be implemented as per-LPAR shared, and that becomes either per-thread or per-core depending on the flag. Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/xive2: Always pass a presenter object when accessing the TIMAFrederic Barrat
The low-level functions to access the TIMA take a presenter object as a first argument. When accessing the TIMA from the IC BAR, i.e. indirect calls, we currently pass a NULL pointer for the presenter argument. While it appears ok with the current usage, it's dangerous. And it's pretty easy to figure out the presenter in that context, so this patch fixes it. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230705081400.218408-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/xive: Print CPU target in all TIMA tracesFrederic Barrat
Add the CPU target in the trace when reading/writing the TIMA space. It was already done for other TIMA ops (notify, accept, ...), only missing for those 2. Useful for debug and even more now that we experiment with SMT. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230705110039.231148-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pegasos2: Add support for -initrd command line optionBALATON Zoltan
This also changes type of sz local variable to ssize_t because it is used to store return value of load_elf() and load_image_targphys() that return ssize_t. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <20230704181920.27B58746335@zero.eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/xive: Allow mmio operations of any size on the ESB CI pagesFrederic Barrat
We currently only allow 64-bit operations on the ESB CI pages. There's no real reason for that limitation, skiboot/linux didn't need more. However the hardware supports any size, so this patch relaxes that restriction. It impacts both the ESB pages for "normal" interrupts as well as the ESB pages for escalation interrupts defined for the ENDs. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230704144848.164287-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: Return zero for core thread state xscomJoel Stanley
Firmware now warns if booting in LPAR per core mode (PPC bit 62). So this warning doesn't trigger, report the core thread state is 0. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-ID: <20230704054204.168547-6-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: Add P10 core xscom modelJoel Stanley
Like the quad xscoms, add a core model for P10 to allow future differentiation from P9. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-ID: <20230704054204.168547-5-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: Add P10 quad xscom modelJoel Stanley
Add a PnvQuad class for the P10 powernv machine. No xscoms are implemented yet, but this allows them to be added. The size is reduced to avoid the quad region from overlapping with the core region. address-space: xscom-0 0000000000000000-00000003ffffffff (prio 0, i/o): xscom-0 0000000100000000-00000001000fffff (prio 0, i/o): xscom-quad.0 0000000100108000-0000000100907fff (prio 0, i/o): xscom-core.3 0000000100110000-000000010090ffff (prio 0, i/o): xscom-core.2 0000000100120000-000000010091ffff (prio 0, i/o): xscom-core.1 0000000100140000-000000010093ffff (prio 0, i/o): xscom-core.0 Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-ID: <20230704054204.168547-4-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: Subclass quad xscom callbacksJoel Stanley
Make the existing pnv_quad_xscom_read/write be P9 specific, in preparation for a different P10 callback. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-ID: <20230704054204.168547-3-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: quad xscom callbacks are P9 specificJoel Stanley
Rename the functions to include P9 in the name in preparation for adding P10 versions. Correct the unimp read message while we're changing the function. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-ID: <20230704054204.168547-2-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/psi: Initialize the PSIHB interrupts to match hardwareFrederic Barrat
On the powernv9 and powernv10 machines, the PSIHB interrupts are currently initialized with a PQ state of 0b01, i.e. interrupts are disabled. However real hardware initializes them to 0b00 for the PSIHB. This patch updates it, in case an hypervisor is in the mood of checking it. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230703081215.55252-3-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/xive: Add property on xive sources to define PQ state on resetFrederic Barrat
The PQ state of a xive interrupt is always initialized to Q=1, which means the interrupt is disabled. Since a xive source can be embedded in many objects, this patch adds a property to allow that behavior to be refined if needed. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230703081215.55252-2-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/xive2: Fix TIMA offset for indirect accessFrederic Barrat
Direct TIMA operations can be done through 4 pages, each with a different privilege level dictating what fields can be accessed. On the other hand, indirect TIMA accesses on P10 are done through a single page, which is the equivalent of the most privileged page of direct TIMA accesses. The offset in the IC bar of an indirect access specifies what hw thread is targeted (page shift bits) and the offset in the TIMA being accessed (the page offset bits). When the indirect access is calling the underlying direct access functions, it is therefore important to clearly separate the 2, as the direct functions assume any page shift bits define the privilege ring level. For indirect accesses, those bits must be 0. This patch fixes the offset passed to direct TIMA functions. It didn't matter for SMT1, as the 2 least significant bits of the page shift are part of the hw thread ID and always 0, so the direct TIMA functions were accessing the privilege ring 0 page. With SMT4/8, it is no longer true. The fix is specific to P10, as indirect TIMA access on P9 was handled differently. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230703080858.54060-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target: ppc: Use MSR_HVB bit to get the target endianness for memory dumpNarayana Murty N
Currently on PPC64 qemu always dumps the guest memory in Big Endian (BE) format even though the guest running in Little Endian (LE) mode. So crash tool fails to load the dump as illustrated below: Log : $ virsh dump DOMAIN --memory-only dump.file Domain 'DOMAIN' dumped to dump.file $ crash vmlinux dump.file <snip> crash 8.0.2-1.el9 WARNING: endian mismatch: crash utility: little-endian dump.file: big-endian WARNING: machine type mismatch: crash utility: PPC64 dump.file: (unknown) crash: dump.file: not a supported file format <snip> This happens because cpu_get_dump_info() passes cpu->env->has_hv_mode to function ppc_interrupts_little_endian(), the cpu->env->has_hv_mode always set for powerNV even though the guest is not running in hv mode. The hv mode should be taken from msr_mask MSR_HVB bit (cpu->env.msr_mask & MSR_HVB). This patch fixes the issue by passing MSR_HVB value to ppc_interrupts_little_endian() in order to determine the guest endianness. The crash tool also expects guest kernel endianness should match the endianness of the dump. The patch was tested on POWER9 box booted with Linux as host in following cases: Host-Endianess Qemu-Target-Machine Qemu-Generated-Guest Memory-Dump-Format BE powernv(OPAL/PowerNV) LE BE powernv(OPAL/PowerNV) BE LE powernv(OPAL/PowerNV) LE LE powernv(OPAL/PowerNV) BE LE pseries(OPAL/PowerNV/pSeries) KVMHV LE LE pseries TCG LE Fixes: 5609400a4228 ("target/ppc: Set the correct endianness for powernv memory dumps") Signed-off-by: Narayana Murty N <nnmlinux@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Vaibhav Jain <vaibhav@linux.ibm.com> Message-ID: <20230623072506.34713-1-nnmlinux@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Get CPUState in one stepBALATON Zoltan
We can get CPUState from env with env_cpu without going through PowerPCCPU and casting that. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <28424220f37f51ce97f24cadc7538a9c0d16cb45.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppd: Remove unused defineBALATON Zoltan
Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop the unused define as well. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <50adc24f9d408882128e896d8a81a1a059c41836.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Remove some more local CPUState variables only used onceBALATON Zoltan
Some helpers only have a CPUState local to call cpu_interrupt_exittb() but we can use env_cpu for that and remove the local. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <aa34e449552c6ab52d48938ccbe762fc06adac01.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Move common check in exception handlers to a functionBALATON Zoltan
All powerpc exception handlers share some code when handling machine check exceptions. Move this to a common function. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <9cfffaa35aa894086dd092af6b0b26f2d62ff3de.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Remove unneeded parameter from powerpc_reset_wakeup()BALATON Zoltan
CPUState is rarely needed by this function (only for logging a fatal error) and it's easy to get from the env parameter so passing it separately is not necessary. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <f42761401c708fd6e02f7523d9f709b1972e5863.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Remove some superfluous parenthesesBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <8384ed0f7335093012bbd3d28fb2a543a2e7346c.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/xive2: Allow indirect TIMA accesses of all sizesFrederic Barrat
Booting linux on the powernv10 machine logs a few errors like: Invalid read at addr 0x38, size 1, region 'xive-ic-tm-indirect', reason: invalid size (min:8 max:8) Invalid write at addr 0x38, size 1, region 'xive-ic-tm-indirect', reason: invalid size (min:8 max:8) Invalid read at addr 0x38, size 1, region 'xive-ic-tm-indirect', reason: invalid size (min:8 max:8) Those errors happen when linux is resetting XIVE. We're trying to read/write the enablement bit for the hardware context and qemu doesn't allow indirect TIMA accesses of less than 8 bytes. Direct TIMA access can go through though, as well as indirect TIMA accesses on P9. So even though there are some restrictions regarding the address/size combinations for TIMA access, the example above is perfectly valid. This patch lets indirect TIMA accesses of all sizes go through. The special operations will be intercepted and the default "raw" handlers will pick up all other requests and complain about invalid sizes as appropriate. Tested-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230626094057.1192473-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07tests/avocado: record_replay test for ppc powernv machineNicholas Piggin
The powernv machine can boot Linux to VFS mount with icount enabled. Add a test case for it. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230625103700.8992-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Fix icount access for some hypervisor instructionsNicholas Piggin
Several instructions and register access require icount reads and are missing translator_io_start(). Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230625103700.8992-1-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07sungem: Add WOL MMIONicholas Piggin
Apple sungem devices are expected to have WOL MMIO registers. Add a region to prevent transaction failures, and implement the WOL-disable CSR write because the Linux driver reset writes this. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-ID: <20230625201628.65231-1-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Add TFMR SPR implementation with read and write helpersNicholas Piggin
TFMR is the Time Facility Management Register which is specific to POWER CPUs, and used for the purpose of timebase management (generally by firmware, not the OS). Add helpers for the TFMR register, which will form part of the core timebase facility model in future but for now behaviour is unchanged. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230625120317.13877-3-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Tidy POWER book4 SPR registrationNicholas Piggin
POWER book4 (implementation-specific) SPRs are sometimes in their own functions, but in other cases are mixed with architected SPRs. Do some spring cleaning on these. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230625120317.13877-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07mv64361: Add dummy gigabit ethernet PHY access registersBALATON Zoltan
We don't emulate the gigabit ethernet part of the chip but the MorphOS driver accesses these and expects to get some valid looking result otherwise it hangs. Add some minimal dummy implementation to avoid rhis. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230605215145.29458746335@zero.eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Only generate decodetree files when TCG is enabledPhilippe Mathieu-Daudé
No need to generate TCG-specific decodetree files when TCG is disabled. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230626140100.67941-1-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07hw/ppc: Fix clock update driftNicholas Piggin
The clock update logic reads the clock twice to compute the new clock value, with a value derived from the later time subtracted from a value derived from the earlier time. The delta causes time to be lost. This can ultimately result in time becoming unsynchronized between CPUs and that can cause OS lockups, timeouts, watchdogs, etc. This can be seen running a KVM guest (that causes lots of TB updates) on a powernv SMP machine. Fix this by reading the clock once. Cc: qemu-stable@nongnu.org Fixes: dbdd25065e90 ("Implement time-base start/stop helpers.") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-ID: <20230629020713.327745-1-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Make HDECR underflow edge triggeredNicholas Piggin
HDEC interrupts are edge-triggered on HDECR underflow (notably different from DEC which is level-triggered). HDEC interrupts already clear the irq on delivery so that does not need to be changed. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230625122045.15544-1-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/psi: Allow access to PSI registers through xscomFrederic Barrat
skiboot only uses mmio to access the PSI registers (once the BAR is set) but we don't have any reason to block the accesses through xscom. This patch enables xscom access to the PSI registers. It converts the xscom addresses to mmio addresses, which requires a bit of care for the PSIHB, then reuse the existing mmio ops. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230630102609.193214-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-06Merge tag 'pull-9p-20230706' of https://github.com/cschoenebeck/qemu into ↵Richard Henderson
staging Administrative changes only: * Deprecate 9p 'proxy' backend. * Raise status of 9p to 'Maintained'. # -----BEGIN PGP SIGNATURE----- # # iQJLBAABCgA1FiEEltjREM96+AhPiFkBNMK1h2Wkc5UFAmSmkAsXHHFlbXVfb3Nz # QGNydWRlYnl0ZS5jb20ACgkQNMK1h2Wkc5We1xAAol+HbhQ2zNCJUbZ2/WY3Jf0H # K86DRQIs6w6UkL9msFz+id+tR5i50HoJ3+RnOKvy/fPqO8Rv6mb0d9r+bIG1JJCc # ubHP91x/nyDbP0XbLMtmtCz/T4g67E11Qqriq7lH1bPF7ccU3iXHZNup9HARjOoE # SQo9x4e7IDi1WdmM2vjvRXCh4ZLIlBv7c+2vAeP4V7FhJhDkL+1y+w6aCFw0xpd8 # lto3Egnhz6pk7+SJfQwCl3rfozHhCxlNmcNa+7vqckVFpdJrvtKOQB4cn9yVDPr/ # WjmYoB2J3MwYuZz+qAkdRJ6dUTLJb87YqJJe6lcKq0lqjiFBk7TccvIN9WgyJQd/ # eLUPCCyo98g9RCaPzjLc4MgbpCPCmqJkg8A1vJzykvq51BqJZcdkwfJ7LFmsvTSo # IfR1Seq4OUUzTZ2gWh8wJBNcPpAbilHzQnumxBEupe0Dg/pwoQWCywTYJN6Yf/6+ # PzcK39bVFKrEyc4Z1Y/yXvAzD7nX8X78kSHvxYYEQfzruLIVQjUUQ7Mp3TiJvljk # mLdcYqavjawgC2zmZU4L2Lx4Su7iVIkhNWj57WkfooSzLrAjueYQIJEltAt8Qmn6 # x3+u3xI/myNKujMpaqgTAU5Gk2J2UApshq5Zwe8HpnVwWoxS3QetXdA/f4AXwZOk # TpnKPYQa7edPLSSAbAs= # =GzjR # -----END PGP SIGNATURE----- # gpg: Signature made Thu 06 Jul 2023 10:57:31 AM BST # gpg: using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395 # gpg: issuer "qemu_oss@crudebyte.com" # gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 D5F4 # Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 7395 * tag 'pull-9p-20230706' of https://github.com/cschoenebeck/qemu: MAINTAINERS: raise status of 9p to 'Maintained' 9pfs: deprecate 'proxy' backend Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-06Merge tag 'pull-target-arm-20230706' of ↵Richard Henderson
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Add raw_writes ops for register whose write induce TLB maintenance * hw/arm/sbsa-ref: use XHCI to replace EHCI * Avoid splitting Zregs across lines in dump * Dump ZA[] when active * Fix SME full tile indexing * Handle IC IVAU to improve compatibility with JITs * xlnx-canfd-test: Fix code coverity issues * gdbstub: Guard M-profile code with CONFIG_TCG * allwinner-sramc: Set class_size * target/xtensa: Assert that interrupt level is within bounds * Avoid over-length shift in arm_cpu_sve_finalize() error case * Define new 'neoverse-v1' CPU type # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmSmwEEZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vBcD/4vKUw6klRV7vyz/KBr2AOi # Z1FnkLmOhwdp7CKvAVfU58TbPEJ8Fjo7OjziByV5nn/Ht9XrXcdl/E+0JamgrJ/n # G90ZfpoY3Boan4XBukBz/KX63sT1erF4io1NxbvqLxZ2mbZWNb0D1v2qkxC5zPFE # 97knlbSle4/VB8N6VgaPaWKVy5gmBZQwl7NUlFtB8TTZp3HPo0V77E9p1Wqpwpls # BNbqdtgUre3dlJci2f24PmXHYraKa68qk9xGnsSae96EY2+pOHbKhoZ/Fobaor2C # u+dfgQ3fY3aLDVKx8UESIUoqkGoVqwEbmt+pWG2rJiljLkdsI3ZsVq7p3+VGbLAN # berL14kCC2vRQYeNUwxeh5wdNVXc58xhWI5KXQRe8hr1dKWS5LQEHWgr7g7mb0+m # zPHqbdF4FR1DAV29vQ9WyK4zttrinFAYl+zvLyd8dX2ogoUeivR+4o3YX4hlFr4H # vcrglZbCGqAb3oKQG3PSGliS9GYtBwodLqKEH8PfcwfOP5PIcnSVc0Kl9DSzf7um # dAuYpaK/XW3MPx5qpWjnip4dRWUV5m/6nSCJr+fELEv3A0sGZY4pywv5NS/Yg1wE # nXdi8D+nyx9+AAiWTcB+ePsLuDEO2gYtubfqed99TFoJbL6/b4NbH8YE6cF3N/gY # lqFyvEIYNJZ9klf7XKnX2w== # =/MkB # -----END PGP SIGNATURE----- # gpg: Signature made Thu 06 Jul 2023 02:23:13 PM BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] * tag 'pull-target-arm-20230706' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case target/arm: Define neoverse-v1 target/arm: Suppress more TCG unimplemented features in ID registers target/xtensa: Assert that interrupt level is within bounds hw: arm: allwinner-sramc: Set class_size target/arm: gdbstub: Guard M-profile code with CONFIG_TCG tests/qtest: xlnx-canfd-test: Fix code coverity issues target/arm: Handle IC IVAU to improve compatibility with JITs target/arm: Fix SME full tile indexing target/arm: Dump ZA[] when active target/arm: Avoid splitting Zregs across lines in dump tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and id_aa64smfr0_el1 hw/arm/sbsa-ref: use XHCI to replace EHCI target/arm: Add raw_writes ops for register whose write induce TLB maintenance Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-06target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error casePeter Maydell
If you build QEMU with the clang sanitizer enabled, you can see it fire when running the arm-cpu-features test: $ QTEST_QEMU_BINARY=./build/arm-clang/qemu-system-aarch64 ./build/arm-clang/tests/qtest/arm-cpu-features [...] ../../target/arm/cpu64.c:125:19: runtime error: shift exponent 64 is too large for 64-bit type 'unsigned long long' [...] This happens because the user can specify some incorrect SVE properties that result in our calculating a max_vq of 0. We catch this and error out, but before we do that we calculate vq_mask = MAKE_64BIT_MASK(0, max_vq);$ and the MAKE_64BIT_MASK() call is only valid for lengths that are greater than zero, so we hit the undefined behaviour. Change the logic so that if max_vq is 0 we specifically set vq_mask to 0 without going via MAKE_64BIT_MASK(). This lets us drop the max_vq check from the error-exit logic, because if max_vq is 0 then vq_map must now be 0. The UB only happens in the case where the user passed us an incorrect set of SVE properties, so it's not a big problem in practice. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230704154332.3014896-1-peter.maydell@linaro.org
2023-07-06target/arm: Define neoverse-v1Peter Maydell
Now that we have implemented support for FEAT_LSE2, we can define a CPU model for the Neoverse-V1, and enable it for the virt and sbsa-ref boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230704130647.2842917-3-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-17 13:37:35 +0000