slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2023-05-06	target/loongarch: Implement vsat	Song Gao
2023-05-06	target/loongarch: Implement vdiv/vmod	Song Gao
2023-05-06	target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od}	Song Gao
2023-05-06	target/loongarch: Implement vmul/vmuh/vmulw{ev/od}	Song Gao
2023-05-06	target/loongarch: Implement vmax/vmin	Song Gao
2023-05-06	target/loongarch: Implement vadda	Song Gao
2023-05-06	target/loongarch: Implement vabsd	Song Gao
2023-05-06	target/loongarch: Implement vavg/vavgr	Song Gao
2023-05-06	target/loongarch: Implement vaddw/vsubw	Song Gao
2023-05-06	target/loongarch: Implement vhaddw/vhsubw	Song Gao
2023-05-06	target/loongarch: Implement vsadd/vssub	Song Gao
2023-05-06	target/loongarch: Implement vneg	Song Gao
2023-05-06	target/loongarch: Implement vaddi/vsubi	Song Gao
2023-05-06	target/loongarch: Implement vadd/vsub	Song Gao
2023-05-06	target/loongarch: Add CHECK_SXE maccro for check LSX enable	Song Gao
2023-05-06	target/loongarch: meson.build support build LSX	Song Gao
2023-05-06	target/loongarch: Add LSX data type VReg	Song Gao
2023-05-05	Merge tag 'pw-pull-request' of https://gitlab.com/marcandre.lureau/qemu into ...	Richard Henderson
2023-05-05	Merge tag 'migration-20230505-pull-request' of https://gitlab.com/juan.quinte...	Richard Henderson
2023-05-05	audio/pwaudio.c: Add Pipewire audio backend for QEMU	Dorinda Bassey
2023-05-05	Merge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/q...	Richard Henderson
2023-05-05	target/riscv: add Ventana's Veyron V1 CPU	Rahul Pathak
2023-05-05	riscv: Make sure an exception is raised if a pte is malformed	Alexandre Ghiti
2023-05-05	target/riscv: Fix Guest Physical Address Translation	Irina Ryapolova
2023-05-05	target/riscv: Restore the predicate() NULL check behavior	Bin Meng
2023-05-05	target/riscv: add TYPE_RISCV_DYNAMIC_CPU	Daniel Henrique Barboza
2023-05-05	target/riscv: add query-cpy-definitions support	Daniel Henrique Barboza
2023-05-05	target/riscv: add CPU QOM header	Daniel Henrique Barboza
2023-05-05	hw/intc/riscv_aplic: Zero init APLIC internal state	Ivan Klokov
2023-05-05	target/riscv: Reorg sum check in get_physical_address	Richard Henderson
2023-05-05	target/riscv: Reorg access check in get_physical_address	Richard Henderson
2023-05-05	target/riscv: Merge checks for reserved pte flags	Richard Henderson
2023-05-05	target/riscv: Don't modify SUM with is_debug	Richard Henderson
2023-05-05	target/riscv: Suppress pte update with is_debug	Richard Henderson
2023-05-05	target/riscv: Move leaf pte processing out of level loop	Richard Henderson
2023-05-05	target/riscv: Hoist pbmte and hade out of the level loop	Richard Henderson
2023-05-05	target/riscv: Hoist second stage mode change to callers	Richard Henderson
2023-05-05	target/riscv: Check SUM in the correct register	Richard Henderson
2023-05-05	target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index	Richard Henderson
2023-05-05	target/riscv: Move hstatus.spvp check to check_access_hlsv	Richard Henderson
2023-05-05	target/riscv: Introduce mmuidx_2stage	Richard Henderson
2023-05-05	target/riscv: Introduce mmuidx_priv	Richard Henderson
2023-05-05	target/riscv: Introduce mmuidx_sum	Richard Henderson
2023-05-05	target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT	Richard Henderson
2023-05-05	target/riscv: Handle HLV, HSV via helpers	Richard Henderson
2023-05-05	target/riscv: Use cpu_ld*_code_mmu for HLVX	Richard Henderson
2023-05-05	target/riscv: Reduce overhead of MSTATUS_SUM change	Fei Wu
2023-05-05	target/riscv: Separate priv from mmu_idx	Fei Wu
2023-05-05	target/riscv: Add a tb flags field for vstart	LIU Zhiwei
2023-05-05	target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags	Richard Henderson