slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2022-05-25	tests: Bump Fedora image version for cross-compilation	Konstantin Kostiuk
2022-05-25	trivial: qga: Log version on start	Konstantin Kostiuk
2022-05-25	qga: add guest-get-diskstats command for Linux guests	luzhipeng
2022-05-25	hw/gpio: replace HWADDR_PRIx with PRIx64	Jamin Lin
2022-05-25	hw/gpio support GPIO index mode for write operation.	Jamin Lin
2022-05-25	hw/gpio: Add ASPEED GPIO model for AST1030	Jamin Lin
2022-05-25	hw/gpio Add GPIO read/write trace event.	Jamin Lin
2022-05-25	hw: aspeed: Init all UART's with serial devices	Peter Delevoryas
2022-05-25	hw: aspeed: Introduce common UART init function	Peter Delevoryas
2022-05-25	hw: aspeed: Ensure AST1030 respects uart-default	Peter Delevoryas
2022-05-25	hw: aspeed: Add uarts_num SoC attribute	Peter Delevoryas
2022-05-25	hw: aspeed: Add missing UART's	Peter Delevoryas
2022-05-25	aspeed: Introduce a get_irq AspeedSoCClass method	Cédric Le Goater
2022-05-25	hw: m25p80: allow write_enable latch get/set	Iris Chen
2022-05-25	docs: aspeed: Add fby35 board	Peter Delevoryas
2022-05-25	hw/arm/aspeed: Add fby35 machine type	Peter Delevoryas
2022-05-25	docs: add minibmc section in aspeed document	Jamin Lin
2022-05-24	Merge tag 'pull-riscv-to-apply-20220525' of github.com:alistair23/qemu into s...	Richard Henderson
2022-05-24	hw/core: loader: Set is_linux to true for VxWorks uImage	Bin Meng
2022-05-24	hw/core: Sync uboot_image.h from U-Boot v2022.01	Bin Meng
2022-05-24	target/riscv: add zicsr/zifencei to isa_string	Hongren (Zenithal) Zheng
2022-05-24	hw/riscv: virt: Fix interrupt parent for dynamic platform devices	Anup Patel
2022-05-24	target/riscv: Set [m\|s]tval for both illegal and virtual instruction traps	Anup Patel
2022-05-24	target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode	Anup Patel
2022-05-24	target/riscv: Fix csr number based privilege checking	Anup Patel
2022-05-24	target/riscv: Fix typo of mimpid cpu option	Frank Chang
2022-05-24	target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize	Weiwei Li
2022-05-24	hw/riscv/sifive_u: Resolve redundant property accessors	Bernhard Beschow
2022-05-24	hw/vfio/pci-quirks: Resolve redundant property getters	Bernhard Beschow
2022-05-24	target/riscv: Move/refactor ISA extension checks	Tsukasa OI
2022-05-24	target/riscv: FP extension requirements	Tsukasa OI
2022-05-24	target/riscv: Change "G" expansion	Tsukasa OI
2022-05-24	target/riscv: Disable "G" by default	Tsukasa OI
2022-05-24	target/riscv: Fix coding style on "G" expansion	Tsukasa OI
2022-05-24	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	Tsukasa OI
2022-05-24	hw/riscv: Make CPU config error handling generous (virt/spike)	Tsukasa OI
2022-05-24	target/riscv: Add short-isa-string option	Tsukasa OI
2022-05-24	target/riscv: Move Zhinx* extensions on ISA string	Tsukasa OI
2022-05-24	hw/intc: Pass correct hartid while updating mtimecmp	Atish Patra
2022-05-24	target/riscv: rvv: Fix early exit condition for whole register load/store	eopXD
2022-05-24	target/riscv: Fix VS mode hypervisor CSR access	Dylan Reid
2022-05-23	linux-user/host/s390: Treat EX and EXRL as writes	Ilya Leoshkevich
2022-05-23	tests/tcg/s390x: Test unwinding from signal handlers	Ilya Leoshkevich
2022-05-23	linux-user/s390x: Fix unwinding from signal handlers	Ilya Leoshkevich
2022-05-23	linux-user: Remove pointless CPU{ARCH}State casts	Philippe Mathieu-Daudé
2022-05-23	linux-user: Have do_syscall() use CPUArchState* instead of void*	Philippe Mathieu-Daudé
2022-05-23	linux-user/elfload: Remove pointless non-const CPUArchState cast	Philippe Mathieu-Daudé
2022-05-23	linux-user/syscall.c: fix build without RLIMIT_RTTIME	Fabrice Fontaine
2022-05-23	hostmem: default the amount of prealloc-threads to smp-cpus	Jaroslav Jindrak
2022-05-23	target/i386: Remove LBREn bit check when access Arch LBR MSRs	Yang Weijiang