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2020-08-27virtio-pci: add virtio_pci_optimal_num_queues() helperStefan Hajnoczi
Multi-queue devices achieve the best performance when each vCPU has a dedicated queue. This ensures that virtqueue used notifications are handled on the same vCPU that submitted virtqueue buffers. When another vCPU handles the the notification an IPI will be necessary to wake the submission vCPU and this incurs a performance overhead. Provide a helper function that virtio-pci devices will use in later patches to automatically select the optimal number of queues. The function handles guests with large numbers of CPUs by limiting the number of queues to fit within the following constraints: 1. The maximum number of MSI-X vectors. 2. The maximum number of virtqueues. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200818143348.310613-4-stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-08-27Introduce a new flag for i440fx to disable PCI hotplug on the root busAni Sinha
We introduce a new global flag 'acpi-root-pci-hotplug' for i440fx with which we can turn on or off PCI device hotplug on the root bus. This flag can be used to prevent all PCI devices from getting hotplugged or unplugged from the root PCI bus. This feature is targetted mostly towards Windows VMs. It is useful in cases where some hypervisor admins want to deploy guest VMs in a way so that the users of the guest OSes are not able to hot-eject certain PCI devices from the Windows system tray. Laine has explained the use case here in detail: https://www.redhat.com/archives/libvir-list/2020-February/msg00110.html Julia has resolved this issue for PCIE buses with the following commit: 530a0963184e57e71a5b538 ("pcie_root_port: Add hotplug disabling option") This commit attempts to introduce similar behavior for PCI root buses used in i440fx machine types (although in this case, we do not have a per-slot capability to turn hotplug on or off). Usage: -global PIIX4_PM.acpi-root-pci-hotplug=off By default, this option is enabled which means that hotplug is turned on for the PCI root bus. The previously existing flag 'acpi-pci-hotplug-with-bridge-support' for PCI-PCI bridges remain as is and can be used along with this new flag to control PCI hotplug on PCI bridges. This change has been tested using a Windows 2012R2 server guest image and also with a Windows 2019 server guest image on a Ubuntu 18.04 host using the latest master qemu from upstream. Signed-off-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20200821165403.26589-1-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2020-08-27acpi: update expected DSDT files with _UID changesMichael S. Tsirkin
_UID of the PCI root has been changed to 0. Update expected files accordingly, and re-enable their testing. Full diff of changed files disassembly: diff -ru /tmp/old/tests/data/acpi/pc/DSDT.acpihmat.dsl /tmp/new/tests/data/acpi/pc/DSDT.acpihmat.dsl --- /tmp/old/tests/data/acpi/pc/DSDT.acpihmat.dsl 2020-08-04 17:37:55.727798633 -0400 +++ /tmp/new/tests/data/acpi/pc/DSDT.acpihmat.dsl 2020-08-04 17:42:57.258859861 -0400 @@ -50,7 +50,7 @@ { Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID } } diff -ru /tmp/old/tests/data/acpi/pc/DSDT.bridge.dsl /tmp/new/tests/data/acpi/pc/DSDT.bridge.dsl --- /tmp/old/tests/data/acpi/pc/DSDT.bridge.dsl 2020-08-04 17:37:55.737798601 -0400 +++ /tmp/new/tests/data/acpi/pc/DSDT.bridge.dsl 2020-08-04 17:42:57.262859849 -0400 @@ -50,7 +50,7 @@ { Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID } } diff -ru /tmp/old/tests/data/acpi/pc/DSDT.cphp.dsl /tmp/new/tests/data/acpi/pc/DSDT.cphp.dsl --- /tmp/old/tests/data/acpi/pc/DSDT.cphp.dsl 2020-08-04 17:37:55.745798576 -0400 +++ /tmp/new/tests/data/acpi/pc/DSDT.cphp.dsl 2020-08-04 17:42:57.265859839 -0400 @@ -50,7 +50,7 @@ { Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID } } diff -ru /tmp/old/tests/data/acpi/pc/DSDT.dimmpxm.dsl /tmp/new/tests/data/acpi/pc/DSDT.dimmpxm.dsl --- /tmp/old/tests/data/acpi/pc/DSDT.dimmpxm.dsl 2020-08-04 17:37:55.759798533 -0400 +++ /tmp/new/tests/data/acpi/pc/DSDT.dimmpxm.dsl 2020-08-04 17:42:57.268859830 -0400 @@ -52,7 +52,7 @@ { Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID } } diff -ru /tmp/old/tests/data/acpi/pc/DSDT.dsl /tmp/new/tests/data/acpi/pc/DSDT.dsl --- /tmp/old/tests/data/acpi/pc/DSDT.dsl 2020-08-04 17:37:55.713798676 -0400 +++ /tmp/new/tests/data/acpi/pc/DSDT.dsl 2020-08-04 17:42:57.256859867 -0400 @@ -50,7 +50,7 @@ { Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID } } diff -ru /tmp/old/tests/data/acpi/pc/DSDT.ipmikcs.dsl /tmp/new/tests/data/acpi/pc/DSDT.ipmikcs.dsl --- /tmp/old/tests/data/acpi/pc/DSDT.ipmikcs.dsl 2020-08-04 17:37:55.765798514 -0400 +++ /tmp/new/tests/data/acpi/pc/DSDT.ipmikcs.dsl 2020-08-04 17:42:57.270859824 -0400 @@ -50,7 +50,7 @@ { Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID } } diff -ru /tmp/old/tests/data/acpi/pc/DSDT.memhp.dsl /tmp/new/tests/data/acpi/pc/DSDT.memhp.dsl --- /tmp/old/tests/data/acpi/pc/DSDT.memhp.dsl 2020-08-04 17:37:55.773798489 -0400 +++ /tmp/new/tests/data/acpi/pc/DSDT.memhp.dsl 2020-08-04 17:42:57.273859814 -0400 @@ -50,7 +50,7 @@ { Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID } } diff -ru /tmp/old/tests/data/acpi/pc/DSDT.numamem.dsl /tmp/new/tests/data/acpi/pc/DSDT.numamem.dsl --- /tmp/old/tests/data/acpi/pc/DSDT.numamem.dsl 2020-08-04 17:37:55.782798461 -0400 +++ /tmp/new/tests/data/acpi/pc/DSDT.numamem.dsl 2020-08-04 17:42:57.276859805 -0400 @@ -50,7 +50,7 @@ { Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID } } diff -ru /tmp/old/tests/data/acpi/q35/DSDT.acpihmat.dsl /tmp/new/tests/data/acpi/q35/DSDT.acpihmat.dsl --- /tmp/old/tests/data/acpi/q35/DSDT.acpihmat.dsl 2020-08-04 17:37:55.911798060 -0400 +++ /tmp/new/tests/data/acpi/q35/DSDT.acpihmat.dsl 2020-08-04 17:42:57.327859646 -0400 @@ -51,7 +51,7 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1) diff -ru /tmp/old/tests/data/acpi/q35/DSDT.bridge.dsl /tmp/new/tests/data/acpi/q35/DSDT.bridge.dsl --- /tmp/old/tests/data/acpi/q35/DSDT.bridge.dsl 2020-08-04 17:37:55.920798032 -0400 +++ /tmp/new/tests/data/acpi/q35/DSDT.bridge.dsl 2020-08-04 17:42:57.331859634 -0400 @@ -51,7 +51,7 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1) diff -ru /tmp/old/tests/data/acpi/q35/DSDT.cphp.dsl /tmp/new/tests/data/acpi/q35/DSDT.cphp.dsl --- /tmp/old/tests/data/acpi/q35/DSDT.cphp.dsl 2020-08-04 17:37:55.930798001 -0400 +++ /tmp/new/tests/data/acpi/q35/DSDT.cphp.dsl 2020-08-04 17:42:57.336859618 -0400 @@ -51,7 +51,7 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1) diff -ru /tmp/old/tests/data/acpi/q35/DSDT.dimmpxm.dsl /tmp/new/tests/data/acpi/q35/DSDT.dimmpxm.dsl --- /tmp/old/tests/data/acpi/q35/DSDT.dimmpxm.dsl 2020-08-04 17:37:55.942797963 -0400 +++ /tmp/new/tests/data/acpi/q35/DSDT.dimmpxm.dsl 2020-08-04 17:42:57.340859606 -0400 @@ -53,7 +53,7 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1) diff -ru /tmp/old/tests/data/acpi/q35/DSDT.dsl /tmp/new/tests/data/acpi/q35/DSDT.dsl --- /tmp/old/tests/data/acpi/q35/DSDT.dsl 2020-08-04 17:37:55.898798100 -0400 +++ /tmp/new/tests/data/acpi/q35/DSDT.dsl 2020-08-04 17:42:57.323859659 -0400 @@ -51,7 +51,7 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1) diff -ru /tmp/old/tests/data/acpi/q35/DSDT.ipmibt.dsl /tmp/new/tests/data/acpi/q35/DSDT.ipmibt.dsl --- /tmp/old/tests/data/acpi/q35/DSDT.ipmibt.dsl 2020-08-04 17:37:55.952797932 -0400 +++ /tmp/new/tests/data/acpi/q35/DSDT.ipmibt.dsl 2020-08-04 17:42:57.344859593 -0400 @@ -51,7 +51,7 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1) diff -ru /tmp/old/tests/data/acpi/q35/DSDT.memhp.dsl /tmp/new/tests/data/acpi/q35/DSDT.memhp.dsl --- /tmp/old/tests/data/acpi/q35/DSDT.memhp.dsl 2020-08-04 17:37:55.962797901 -0400 +++ /tmp/new/tests/data/acpi/q35/DSDT.memhp.dsl 2020-08-04 17:42:57.348859581 -0400 @@ -51,7 +51,7 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1) diff -ru /tmp/old/tests/data/acpi/q35/DSDT.mmio64.dsl /tmp/new/tests/data/acpi/q35/DSDT.mmio64.dsl --- /tmp/old/tests/data/acpi/q35/DSDT.mmio64.dsl 2020-08-04 17:37:55.972797870 -0400 +++ /tmp/new/tests/data/acpi/q35/DSDT.mmio64.dsl 2020-08-04 17:42:57.351859572 -0400 @@ -51,7 +51,7 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1) diff -ru /tmp/old/tests/data/acpi/q35/DSDT.numamem.dsl /tmp/new/tests/data/acpi/q35/DSDT.numamem.dsl --- /tmp/old/tests/data/acpi/q35/DSDT.numamem.dsl 2020-08-04 17:37:55.983797836 -0400 +++ /tmp/new/tests/data/acpi/q35/DSDT.numamem.dsl 2020-08-04 17:42:57.354859562 -0400 @@ -51,7 +51,7 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1) diff -ru /tmp/old/tests/data/acpi/q35/DSDT.tis.dsl /tmp/new/tests/data/acpi/q35/DSDT.tis.dsl --- /tmp/old/tests/data/acpi/q35/DSDT.tis.dsl 2020-08-04 17:37:55.993797804 -0400 +++ /tmp/new/tests/data/acpi/q35/DSDT.tis.dsl 2020-08-04 17:42:57.358859550 -0400 @@ -51,7 +51,7 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_ADR, Zero) // _ADR: Address - Name (_UID, One) // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1) diff -ru /tmp/old/tests/data/acpi/virt/DSDT.dsl /tmp/new/tests/data/acpi/virt/DSDT.dsl --- /tmp/old/tests/data/acpi/virt/DSDT.dsl 2020-08-04 17:37:56.121797406 -0400 +++ /tmp/new/tests/data/acpi/virt/DSDT.dsl 2020-08-04 17:42:57.408859394 -0400 @@ -641,7 +641,7 @@ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment Name (_BBN, Zero) // _BBN: BIOS Bus Number - Name (_UID, "PCI0") // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_PRT, Package (0x80) // _PRT: PCI Routing Table diff -ru /tmp/old/tests/data/acpi/virt/DSDT.memhp.dsl /tmp/new/tests/data/acpi/virt/DSDT.memhp.dsl --- /tmp/old/tests/data/acpi/virt/DSDT.memhp.dsl 2020-08-04 17:37:56.129797381 -0400 +++ /tmp/new/tests/data/acpi/virt/DSDT.memhp.dsl 2020-08-04 17:42:57.411859385 -0400 @@ -643,7 +643,7 @@ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment Name (_BBN, Zero) // _BBN: BIOS Bus Number - Name (_UID, "PCI0") // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_PRT, Package (0x80) // _PRT: PCI Routing Table diff -ru /tmp/old/tests/data/acpi/virt/DSDT.numamem.dsl /tmp/new/tests/data/acpi/virt/DSDT.numamem.dsl --- /tmp/old/tests/data/acpi/virt/DSDT.numamem.dsl 2020-08-04 17:37:56.141797343 -0400 +++ /tmp/new/tests/data/acpi/virt/DSDT.numamem.dsl 2020-08-04 17:42:57.413859379 -0400 @@ -641,7 +641,7 @@ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment Name (_BBN, Zero) // _BBN: BIOS Bus Number - Name (_UID, "PCI0") // _UID: Unique ID + Name (_UID, Zero) // _UID: Unique ID Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_PRT, Package (0x80) // _PRT: PCI Routing Table Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-08-27disassemble-aml: -o actually worksMichael S. Tsirkin
Turns out that option was borken due to weird iasl command line handling. Fix it. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-08-27arm/acpi: fix an out of spec _UID for PCI rootMichael S. Tsirkin
On ARM/virt machine type QEMU currently reports an incorrect _UID in ACPI. The particular node in question is the primary PciRoot (PCI0 in ACPI), which gets assigned PCI0 in ACPI UID and 0 in the DevicePath. This is due to the _UID assigned to it by build_dsdt in hw/arm/virt-acpi-build.c Which does not correspond to the primary PCI identifier given by pcibus_num in hw/pci/pci.c In UEFI v2.8, section "10.4.2 Rules with ACPI _HID and _UID" ends with the paragraph, Root PCI bridges will use the plug and play ID of PNP0A03, This will be stored in the ACPI Device Path _HID field, or in the Expanded ACPI Device Path _CID field to match the ACPI name space. The _UID in the ACPI Device Path structure must match the _UID in the ACPI name space. (See especially the last sentence.) A similar bug has been reported on i386, on that architecture it has been reported to confuse at least macOS which uses ACPI UIDs to build the DevicePath for NVRAM boot options, while OVMF firmware gets them via an internal channel through QEMU. When UEFI firmware and ACPI have different values, this makes the underlying operating system unable to report its boot option. Cc: qemu-stable@nongnu.org Reported-by: Vitaly Cheptsov <vit9696@protonmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2020-08-27i386/acpi: fix inconsistent QEMU/OVMF device pathsMichael S. Tsirkin
macOS uses ACPI UIDs to build the DevicePath for NVRAM boot options, while OVMF firmware gets them via an internal channel through QEMU. Due to a bug in QEMU ACPI currently UEFI firmware and ACPI have different values, and this makes the underlying operating system unable to report its boot option. The particular node in question is the primary PciRoot (PCI0 in ACPI), which for some reason gets assigned 1 in ACPI UID and 0 in the DevicePath. This is due to the _UID assigned to it by build_dsdt in hw/i386/acpi-build.c Which does not correspond to the primary PCI identifier given by pcibus_num in hw/pci/pci.c Reference with the device paths, OVMF startup logs, and ACPI table dumps (SysReport): https://github.com/acidanthera/bugtracker/issues/1050 In UEFI v2.8, section "10.4.2 Rules with ACPI _HID and _UID" ends with the paragraph, Root PCI bridges will use the plug and play ID of PNP0A03, This will be stored in the ACPI Device Path _HID field, or in the Expanded ACPI Device Path _CID field to match the ACPI name space. The _UID in the ACPI Device Path structure must match the _UID in the ACPI name space. (See especially the last sentence.) Considering *extra* root bridges / root buses (with bus number > 0), QEMU's ACPI generator actually does the right thing; since QEMU commit c96d9286a6d7 ("i386/acpi-build: more traditional _UID and _HID for PXB root buses", 2015-06-11). However, the _UID values for root bridge zero (on both i440fx and q35) have always been "wrong" (from UEFI perspective), going back in QEMU to commit 74523b850189 ("i386: add ACPI table files from seabios", 2013-10-14). Even in SeaBIOS, these _UID values have always been 1; see commit a4d357638c57 ("Port rombios32 code from bochs-bios.", 2008-03-08) for i440fx, and commit ecbe3fd61511 ("seabios: q35: add dsdt", 2012-12-01) for q35. Cc: qemu-stable@nongnu.org Suggested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Vitaly Cheptsov <vit9696@protonmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2020-08-27acpi: allow DSDT changesMichael S. Tsirkin
We are updating all DSDTs with UID 0 for PCI Root. Allow changes. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-08-26Merge remote-tracking branch ↵Peter Maydell
'remotes/hdeller/tags/target-hppa-v3-pull-request' into staging artist out of bounds fixes # gpg: Signature made Wed 26 Aug 2020 22:09:55 BST # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * remotes/hdeller/tags/target-hppa-v3-pull-request: hw/display/artist: Fix invalidation of lines near screen border hw/display/artist: Fix invalidation of lines in artist_draw_line() hw/display/artist: Unbreak size mismatch memory accesses hw/display/artist: Prevent out of VRAM buffer accesses Revert "hw/display/artist: Avoid drawing line when nothing to display" hw/display/artist: Refactor artist_rop8() to avoid buffer over-run hw/display/artist: Check offset in draw_line to avoid buffer over-run hw/hppa/lasi: Don't abort on invalid IMR value hw/display/artist.c: fix out of bounds check hw/hppa: Implement proper SeaBIOS version check seabios-hppa: Update to SeaBIOS hppa version 1 hw/hppa: Sync hppa_hardware.h file with SeaBIOS sources Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-26hw/display/artist: Fix invalidation of lines near screen borderSven Schnelle
If parts of the invalidated screen lines are outside of the VRAM buffer, the code skips the whole invalidate. This is incorrect when only parts of the buffer are invisble - which is the case when the mouse cursor is located near the screen border. Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Helge Deller <deller@gmx.de>
2020-08-26hw/display/artist: Fix invalidation of lines in artist_draw_line()Sven Schnelle
The old code didn't invalidate correctly when vertical lines were drawn. Fix this and move the invalidation out of the loop. Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Helge Deller <deller@gmx.de>
2020-08-26hw/display/artist: Unbreak size mismatch memory accessesHelge Deller
Commit 5d971f9e6725 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid") broke the artist driver in a way that the dtwm window manager on HP-UX rendered wrong. Fixes: 5d971f9e6725 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid") Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Helge Deller <deller@gmx.de>
2020-08-26hw/display/artist: Prevent out of VRAM buffer accessesHelge Deller
Simplify various bounds checks by changing parameters like row and column numbers to become unsigned instead of signed. With that we can check if the calculated offset is bigger than the size of the VRAM region and bail out if not. Reported-by: LLVM libFuzzer Reported-by: Alexander Bulekov <alxndr@bu.edu> Buglink: https://bugs.launchpad.net/qemu/+bug/1880326 Buglink: https://bugs.launchpad.net/qemu/+bug/1890310 Buglink: https://bugs.launchpad.net/qemu/+bug/1890311 Buglink: https://bugs.launchpad.net/qemu/+bug/1890312 Buglink: https://bugs.launchpad.net/qemu/+bug/1890370 Acked-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Helge Deller <deller@gmx.de>
2020-08-26Revert "hw/display/artist: Avoid drawing line when nothing to display"Helge Deller
This reverts commit b0f6455feac97e41045ee394e11c24d92c370f6e. It's wrong. A line could even be a dot. Signed-off-by: Helge Deller <deller@gmx.de>
2020-08-26hw/display/artist: Refactor artist_rop8() to avoid buffer over-runPhilippe Mathieu-Daudé
Invalid I/O writes can craft an offset out of the vram_buffer range. Instead of passing an unsafe pointer to artist_rop8(), pass the vram_buffer and the offset. We can now check if the offset is in range before accessing it. We avoid: Program terminated with signal SIGSEGV, Segmentation fault. 284 *dst &= ~plane_mask; (gdb) bt #0 0x000056367b2085c0 in artist_rop8 (s=0x56367d38b510, dst=0x7f9f972fffff <error: Cannot access memory at address 0x7f9f972fffff>, val=0 '\000') at hw/display/artist.c:284 #1 0x000056367b209325 in draw_line (s=0x56367d38b510, x1=-20480, y1=-1, x2=0, y2=17920, update_start=true, skip_pix=-1, max_pix=-1) at hw/display/artist.c:646 Reported-by: LLVM libFuzzer Buglink: https://bugs.launchpad.net/qemu/+bug/1880326 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Helge Deller <deller@gmx.de>
2020-08-26hw/display/artist: Check offset in draw_line to avoid buffer over-runPhilippe Mathieu-Daudé
Invalid I/O writes can craft an offset out of the vram_buffer range. We avoid: Program terminated with signal SIGSEGV, Segmentation fault. 284 *dst &= ~plane_mask; (gdb) bt #0 0x000055d5dccdc5c0 in artist_rop8 (s=0x55d5defee510, dst=0x7f8e84ed8216 <error: Cannot access memory at address 0x7f8e84ed8216>, val=0 '\000') at hw/display/artist.c:284 #1 0x000055d5dccdcf83 in fill_window (s=0x55d5defee510, startx=22, starty=5674, width=65, height=5697) at hw/display/artist.c:551 #2 0x000055d5dccddfb9 in artist_reg_write (opaque=0x55d5defee510, addr=1051140, val=4265537, size=4) at hw/display/artist.c:902 #3 0x000055d5dcb42a7c in memory_region_write_accessor (mr=0x55d5defeea10, addr=1051140, value=0x7ffe57db08c8, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:483 Reported-by: LLVM libFuzzer Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Helge Deller <deller@gmx.de>
2020-08-26hw/hppa/lasi: Don't abort on invalid IMR valueHelge Deller
NetBSD initializes the LASI IMR value with 0xffffffff to disable all LASI interrupts. This triggered an assert() and stopped the emulation. By replacing the check with a warning in the guest log we now allow NetBSD to boot again. Signed-off-by: Helge Deller <deller@gmx.de>
2020-08-26Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-08-26' ↵Peter Maydell
into staging Block patches: - qcow2 subclusters (extended L2 entries) # gpg: Signature made Wed 26 Aug 2020 08:37:04 BST # gpg: using RSA key 91BEB60A30DB3E8857D11829F407DB0061D5CF40 # gpg: issuer "mreitz@redhat.com" # gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full] # Primary key fingerprint: 91BE B60A 30DB 3E88 57D1 1829 F407 DB00 61D5 CF40 * remotes/maxreitz/tags/pull-block-2020-08-26: (34 commits) iotests: Add tests for qcow2 images with extended L2 entries qcow2: Assert that expand_zero_clusters_in_l1() does not support subclusters qcow2: Allow preallocation and backing files if extended_l2 is set qcow2: Add the 'extended_l2' option and the QCOW2_INCOMPAT_EXTL2 bit qcow2: Add prealloc field to QCowL2Meta qcow2: Add subcluster support to qcow2_measure() qcow2: Add subcluster support to qcow2_co_pwrite_zeroes() qcow2: Add subcluster support to handle_alloc_space() qcow2: Clear the L2 bitmap when allocating a compressed cluster qcow2: Update L2 bitmap in qcow2_alloc_cluster_link_l2() qcow2: Add subcluster support to check_refcounts_l2() qcow2: Add subcluster support to discard_in_l2_slice() qcow2: Add subcluster support to zero_in_l2_slice() qcow2: Add subcluster support to qcow2_get_host_offset() qcow2: Add subcluster support to calculate_l2_meta() qcow2: Handle QCOW2_SUBCLUSTER_UNALLOCATED_ALLOC qcow2: Replace QCOW2_CLUSTER_* with QCOW2_SUBCLUSTER_* qcow2: Add cluster type parameter to qcow2_get_host_offset() qcow2: Add qcow2_cluster_is_allocated() qcow2: Add qcow2_get_subcluster_range_type() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-26iotests: Add tests for qcow2 images with extended L2 entriesAlberto Garcia
Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <e6dd0429cafe84ca603179c298a8703bddca2904.1594396418.git.berto@igalia.com> [mreitz: Use env in shebang line] Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-08-25Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20200825' into staging This pull request first adds support for multi-socket NUMA RISC-V machines. The Spike and Virt machines both support NUMA sockets. This PR also updates the current experimental Hypervisor support to the v0.6.1 spec. # gpg: Signature made Tue 25 Aug 2020 19:47:41 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200825: target/riscv: Support the Virtual Instruction fault target/riscv: Return the exception from invalid CSR accesses target/riscv: Support the v0.6 Hypervisor extension CRSs target/riscv: Only support little endian guests target/riscv: Only support a single VSXL length target/riscv: Update the CSRs to the v0.6 Hyp extension target/riscv: Update the Hypervisor trap return/entry target/riscv: Fix the interrupt cause code target/riscv: Convert MSTATUS MTL to GVA target/riscv: Don't allow guest to write to htinst target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions target/riscv: Allow generating hlv/hlvx/hsv instructions target/riscv: Allow setting a two-stage lookup in the virt status hw/riscv: virt: Allow creating multiple NUMA sockets hw/riscv: spike: Allow creating multiple NUMA sockets hw/riscv: Add helpers for RISC-V multi-socket NUMA machines hw/riscv: Allow creating multiple instances of PLIC hw/riscv: Allow creating multiple instances of CLINT Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com Message-Id: <4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Return the exception from invalid CSR accessesAlistair Francis
When performing a CSR access let's return a negative exception value on an error instead of -1. This will allow us to specify the exception in future patches. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com Message-Id: <a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com Message-Id: <644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Only support little endian guestsAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com Message-Id: <93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Only support a single VSXL lengthAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com Message-Id: <f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com Message-Id: <4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com Message-Id: <e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Fix the interrupt cause codeAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com Message-Id: <85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com Message-Id: <9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Don't allow guest to write to htinstAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: ca5359fec6b2aff851eef3b3bc4b53cb5d4ad194.1597259519.git.alistair.francis@wdc.com Message-Id: <ca5359fec6b2aff851eef3b3bc4b53cb5d4ad194.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructionsAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com Message-Id: <024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com Message-Id: <08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com>
2020-08-25hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel
We extend RISC-V virt machine to allow creating a multi-socket machine. Each RISC-V virt machine socket is a NUMA node having a set of HARTs, a memory instance, a CLINT instance, and a PLIC instance. Other devices are shared between all sockets. We also update the generated device tree accordingly. By default, NUMA multi-socket support is disabled for RISC-V virt machine. To enable it, users can use "-numa" command-line options of QEMU. Example1: For two NUMA nodes with 2 CPUs each, append following to command-line options: "-smp 4 -numa node -numa node" Example2: For two NUMA nodes with 1 and 3 CPUs, append following to command-line options: "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \ -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \ -numa cpu,node-id=1,core-id=3" The maximum number of sockets in a RISC-V virt machine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-6-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-08-25hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel
We extend RISC-V spike machine to allow creating a multi-socket machine. Each RISC-V spike machine socket is a NUMA node having a set of HARTs, a memory instance, and a CLINT instance. Other devices are shared between all sockets. We also update the generated device tree accordingly. By default, NUMA multi-socket support is disabled for RISC-V spike machine. To enable it, users can use "-numa" command-line options of QEMU. Example1: For two NUMA nodes with 2 CPUs each, append following to command-line options: "-smp 4 -numa node -numa node" Example2: For two NUMA nodes with 1 and 3 CPUs, append following to command-line options: "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \ -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \ -numa cpu,node-id=1,core-id=3" The maximum number of sockets in a RISC-V spike machine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-5-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-08-25hw/riscv: Add helpers for RISC-V multi-socket NUMA machinesAnup Patel
We add common helper routines which can be shared by RISC-V multi-socket NUMA machines. We have two types of helpers: 1. riscv_socket_xyz() - These helper assist managing multiple sockets irrespective whether QEMU NUMA is enabled/disabled 2. riscv_numa_xyz() - These helpers assist in providing necessary QEMU machine callbacks for QEMU NUMA emulation Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-4-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel
We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200616032229.766089-3-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel
We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-Id: <20200616032229.766089-2-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-08-25Merge remote-tracking branch ↵Peter Maydell
'remotes/berrange/tags/socket-next-pull-request' into staging Add support for UNIX sockets in the abstract namespace # gpg: Signature made Tue 25 Aug 2020 11:52:22 BST # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/socket-next-pull-request: tests: fix a memory in test_socket_unix_abstract_good Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-25tests: fix a memory in test_socket_unix_abstract_goodLi Qiang
After build qemu with '-fsanitize=address' extra-cflags, 'make check' show following leak: ================================================================= ==44580==ERROR: LeakSanitizer: detected memory leaks Direct leak of 2500 byte(s) in 1 object(s) allocated from: #0 0x7f1b5a8b8d28 in __interceptor_calloc (/usr/lib/x86_64-linux-gnu/libasan.so.4+0xded28) #1 0x7f1b5a514b10 in g_malloc0 (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x51b10) #2 0xd79ea4e4c0ad31c3 (<unknown module>) SUMMARY: AddressSanitizer: 2500 byte(s) leaked in 1 allocation(s). Call 'g_rand_free' in the end of function to avoid this. Fixes: 4d3a329af59("tests/util-sockets: add abstract unix socket cases") Signed-off-by: Li Qiang <liq3ea@163.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:  xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2020-08-25Merge remote-tracking branch ↵Peter Maydell
'remotes/kraxel/tags/fixes-20200825-pull-request' into staging meson: keymap fixes # gpg: Signature made Tue 25 Aug 2020 07:19:15 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/fixes-20200825-pull-request: meson: avoid compiling qemu-keymap by default meson: move xkbcommon to meson meson: drop keymaps symlink Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-25qcow2: Assert that expand_zero_clusters_in_l1() does not support subclustersAlberto Garcia
This function is only used by qcow2_expand_zero_clusters() to downgrade a qcow2 image to a previous version. This would require transforming all extended L2 entries into normal L2 entries but this is not a simple task and there are no plans to implement this at the moment. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <15e65112b4144381b4d8c0bdf8fb76b0d813e3d1.1594396418.git.berto@igalia.com> [mreitz: Fixed comment style] Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-08-25qcow2: Allow preallocation and backing files if extended_l2 is setAlberto Garcia
Traditional qcow2 images don't allow preallocation if a backing file is set. This is because once a cluster is allocated there is no way to tell that its data should be read from the backing file. Extended L2 entries have individual allocation bits for each subcluster, and therefore it is perfectly possible to have an allocated cluster with all its subclusters unallocated. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <6d5b0f38e7dc5f2f31d8cab1cb92044e9909aece.1594396418.git.berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-08-25qcow2: Add the 'extended_l2' option and the QCOW2_INCOMPAT_EXTL2 bitAlberto Garcia
Now that the implementation of subclusters is complete we can finally add the necessary options to create and read images with this feature, which we call "extended L2 entries". Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <6476caaa73216bd05b7bb2d504a20415e1665176.1594396418.git.berto@igalia.com> [mreitz: %s/5\.1/5.2/; fixed 302's and 303's reference output] Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-08-25qcow2: Add prealloc field to QCowL2MetaAlberto Garcia
This field allows us to indicate that the L2 metadata update does not come from a write request with actual data but from a preallocation request. For traditional images this does not make any difference, but for images with extended L2 entries this means that the clusters are allocated normally in the L2 table but individual subclusters are marked as unallocated. This will allow preallocating images that have a backing file. There is one special case: when we resize an existing image we can also request that the new clusters are preallocated. If the image already had a backing file then we have to hide any possible stale data and zero out the new clusters (see commit 955c7d6687 for more details). In this case the subclusters cannot be left as unallocated so the L2 bitmap must be updated. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <960d4c444a4f5a870e2b47e5da322a73cd9a2f5a.1594396418.git.berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-08-25qcow2: Add subcluster support to qcow2_measure()Alberto Garcia
Extended L2 entries are bigger than normal L2 entries so this has an impact on the amount of metadata needed for a qcow2 file. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <7efae2efd5e36b42d2570743a12576d68ce53685.1594396418.git.berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-08-25qcow2: Add subcluster support to qcow2_co_pwrite_zeroes()Alberto Garcia
This works now at the subcluster level and pwrite_zeroes_alignment is updated accordingly. qcow2_cluster_zeroize() is turned into qcow2_subcluster_zeroize() with the following changes: - The request can now be subcluster-aligned. - The cluster-aligned body of the request is still zeroized using zero_in_l2_slice() as before. - The subcluster-aligned head and tail of the request are zeroized with the new zero_l2_subclusters() function. There is just one thing to take into account for a possible future improvement: compressed clusters cannot be partially zeroized so zero_l2_subclusters() on the head or the tail can return -ENOTSUP. This makes the caller repeat the *complete* request and write actual zeroes to disk. This is sub-optimal because 1) if the head area was compressed we would still be able to use the fast path for the body and possibly the tail. 2) if the tail area was compressed we are writing zeroes to the head and the body areas, which are already zeroized. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <17e05e2ee7e12f10dcf012da81e83ebe27eb3bef.1594396418.git.berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-08-25qcow2: Add subcluster support to handle_alloc_space()Alberto Garcia
The bdrv_co_pwrite_zeroes() call here fills complete clusters with zeroes, but it can happen that some subclusters are not part of the write request or the copy-on-write. This patch makes sure that only the affected subclusters are overwritten. A potential improvement would be to also fill with zeroes the other subclusters if we can guarantee that we are not overwriting existing data. However this would waste more disk space, so we should first evaluate if it's really worth doing. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <b3dc97e8e2240ddb5191a4f930e8fc9653f94621.1594396418.git.berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-08-25qcow2: Clear the L2 bitmap when allocating a compressed clusterAlberto Garcia
Compressed clusters always have the bitmap part of the extended L2 entry set to 0. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <04455b3de5dfeb9d1cfe1fc7b02d7060a6e09710.1594396418.git.berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-08-25qcow2: Update L2 bitmap in qcow2_alloc_cluster_link_l2()Alberto Garcia
The L2 bitmap needs to be updated after each write to indicate what new subclusters are now allocated. This needs to happen even if the cluster was already allocated and the L2 entry was otherwise valid. In some cases however a write operation doesn't need change the L2 bitmap (because all affected subclusters were already allocated). This is detected in calculate_l2_meta(), and qcow2_alloc_cluster_link_l2() is never called in those cases. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <0875620d49f44320334b6a91c73b3f301f975f38.1594396418.git.berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-08-25qcow2: Add subcluster support to check_refcounts_l2()Alberto Garcia
The offset field of an uncompressed cluster's L2 entry must be aligned to the cluster size, otherwise it is invalid. If the cluster has no data then it means that the offset points to a preallocation, so we can clear the offset field without affecting the guest-visible data. This is what 'qemu-img check' does when run in repair mode. On traditional qcow2 images this can only happen when QCOW_OFLAG_ZERO is set, and repairing such entries turns the clusters from ZERO_ALLOC into ZERO_PLAIN. Extended L2 entries have no ZERO_ALLOC clusters and no QCOW_OFLAG_ZERO but the idea is the same: if none of the subclusters are allocated then we can clear the offset field and leave the bitmap untouched. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <9f4ed1d0a34b0a545b032c31ecd8c14734065342.1594396418.git.berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-19 05:20:28 +0000