slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2021-09-21	include/exec: Move cpu_signal_handler declaration	Richard Henderson
2021-09-21	Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...	Richard Henderson
2021-09-21	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921'...	Peter Maydell
2021-09-21	target/arm: Optimize MVE 1op-immediate insns	Peter Maydell
2021-09-21	target/arm: Optimize MVE VSLI and VSRI	Peter Maydell
2021-09-21	target/arm: Optimize MVE VSHLL and VMOVL	Peter Maydell
2021-09-21	target/arm: Optimize MVE VSHL, VSHR immediate forms	Peter Maydell
2021-09-21	target/arm: Optimize MVE VMVN	Peter Maydell
2021-09-21	target/arm: Optimize MVE VDUP	Peter Maydell
2021-09-21	target/arm: Optimize MVE VNEG, VABS	Peter Maydell
2021-09-21	target/arm: Optimize MVE arithmetic ops	Peter Maydell
2021-09-21	target/arm: Optimize MVE logic ops	Peter Maydell
2021-09-21	target/arm: Add TB flag for "MVE insns not predicated"	Peter Maydell
2021-09-21	target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration	Peter Maydell
2021-09-21	target/arm: Avoid goto_tb if we're trying to exit to the main loop	Peter Maydell
2021-09-21	hvf: arm: Add rudimentary PMC support	Alexander Graf
2021-09-21	arm: Add Hypervisor.framework build target	Alexander Graf
2021-09-21	hvf: arm: Implement PSCI handling	Alexander Graf
2021-09-21	hvf: arm: Implement -cpu host	Peter Maydell
2021-09-21	arm/hvf: Add a WFI handler	Peter Collingbourne
2021-09-21	Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210920' int...	Peter Maydell
2021-09-21	hw/riscv: opentitan: Correct the USB Dev address	Alistair Francis
2021-09-21	target/riscv: csr: Rename HCOUNTEREN_CY and friends	Bin Meng
2021-09-21	target/riscv: Backup/restore mstatus.SD bit when virtual register swapped	Frank Chang
2021-09-21	docs/system/riscv: sifive_u: Update U-Boot instructions	Bin Meng
2021-09-21	hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer	Frank Chang
2021-09-21	hw/dma: sifive_pdma: allow non-multiple transaction size transactions	Green Wan
2021-09-21	hw/dma: sifive_pdma: claim bit must be set before DMA transactions	Frank Chang
2021-09-21	hw/dma: sifive_pdma: reset Next* registers when Control.claim is set	Frank Chang
2021-09-21	hw/riscv: virt: Add optional ACLINT support to virt machine	Anup Patel
2021-09-21	hw/riscv: virt: Re-factor FDT generation	Anup Patel
2021-09-21	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	Anup Patel
2021-09-21	hw/intc: Rename sifive_clint sources to riscv_aclint sources	Anup Patel
2021-09-21	sifive_u: Connect the SiFive PWM device	Alistair Francis
2021-09-21	hw/timer: Add SiFive PWM support	Alistair Francis
2021-09-21	hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines	Alistair Francis
2021-09-21	hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines	Alistair Francis
2021-09-21	hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines	Alistair Francis
2021-09-21	hw/intc: sifive_clint: Use RISC-V CPU GPIO lines	Alistair Francis
2021-09-21	target/riscv: Expose interrupt pending bits as GPIO lines	Alistair Francis
2021-09-21	target/riscv: Fix satp write	LIU Zhiwei
2021-09-21	target/riscv: Update the ePMP CSR address	Alistair Francis
2021-09-20	Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into st...	Peter Maydell
2021-09-20	Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' ...	Peter Maydell
2021-09-20	hvf: Add Apple Silicon support	Alexander Graf
2021-09-20	hvf: Introduce hvf_arch_init() callback	Alexander Graf
2021-09-20	hvf: Add execute to dirty log permission bitmap	Alexander Graf
2021-09-20	arm: Move PMC register definitions to internals.h	Alexander Graf
2021-09-20	hw/intc: Set GIC maintenance interrupt level to only 0 or 1	Shashi Mallela
2021-09-20	target/arm: Consolidate ifdef blocks in reset	Peter Maydell