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2019-09-17riscv: roms: Update default bios for sifive_u machineBin Meng
2019-09-17riscv: sifive_u: Change UART node name in device treeBin Meng
2019-09-17riscv: sifive_u: Update UART base addresses and IRQsBin Meng
2019-09-17riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng
2019-09-17riscv: sifive_u: Add PRCI block to the SoCBin Meng
2019-09-17riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng
2019-09-17riscv: sifive: Implement PRCI model for FU540Bin Meng
2019-09-17riscv: sifive_u: Update PLIC hart topology configuration stringBin Meng
2019-09-17riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng
2019-09-17riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng
2019-09-17riscv: hart: Add a "hartid-base" property to RISC-V hart arrayBin Meng
2019-09-17riscv: hart: Extract hart realize to a separate routineBin Meng
2019-09-17riscv: Add a sifive_cpu.h to include both E and U cpu type definesBin Meng
2019-09-17riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng
2019-09-17riscv: sifive_e: prci: Update the PRCI register block sizeBin Meng
2019-09-17riscv: sifive_e: prci: Fix a typo of hfxosccfg register programmingBin Meng
2019-09-17riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng
2019-09-17riscv: sifive_u: Remove the unnecessary include of prci headerBin Meng
2019-09-17riscv: roms: Remove executable attribute of opensbi imagesBin Meng
2019-09-17riscv: hw: Remove the unnecessary include of target/riscv/cpu.hBin Meng
2019-09-17riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) insteadBin Meng
2019-09-17riscv: hw: Change create_fdt() to return voidBin Meng
2019-09-17riscv: hw: Remove not needed PLIC properties in device treeBin Meng
2019-09-17riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cellBin Meng
2019-09-17riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng
2019-09-17riscv: hw: Remove duplicated "hw/hw.h" inclusionBin Meng
2019-09-17riscv: sifive_test: Add reset functionalityBin Meng
2019-09-17riscv: hmp: Add a command to show virtual memory mappingsBin Meng
2019-09-17riscv: Resolve full path of the given bios imageBin Meng
2019-09-17riscv: Add a helper routine for finding firmwareBin Meng
2019-09-17riscv: rv32: Root page table address can be larger than 32-bitBin Meng
2019-09-17target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis
2019-09-17riscv: plic: Remove unused interrupt functionsAlistair Francis
2019-09-17target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace eventsPhilippe Mathieu-Daudé
2019-09-17target/riscv/pmp: Restrict priviledged PMP to system-mode emulationPhilippe Mathieu-Daudé
2019-09-17riscv: sifive_u: Fix clock-names property for ethernet nodeGuenter Roeck
2019-09-17riscv: sivive_u: Add dummy serial clock and aliases entry for uartGuenter Roeck
2019-09-17riscv: sifive_u: Add support for loading initrdGuenter Roeck
2019-09-17target/sparc: Switch to do_transaction_failed() hookPeter Maydell
2019-09-17target/sparc: Remove unused ldl_phys from dump_mmu()Peter Maydell
2019-09-17target/sparc: Handle bus errors in mmu_probe()Peter Maydell
2019-09-17target/sparc: Correctly handle bus errors in page table walksPeter Maydell
2019-09-17target/sparc: Check for transaction failures in MXCC stream ASI accessesPeter Maydell
2019-09-17target/sparc: Check for transaction failures in MMU passthrough ASIsPeter Maydell
2019-09-17target/sparc: Factor out the body of sparc_cpu_unassigned_access()Peter Maydell
2019-09-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2019-09-16hw/i386/pc: Extract the x86 generic fw_cfg codePhilippe Mathieu-Daudé
2019-09-16hw/i386/pc: Rename pc_build_feature_control() as generic fw_cfg_build_*Philippe Mathieu-Daudé
2019-09-16hw/i386/pc: Let pc_build_feature_control() take a MachineState argumentPhilippe Mathieu-Daudé