aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2011-10-06PPC: Enable to use PAPR with PR style KVMAlexander Graf
When running PR style KVM, we need to tell the kernel that we want to run in PAPR mode now. This means that we need to pass some more register information down and enable papr mode. We also need to align the HTAB to htab_size boundary. Using this patch, -M pseries works with kvm even on non-hv kvm implementations, as long as the preceding kernel patches are in. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - match on CONFIG_PSERIES v2 -> v3: - remove HIOR pieces from PAPR patch (ABI breakage)
2011-10-06KVM: update kernel headersAlexander Graf
This patch updates the kvm kernel headers to the latest version. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Add new target config for pseriesAlexander Graf
We only support -M pseries when certain prerequisites are met, such as a PPC64 guest and libfdt. To only gather these requirements in a single place, this patch introduces a new CONFIG_PSERIES variable that gets set when all prerequisites are met. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Bump CPU count to 15Alexander Graf
Now that we have everything in place, make the machine description aware of the fact that we can now handle 15 virtual CPUs! Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - Max cpus is 15 because of MPIC
2011-10-06MPC8544DS: Generate CPU nodes on initAlexander Graf
With this patch, we generate CPU nodes in the machine initialization, giving us the freedom to generate as many nodes as we want and as the machine supports, but only those. This is a first step towards a much cleaner device tree generation infrastructure, where we would not require precompiled dtb blobs anymore. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06MPC8544DS: Remove CPU nodesAlexander Graf
We want to generate the CPU nodes in machine init code, so remove them from the device tree definition that we precompile. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06device tree: give dt more sizeAlexander Graf
We currently load a device tree blob and then just take its size x2 to account for modifications we do inside. While this is nice and great, it fails when we have a small device tree as blob and lots of nodes added in machine init code. So for now, just make it 20k bigger than it was before. We maybe want to be more clever about this later. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06device tree: dont fail operationsAlexander Graf
When we screw up and issue an FDT command that doesn't work, we really need to know immediately and usually can't continue to create the machine. To make sure we don't need to add error checking in all device tree modification code users, we can just add the fail checks to the qemu abstract functions. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06device tree: add add_subnode commandAlexander Graf
We want to be able to create subnodes in our device tree, so export it through the qemu device tree abstraction framework. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Update cpu-release-addr property in cpu nodesAlexander Graf
The guest OS wants to know where the guest spins, so let's tell him while updating the CPU nodes with the frequencies anyways. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - use new spin table address
2011-10-06PPC: E500: Add PV spinning codeAlexander Graf
CPUs that are not the boot CPU need to run in spinning code to check if they should run off to execute and if so where to jump to. This usually happens by leaving secondary CPUs looping and checking if some variable in memory changed. In an environment like Qemu however we can be more clever. We can just export the spin table the primary CPU modifies as MMIO region that would event based wake up the respective secondary CPUs. That saves us quite some cycles while the secondary CPUs are not up yet. So this patch adds a PV device that simply exports the spinning table into the guest and thus allows the primary CPU to wake up secondary ones. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - change into MMIO scheme - map the secondary NIP instead of 0 1:1 - only map 64MB for TLB, same as u-boot - prepare code for 64-bit spinnings v2 -> v3: - remove r6 - set MAS2_M - map EA 0 - use second TLB1 entry v3 -> v4: - change to memoryops v4 -> v5: - fix endianness bugs v5 -> v6: - add header
2011-10-06PPC: E500: Remove unneeded CPU nodesAlexander Graf
We should only keep CPU nodes in the device tree around that we really have virtual CPUs for. So remove all superfluous entries that we just keep there in case someone wants to create a lot of vCPUs. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Update freqs for all CPUsAlexander Graf
Now that we can so nicely find out the host's frequencies, we should also make sure that we get them into all virtual CPUs' device tree nodes. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: KVM: Add stubs for kvm helper functionsAlexander Graf
We have a bunch of helper functions that don't have any stubs for them in case we don't have CONFIG_KVM enabled. That didn't bite us so far, because gcc can optimize them out pretty well, but we should really provide them. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - use uint64_t for clockfreq
2011-10-06PPC: KVM: Remove kvmppc_read_host_propertyAlexander Graf
We just got rid of the last user of kvmppc_read_host_property, so we can now safely remove it. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: bamboo: Use kvm api for freq and clock frequenciesAlexander Graf
Now that we have nice and shiny APIs to read out the host's clock and timebase frequencies, let's use them in the bamboo code as well! Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Remove mpc8544_copy_soc_cellAlexander Graf
We don't need mpc8544_copy_soc_cell anymore, since we're explicitly reading host values and writing guest values respectively. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Use generic kvm function for freqAlexander Graf
Now that we have generic KVM functions to read out the host tb and clock frequencies, let's use them in the e500 code! Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: KVM: Add generic function to read host clockfreqAlexander Graf
We need to find out the host's clock-frequency when running on KVM, so let's export a respective function. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - enable 64bit values
2011-10-06PPC: bamboo: Move host fdt copy to targetAlexander Graf
We have some code in generic kvm_ppc.c that is only used by 440. Move to the 440 specific device code. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06device tree: add nop_nodeAlexander Graf
We have a qemu internal abstraction layer on FDT. While I'm not fully convinced we need it at all, it's missing the nop_node functionality that we now need on e500. So let's add it and think about the general future of that API later. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Generate IRQ lines for many CPUsAlexander Graf
Now that we can generate multiple envs for all our virtual CPUs, we also need to tell the MPIC that we have multiple CPUs connected and connect them all to the respective virtual interrupt lines. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: create multiple envsAlexander Graf
When creating a VM, we should go through smp_cpus and create a virtual CPU for every CPU the user requested. This patch adds support for that and moves some code around to make that more convenient. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Bump MPIC up to 32 supported CPUsAlexander Graf
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in the code exporting the numbers out and fix an integer overflow while at it. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - Max cpus is 15 due to cINT routing - Report nb_cpus not MAX_CPUS in MPIC capabilities
2011-10-06PPC: MPIC: Fix CI bit definitionsAlexander Graf
The bit definitions for critical interrupt routing are in PowerPC order (most significant bit is 0), while we end up shifting it with normal bit order. Turn the numbers around so we actually end up fetching the right ones. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: MPIC: Remove read functionality for WO registersAlexander Graf
The IPI dispatch registers are write only according to every MPIC spec I have found. So instead of pretending you could read back something from them, better not handle them at all. Reported-by: Elie Richa <richa@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Set MPIC IDE for IPI to 0Alexander Graf
We use the IDE register with IPIs as a mask to keep track which processors have already acknowledged the respective interrupt. So we need to initialize it to 0 to make sure that it doesn't accidently fire an IPI on CPU0 when the first IPI is triggered. Reported-by: Elie Richa <richa@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de> --- v2 -> v3: - fix IDE IPI reset
2011-10-06PPC: Fix IPI support in MPICAlexander Graf
The current IPI support in the MPIC code is incomplete and doesn't work. This code adds proper support for IPIs in MPIC by using the IDE register to remember which CPUs IPIs are still outstanding to. New triggers through the IPI trigger register only add to the list of CPUs we want to IPI. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - Use MAX_IPI instead of hardcoded 4 Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Extend MPIC MMIO rangeAlexander Graf
The MPIC exports a page for each CPU that it controls. To support more than one CPU, we need to also reserve the MMIO space according to the amount of CPUs we want to support. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Add CPU local MMIO regions to MPICAlexander Graf
The MPIC exports a register set for each CPU connected to it. They can all be accessed through specific registers or using a shadow page that is mapped differently depending on which CPU accesses it. This patch implements the shadow map, making it possible for guests to access the CPU local registers using the same address on each CPU. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Move openpic to target specific code compilationAlexander Graf
The MPIC has some funny feature where it maps different registers to an MMIO region depending which CPU accesses them. To be able to reflect that, we need to make OpenPIC be compiled in the target code, so it can access cpu_single_env. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06spapr: make irq customizable via qdevPaolo Bonzini
This also lets the user see the irq in "info qtree". Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06spapr: prepare for qdevification of irqPaolo Bonzini
Restructure common properties for sPAPR devices so that IRQ definitions can be added in one place. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06spapr: proper qdevificationPaolo Bonzini
Right now the spapr devices cannot be instantiated with -device, because the IRQs need to be passed to the spapr_*_create functions. Do this instead in the bus's init wrapper. This is particularly important with the conversion from scsi-disk to scsi-{cd,hd} that Markus made. After his patches, if you specify a scsi-cd device attached to an if=none drive, the default VSCSI controller will not be created and, without qdevification, you will not be able to add yours. NOTE from agraf: added small compile fix Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-05qed: fix use-after-free during l2 cache commitStefan Hajnoczi
QED's metadata caching strategy allows two parallel requests to race for metadata lookup. The first one to complete will populate the metadata cache and the second one will drop the data it just read in favor of the cached data. There is a use-after-free in qed_read_l2_table_cb() and qed_commit_l2_update() where l2_table->offset was used after the l2_table may have been freed due to a metadata lookup race. Fix this by keeping the l2_offset in a local variable and not reaching into the possibly freed l2_table. Reported-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-10-03etrax-dma: Remove bogus if statementEdgar E. Iglesias
Reported-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-10-02memory: Print regions in ascending orderJan Kiszka
Makes reading the output more user friendly. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02memory: Do not print empty PIO rootJan Kiszka
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02memory: Print region priorityJan Kiszka
Useful to discover eclipses. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02memory: simple memory tree printerBlue Swirl
Add a monitor command 'info mtree' to show the memory hierarchy much like /proc/iomem in Linux. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-01Move GETPC from dyngen-exec.h to exec-all.hBlue Swirl
GETPC() can be used even from outside of helper code. Move the macro to a more accessible location. Avoid a compile warning from redefining it in exec.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl
Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01Document softmmu templatesBlue Swirl
Add some comments to describe each file. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01ESP: convert to trace frameworkBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01PPC: Drop initial ESCC mappingAlexander Graf
We are mapping ESCC to a static (incorrect) address on machine init. This overlaps with our vram, rendering the screen barely usable. Since openBIOS is clever enough to map ESCC to where it needs to be, we can just drop that invalid map and everyone's happy. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01tcg-i386: Introduce limited deposit supportJan Kiszka
x86 cannot provide an optimized generic deposit implementation. But at least for a few special cases, namely for writing bits 0..7, 8..15, and 0..15, versions using only a single instruction are feasible. Introducing such limited support improves emulating 16-bit x86 code on x86, but also rarer cases where 32-bit or 64-bit code accesses bytes or words. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01mips_fulong2e: Reorder ISA bus and i8259 creationJan Kiszka
Missed during memory region conversion: The i8259 now depends on the ISA bus being created first. Reorder the initialization. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01target-i386: Remove redundant word mask in port out instructionsJan Kiszka
T0 was already masked to 16 bits when loading it. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01softfloat: Reinstate accidentally disabled target-specific NaN handlingPeter Maydell
Include config.h in softfloat.c, so that the target specific ifdefs in softfloat-specialize.h are evaluated correctly. This was accidentally broken in commit 789ec7ce2 when config-target.h was removed from softfloat.h, and means that most targets will have been returning the wrong results for calculations involving NaNs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01tcg/arm: Remove unused tcg_out_addi()Peter Maydell
Remove the unused function tcg_out_addi() from the ARM TCG backend; this fixes a compilation failure on ARM hosts with newer gcc. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-28 03:14:14 +0000