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2016-01-25fdc: Throw an assertion on misconfigured fd_formats tableJohn Snow
pick_geometry is a convoluted function that makes it difficult to tell at a glance what QEMU's current behavior for choosing a floppy drive type is when it can't quite identify the diskette. The code iterates over all entries in the candidate geometry table ("fd_formats") and if our specific drive type matches a row in the table, then either "match" is set to that entry (an exact match) and the loop exits, or "first_match" will be non-negative (the first such entry that shares the same drive type), and the loop continues. If our specific drive type is NONE, then all drive types in the candidate geometry table are considered. After iteration, if "match" was not set, we fall back to "first match". This means that either "match" was set, or we exited the loop without an exact match, in which case: - If drive type is NONE, the default is truly fd_formats[0], a 1.44MB type, because "first_match" will always get set to the first item. - If drive type is not NONE, pick_geometry's iteration was fussier and only looked at rows that matched our drive type. However, since all possible drive types are represented in the table, we still know that "first match" was set. - If drive type is not NONE and the fd_formats table lists no options for our drive type, we choose fd_formats[1], an incomprehensibly bizarre choice that can never happen anyway. Correct this: If first_match is -1, it can ONLY mean we didn't edit our fd_formats table correctly. Throw an assertion instead. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: John Snow <jsnow@redhat.com> Message-id: 1453495865-9649-6-git-send-email-jsnow@redhat.com
2016-01-25fdc: add disk fieldJohn Snow
Currently, 'drive' is used both to represent the current diskette type as well as the current drive type. This patch adds a 'disk' field that is updated explicitly to match the type of the disk. As of this patch, disk and drive are always the same, but forthcoming patches to change the behavior of pick_geometry will invalidate this assumption. disk does not need to be migrated because it is not user-visible state nor is it currently used for any calculations. It is purely informative, and will be rebuilt automatically via fd_revalidate on the new host. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: John Snow <jsnow@redhat.com> Message-id: 1453495865-9649-5-git-send-email-jsnow@redhat.com
2016-01-25fdc: add drive type qapi enumJohn Snow
Change the floppy drive type to a QAPI enum type, to allow us to specify the floppy drive type from the CLI in a forthcoming patch. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: John Snow <jsnow@redhat.com> Message-id: 1453495865-9649-4-git-send-email-jsnow@redhat.com
2016-01-25fdc: reduce number of pick_geometry argumentsJohn Snow
Modify this function to operate directly on FDrive objects instead of unpacking and passing all of those parameters manually. Reduces the complexity in the caller and reduces the number of args to just one. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: John Snow <jsnow@redhat.com> Message-id: 1453495865-9649-3-git-send-email-jsnow@redhat.com
2016-01-25fdc: move pick_geometryJohn Snow
Code motion: I want to refactor this function to work with FDrive directly, so shuffle it below that definition. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: John Snow <jsnow@redhat.com> Message-id: 1453495865-9649-2-git-send-email-jsnow@redhat.com
2016-01-25ide: Correct the CHS 'cyls_max' limit to be 65535Shmulik Ladkani
In b7eb0c9: hw/block-common: Factor out fall back to legacy -drive cyls=... 'blkconf_geometry()' was introduced, factoring out CHS limit validation code that was repeated in ide, scsi, virtio-blk. The original IDE CHS limit prior b7eb0c9 was 65535,16,255 (as per ATA CHS addressing). However the 'cyls_max' argument passed to 'blkconf_geometry' in the ide_dev_initfn case was accidentally set to 65536 instead of 65535. Fix, providing the correct 'cyls_max'. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 1453112371-29760-1-git-send-email-shmulik.ladkani@ravellosystems.com Signed-off-by: John Snow <jsnow@redhat.com>
2016-01-25Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160125' into stagingPeter Maydell
MIPS patches 2016-01-25 Changes: * fixes and includes clean-up # gpg: Signature made Mon 25 Jan 2016 09:29:51 GMT using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" * remotes/lalrae/tags/mips-20160125: mips: Clean up includes target-mips: Fix ALIGN instruction when bp=0 target-mips: silence NaNs for cvt.s.d and cvt.d.s target-mips/cpu.h: Fix spell error Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-23mips: Clean up includesPeter Maydell
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-01-23target-mips: Fix ALIGN instruction when bp=0Miodrag Dinic
If executing ALIGN with shift count bp=0 within mips64 emulation, the result of the operation should be sign extended. Taken from the official documentation (pseudo code) : ALIGN: tmp_rt_hi = unsigned_word(GPR[rt]) << (8*bp) tmp_rs_lo = unsigned_word(GPR[rs]) >> (8*(4-bp)) tmp = tmp_rt_hi || tmp_rt_lo GPR[rd] = sign_extend.32(tmp) Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-01-23target-mips: silence NaNs for cvt.s.d and cvt.d.sAurelien Jarno
cvt.s.d and cvt.d.s are FP operations and thus need to convert input sNaN into corresponding qNaN. Explicitely use the floatXX_maybe_silence_nan functions for that as the floatXX_to_floatXX functions do not do that. Cc: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-01-23target-mips/cpu.h: Fix spell errorDongxue Zhang
CP0IntCtl_IPPC1, the last letter should be 'i', not 'one'. Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-01-22Merge remote-tracking branch 'remotes/pmaydell/tags/pull-softfloat-20160122' ↵Peter Maydell
into staging softfloat: * drop confusing softfloat-only types * fix return type of roundAndPackFloat16 # gpg: Signature made Fri 22 Jan 2016 15:15:17 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-softfloat-20160122: softfloat: fix return type of roundAndPackFloat16 fpu: Replace uint8 typedef with uint8_t fpu: Replace int8 typedef with int8_t fpu: Replace uint32 typedef with uint32_t fpu: Replace int32 typedef with int32_t fpu: Replace uint64 typedef with uint64_t fpu: Replace int64 typedef with int64_t Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-22softfloat: fix return type of roundAndPackFloat16Aurelien Jarno
The roundAndPackFloat16 function should return a float16 value, not a float32 one. Fix that. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1452700993-6570-1-git-send-email-aurelien@aurel32.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-22fpu: Replace uint8 typedef with uint8_tPeter Maydell
Replace the uint8 softfloat-specific typedef with uint8_t. This change was made with find include hw fpu target-* -name '*.[ch]' | xargs sed -i -e 's/\buint8\b/uint8_t/g' together with manual removal of the typedef definition and manual fixing of more erroneous uses found via test compilation. It turns out that the only code using this type is an accidental use where uint8_t was intended anyway... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Leon Alrae <leon.alrae@imgtec.com> Acked-by: James Hogan <james.hogan@imgtec.com> Message-id: 1452603315-27030-7-git-send-email-peter.maydell@linaro.org
2016-01-22fpu: Replace int8 typedef with int8_tPeter Maydell
Replace the int8 softfloat-specific typedef with int8_t. This change was made with find include hw fpu target-* -name '*.[ch]' | xargs sed -i -e 's/\bint8\b/int8_t/g' together with manual removal of the typedef definition, and manual undoing of various mis-hits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Leon Alrae <leon.alrae@imgtec.com> Acked-by: James Hogan <james.hogan@imgtec.com> Message-id: 1452603315-27030-6-git-send-email-peter.maydell@linaro.org
2016-01-22fpu: Replace uint32 typedef with uint32_tPeter Maydell
Replace the uint32 softfloat-specific typedef with uint32_t. This change was made with find include hw fpu target-* -name '*.[ch]' | xargs sed -i -e 's/\buint32\b/uint32_t/g' together with manual removal of the typedef definition, manual undoing of various mis-hits, and another couple of fixes found via test compilation. All the uses in hw/ were using the wrong type by mistake. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Leon Alrae <leon.alrae@imgtec.com> Acked-by: James Hogan <james.hogan@imgtec.com> Message-id: 1452603315-27030-5-git-send-email-peter.maydell@linaro.org
2016-01-22fpu: Replace int32 typedef with int32_tPeter Maydell
Replace the int32 softfloat-specific typedef with int32_t. This change was made with find hw include fpu target-* -name '*.[ch]' | xargs sed -i -e 's/\bint32\b/int32_t/g' together with manual removal of the typedef definition, and manual undoing of some mis-hits where macro arguments were being used for token pasting rather than as a type. The uses in hw/ipmi/ should not have been using this type at all. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Leon Alrae <leon.alrae@imgtec.com> Acked-by: James Hogan <james.hogan@imgtec.com> Message-id: 1452603315-27030-4-git-send-email-peter.maydell@linaro.org
2016-01-22fpu: Replace uint64 typedef with uint64_tPeter Maydell
Replace the uint64 softfloat-specific typedef with uint64_t. This change was made with find include fpu target-* -name '*.[ch]' | xargs sed -i -e 's/\buint64\b/uint64_t/g' together with manual removal of the typedef definition, and manual undoing of some mis-hits where macro arguments were being used for token pasting rather than as a type. Note that the target-mips/kvm.c and target-s390x/kvm.c changes are fixing code that should not have been using the uint64 type in the first place. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Leon Alrae <leon.alrae@imgtec.com> Acked-by: James Hogan <james.hogan@imgtec.com> Message-id: 1452603315-27030-3-git-send-email-peter.maydell@linaro.org
2016-01-22fpu: Replace int64 typedef with int64_tPeter Maydell
Replace the int64 softfloat-specific typedef with int64_t. This change was made with find include fpu target-* -name '*.[ch]' | xargs sed -i -e 's/\bint64\b/int64_t/g' together with manual removal of the typedef definition, and manual undoing of some mis-hits where macro arguments were being used for token pasting rather than as a type. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Leon Alrae <leon.alrae@imgtec.com> Message-id: 1452603315-27030-2-git-send-email-peter.maydell@linaro.org
2016-01-22Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into stagingPeter Maydell
fprintf to error_report conversion in hw/9pfs and fsdev # gpg: Signature made Fri 22 Jan 2016 14:23:15 GMT using DSA key ID 0101DBC2 # gpg: Good signature from "Greg Kurz <gkurz@fr.ibm.com>" # gpg: aka "Greg Kurz <groug@free.fr>" # gpg: aka "Greg Kurz <gkurz@linux.vnet.ibm.com>" # gpg: aka "Gregory Kurz (Groug) <groug@free.fr>" # gpg: aka "Gregory Kurz (Cimai Technology) <gkurz@cimai.com>" # gpg: aka "Gregory Kurz (Meiosys Technology) <gkurz@meiosys.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2BD4 3B44 535E C0A7 9894 DBA2 02FC 3AEB 0101 DBC2 * remotes/gkurz/tags/for-upstream: fsdev: use error_report() instead of fprintf(stderr) 9pfs: use error_report() instead of fprintf(stderr) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-22fsdev: use error_report() instead of fprintf(stderr)Greg Kurz
Only fix the code that gets built into QEMU. Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
2016-01-229pfs: use error_report() instead of fprintf(stderr)Greg Kurz
Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
2016-01-22seabios: fix submoduleGerd Hoffmann
Commit "36f96c4 target-i386: Add support to migrate vcpu's TSC rate" updates roms/seabios, appearently by mistake. Revert this. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 1453460391-7664-1-git-send-email-kraxel@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21Merge remote-tracking branch 'remotes/sstabellini/tags/xen-20160121' into ↵Peter Maydell
staging Xen 2016/01/21 # gpg: Signature made Thu 21 Jan 2016 16:58:50 GMT using RSA key ID 70E1AE90 # gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" * remotes/sstabellini/tags/xen-20160121: Xen PCI passthru: convert to realize() Add Error **errp for xen_pt_config_init() Add Error **errp for xen_pt_setup_vga() Add Error **errp for xen_host_pci_device_get() Xen: use qemu_strtoul instead of strtol Change xen_host_pci_sysfs_path() to return void xen-pvdevice: convert to realize() xen-hvm: Clean up xen_ram_alloc() error handling xen-hvm: Clean up xen_hvm_init() error handling xenfb.c: avoid expensive loops when prod <= out_cons MAINTAINERS: update Xen files Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21Xen PCI passthru: convert to realize()Cao jin
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2016-01-21Add Error **errp for xen_pt_config_init()Cao jin
To catch the error message. Also modify the caller Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2016-01-21Add Error **errp for xen_pt_setup_vga()Cao jin
To catch the error message. Also modify the caller Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2016-01-21Add Error **errp for xen_host_pci_device_get()Cao jin
To catch the error message. Also modify the caller Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-01-21Xen: use qemu_strtoul instead of strtolCao jin
No need to roll our own (with slightly incorrect handling of errno), when we can use the common version. Change signed parsing to unsigned, because what it read are values in PCI config space, which are non-negative. Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-01-21Change xen_host_pci_sysfs_path() to return voidCao jin
And assert the snprintf() error, because user can do nothing in case of snprintf() fail. Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-01-21Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell
staging X86 queue, 2016-01-21 # gpg: Signature made Thu 21 Jan 2016 15:08:40 GMT using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" * remotes/ehabkost/tags/x86-pull-request: target-i386: Add PKU and and OSPKE support target-i386: Add support to migrate vcpu's TSC rate target-i386: Reorganize TSC rate setting code target-i386: Fallback vcpu's TSC rate to value returned by KVM target-i386: Add suffixes to MMReg struct fields target-i386: Define MMREG_UNION macro target-i386: Define MMXReg._d field target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_* target-i386: Rename struct XMMReg to ZMMReg target-i386: Use a _q array on MMXReg too target-i386/ops_sse.h: Use MMX_Q macro target-i386: Rename optimize_flags_init() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21xen-pvdevice: convert to realize()Cao jin
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2016-01-21Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20160121' into staging target-arm queue: * connect SPI devices in Xilinx Zynq platforms * multiple-address-space support * use multiple-address-space support for ARM TrustZone * arm_gic: return correct ID registers for 11MPCore/v1/v2 GICs * various fixes for (currently disabled) AArch64 EL2 and EL3 support * add 'always-on' property to the virt board timer DT entry # gpg: Signature made Thu 21 Jan 2016 14:54:56 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20160121: (36 commits) target-arm: Implement FPEXC32_EL2 system register target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode target-arm: Implement remaining illegal return event checks target-arm: Handle exception return from AArch64 to non-EL0 AArch32 target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target target-arm: Pull semihosting handling out to arm_cpu_do_interrupt() target-arm: Use a single entry point for AArch64 and AArch32 exceptions target-arm: Move aarch64_cpu_do_interrupt() to helper.c target-arm: Properly support EL2 and EL3 in arm_el_is_aa64() arm_gic: Update ID registers based on revision hw/arm/virt: Add always-on property to the virt board timer hw/arm/virt: add secure memory region and UART hw/arm/virt: Wire up memory region to CPUs explicitly target-arm: Support multiple address spaces in page table walks target-arm: Implement cpu_get_phys_page_attrs_debug target-arm: Implement asidx_from_attrs target-arm: Add QOM property for Secure memory region qom/cpu: Add MemoryRegion property memory: Add address_space_init_shareable() exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21target-i386: Add PKU and and OSPKE supportHuaitong Han
Add PKU and OSPKE CPUID features, including xsave state and migration support. Signed-off-by: Huaitong Han <huaitong.han@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: squashed 3 patches together, edited patch description] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Add support to migrate vcpu's TSC rateHaozhong Zhang
This patch enables migrating vcpu's TSC rate. If KVM on the destination machine supports TSC scaling, guest programs will observe a consistent TSC rate across the migration. If TSC scaling is not supported on the destination machine, the migration will not be aborted and QEMU on the destination will not set vcpu's TSC rate to the migrated value. If vcpu's TSC rate specified by CPU option 'tsc-freq' on the destination machine is inconsistent with the migrated TSC rate, the migration will be aborted. For backwards compatibility, the migration of vcpu's TSC rate is disabled on pc-*-2.5 and older machine types. Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: Rewrote comment at kvm_arch_put_registers()] [ehabkost: Moved compat code to pc-2.5] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Reorganize TSC rate setting codeHaozhong Zhang
Following changes are made to the TSC rate setting code in kvm_arch_init_vcpu(): * The code is moved to a new function kvm_arch_set_tsc_khz(). * If kvm_arch_set_tsc_khz() fails, i.e. following two conditions are both satisfied: * KVM does not support the TSC scaling or it fails to set vcpu's TSC rate by KVM_SET_TSC_KHZ, * the TSC rate to be set is different than the value currently used by KVM, then kvm_arch_init_vcpu() will fail. Prevously, * the lack of TSC scaling never failed kvm_arch_init_vcpu(), * the failure of KVM_SET_TSC_KHZ failed kvm_arch_init_vcpu() unconditionally, even though the TSC rate to be set is identical to the value currently used by KVM. Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Fallback vcpu's TSC rate to value returned by KVMHaozhong Zhang
If no user-specified TSC rate is present, we will try to set env->tsc_khz to the value returned by KVM_GET_TSC_KHZ. This patch does not change the current functionality of QEMU and just prepares for later patches to enable migrating vcpu's TSC rate. Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Add suffixes to MMReg struct fieldsEduardo Habkost
This will ensure we never use the MMX_* and ZMM_* macros with the wrong struct type. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Define MMREG_UNION macroEduardo Habkost
This will simplify the definitions of ZMMReg and MMXReg. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Define MMXReg._d fieldEduardo Habkost
Add a new field and reorder MMXReg fields, to make MMXReg and ZMMReg field lists look the same (except for the array sizes). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_*Eduardo Habkost
They are helpers for the ZMMReg fields, so name them accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Rename struct XMMReg to ZMMRegEduardo Habkost
The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Use a _q array on MMXReg tooEduardo Habkost
Make MMXReg use the same field names used on XMMReg, so we can try to reuse macros and other code later. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386/ops_sse.h: Use MMX_Q macroEduardo Habkost
We have a MMX_Q macro in addition to MMX_{B,W,L}. Use it. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Rename optimize_flags_init()Eduardo Habkost
Rename the function so that the reason for its existence is clearer: it does x86-specific initialization of TCG structures. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-arm: Implement FPEXC32_EL2 system registerPeter Maydell
The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, and allows those exception levels to read and write the FPEXC register for a lower exception level that is using AArch32. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1453132414-8127-1-git-send-email-peter.maydell@linaro.org
2016-01-21target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM modePeter Maydell
The architecture requires that for an exception return to AArch32 the low bits of ELR_ELx are ignored when the PC is set from them: * if returning to Thumb mode, ignore ELR_ELx[0] * if returning to ARM mode, ignore ELR_ELx[1:0] We were only squashing bit 0; also squash bit 1 if the SPSR T bit indicates this is a return to ARM code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Implement remaining illegal return event checksPeter Maydell
We already implement almost all the checks for the illegal return events from AArch64 state described in the ARM ARM section D1.11.2. Add the two missing ones: * return to EL2 when EL3 is implemented and SCR_EL3.NS is 0 * return to Non-secure EL1 when EL2 is implemented and HCR_EL2.TGE is 1 (We don't implement external debug, so the case of "debug state exit from EL0 using AArch64 state to EL0 using AArch32 state" doesn't apply for QEMU.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Handle exception return from AArch64 to non-EL0 AArch32Peter Maydell
Remove the assumptions that the AArch64 exception return code was making about a return to AArch32 always being a return to EL0. This includes pulling out the illegal-SPSR checks so we can apply them for return to 32 bit as well as return to 64-bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Fix wrong AArch64 entry offset for EL2/EL3 targetPeter Maydell
The entry offset when taking an exception to AArch64 from a lower exception level may be 0x400 or 0x600. 0x400 is used if the implemented exception level immediately lower than the target level is using AArch64, and 0x600 if it is using AArch32. We were incorrectly implementing this as checking the exception level that the exception was taken from. (The two can be different if for example we take an exception from EL0 to AArch64 EL3; we should in this case be checking EL2 if EL2 is implemented, and EL1 if EL2 is not implemented.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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