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2022-04-22hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()Bin Meng
2022-04-22target/riscv: cpu: Enable native debug featureBin Meng
2022-04-22target/riscv: machine: Add debug state descriptionBin Meng
2022-04-22target/riscv: csr: Hook debug CSR read/writeBin Meng
2022-04-22target/riscv: cpu: Add a config option for native debugBin Meng
2022-04-22target/riscv: debug: Implement debug related TCGCPUOpsBin Meng
2022-04-22hw/intc: riscv_aclint: Add reset function of ACLINT devicesJim Shu
2022-04-22hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang
2022-04-22hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINTFrank Chang
2022-04-22hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINTFrank Chang
2022-04-22hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabledNiklas Cassel
2022-04-22target/riscv/pmp: fix NAPOT range computation overflowNicolas Pitre
2022-04-22hw/riscv: virt: Exit if the user provided -bios in combination with KVMRalf Ramsauer
2022-04-22target/riscv: Use cpu_loop_exit_restore directly from mmu faultsRichard Henderson
2022-04-22target/riscv: fix start byte for vmv<nf>r.v when vstart != 0Weiwei Li
2022-04-22target/riscv: Add isa extenstion strings to the device treeAtish Patra
2022-04-22target/riscv: misa to ISA string conversion fixTsukasa OI
2022-04-22target/riscv: optimize helper for vmv<nr>r.vWeiwei Li
2022-04-22target/riscv: optimize condition assign for scale < 0Weiwei Li
2022-04-22target/riscv: Add initial support for the Sdtrig extensionBin Meng
2022-04-22target/riscv: Allow software access to MIP SEIPAlistair Francis
2022-04-22target/riscv: cpu: Fixup indentationAlistair Francis
2022-04-22target/riscv: Enable privileged spec version 1.12Atish Patra
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra
2022-04-22target/riscv: Add support for mconfigptrAtish Patra
2022-04-22target/riscv: Introduce privilege version field in the CSR ops.Atish Patra
2022-04-22target/riscv: Add the privileged spec version 1.12.0Atish Patra
2022-04-22target/riscv: Define simpler privileged spec version numberingAtish Patra
2022-04-22riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa
2022-04-22hw/ssi: Add Ibex SPI device modelWilfred Mallawa
2022-04-21Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into stagingRichard Henderson
2022-04-21Merge tag 'pull-qapi-2022-04-21' of git://repo.or.cz/qemu/armbru into stagingRichard Henderson
2022-04-21Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into stagingRichard Henderson
2022-04-21Merge tag 'pull-target-arm-20220421' of https://git.linaro.org/people/pmaydel...Richard Henderson
2022-04-21python/qmp: remove pylint workaround from legacy.pyJohn Snow
2022-04-21python: rename 'aqmp-tui' to 'qmp-tui'John Snow
2022-04-21python: rename qemu.aqmp to qemu.qmpJohn Snow
2022-04-21python: re-enable pylint duplicate-code warningsJohn Snow
2022-04-21python: remove the old QMP packageJohn Snow
2022-04-21python/aqmp: copy qmp docstrings to qemu.aqmp.legacyJohn Snow
2022-04-21python/aqmp: fully separate from qmp.QEMUMonitorProtocolJohn Snow
2022-04-21python/aqmp: take QMPBadPortError and parse_address from qemu.qmpJohn Snow
2022-04-21python: temporarily silence pylint duplicate-code warningsJohn Snow
2022-04-21python/aqmp-tui: relicense as LGPLv2+John Snow
2022-04-21python/qmp-shell: relicense as LGPLv2+John Snow
2022-04-21python/aqmp: relicense as LGPLv2+John Snow
2022-04-21python/aqmp: add explicit GPLv2 license to legacy.pyJohn Snow
2022-04-21iotests: switch to AQMPJohn Snow
2022-04-21iotests/mirror-top-perms: switch to AQMPJohn Snow
2022-04-21scripts/bench-block-job: switch to AQMPJohn Snow