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AgeCommit message (Expand)Author
2023-07-10target/riscv/kvm.c: update KVM MISA bitsDaniel Henrique Barboza
2023-07-10target/riscv: add KVM specific MISA propertiesDaniel Henrique Barboza
2023-07-10target/riscv/cpu: add misa_ext_info_arr[]Daniel Henrique Barboza
2023-07-10target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPUDaniel Henrique Barboza
2023-07-10target/riscv: handle mvendorid/marchid/mimpid for KVM CPUsDaniel Henrique Barboza
2023-07-10target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids()Daniel Henrique Barboza
2023-07-10target/riscv: use KVM scratch CPUs to init KVM propertiesDaniel Henrique Barboza
2023-07-10target/riscv/cpu.c: restrict 'marchid' valueDaniel Henrique Barboza
2023-07-10target/riscv/cpu.c: restrict 'mimpid' valueDaniel Henrique Barboza
2023-07-10target/riscv/cpu.c: restrict 'mvendorid' valueDaniel Henrique Barboza
2023-07-10hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not setDaniel Henrique Barboza
2023-07-10target/riscv: skip features setup for KVM CPUsDaniel Henrique Barboza
2023-07-10hw/riscv: virt: Convert fdt_load_addr to uint64_tLakshmi Bai Raja Subramanian
2023-07-10riscv: Generate devicetree only after machine initialization is completeGuenter Roeck
2023-07-10target/riscv KVM_RISCV_SET_TIMER macro is not configured correctlyyang.zhang
2023-07-10target/riscv: Add disas support for BF16 extensionsWeiwei Li
2023-07-10target/riscv: Set the correct exception for implict G-stage translation failJason Chien
2023-07-10target/riscv: Expose properties for BF16 extensionsWeiwei Li
2023-07-10target/riscv: Add support for Zvfbfwma extensionWeiwei Li
2023-07-10target/riscv: Add support for Zvfbfmin extensionWeiwei Li
2023-07-10target/riscv: Add support for Zfbfmin extensionWeiwei Li
2023-07-10target/riscv: Add properties for BF16 extensionsWeiwei Li
2023-07-10linux-user/riscv: Add syscall riscv_hwprobeRobbin Ehn
2023-07-10hw/riscv/virt: Restrict ACLINT to TCGPhilippe Mathieu-Daudé
2023-07-10target/riscv: Add RVV registers to logIvan Klokov
2023-07-10target/riscv: Only build KVM guest with same wordsize as hostPhilippe Mathieu-Daudé
2023-07-10target/riscv: Only unify 'riscv32/64' -> 'riscv' for host cpu in mesonPhilippe Mathieu-Daudé
2023-07-10tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_eTommy Wu
2023-07-10hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.Tommy Wu
2023-07-10hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.Tommy Wu
2023-07-10tests/avocado: riscv: Enable 32-bit Spike OpenSBI boot testingBin Meng
2023-07-10roms/opensbi: Upgrade from v1.2 to v1.3Bin Meng
2023-07-10target/riscv: update cur_pmbase/pmmask based on mode affected by MPRVWeiwei Li
2023-07-10target/riscv: Add additional xlen for address when MPRV=1Weiwei Li
2023-07-10target/riscv/cpu.c: fix veyron-v1 CPU propertiesDaniel Henrique Barboza
2023-07-10target/riscv: Remove redundant assignment to SXLWeiwei Li
2023-07-10target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabledWeiwei Li
2023-07-10target/riscv: Make MPV only work when MPP != PRV_MWeiwei Li
2023-07-10disas/riscv: Add support for XThead* instructionsChristoph Müllner
2023-07-10disas/riscv: Add support for XVentanaCondOpsChristoph Müllner
2023-07-10disas/riscv: Provide infrastructure for vendor extensionsChristoph Müllner
2023-07-10disas/riscv: Encapsulate opcode_data into decodeChristoph Müllner
2023-07-10disas/riscv: Make rv_op_illegal a shared enum valueChristoph Müllner
2023-07-10disas/riscv: Move types/constants to new header fileChristoph Müllner
2023-07-10target/riscv: Factor out extension tests to cpu_cfg.hChristoph Müllner
2023-07-10target/riscv: Use xl instead of mxl for disassembleLIU Zhiwei
2023-07-10Merge tag 'pull-vfio-20230710' of https://github.com/legoater/qemu into stagingRichard Henderson
2023-07-10vfio/pci: Enable AtomicOps completers on root portsAlex Williamson
2023-07-10pcie: Add a PCIe capability version helperAlex Williamson
2023-07-10s390x/ap: Wire up the device request notifier interfaceTony Krowiak
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