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2020-08-12spapr: Clarify error and documentation for broken KVM XICSGreg Kurz
When starting an L2 KVM guest with `ic-mode=dual,kernel-irqchip=on`, QEMU fails with: KVM is too old to support ic-mode=dual,kernel-irqchip=on This error message was introduced to detect older KVM versions that didn't allow destruction and re-creation of the XICS KVM device that we do at reboot. But it is actually the same issue that we get with nested guests : when running under pseries, KVM currently provides a genuine XICS device (not the XICS-on-XIVE device that we get under powernv) which doesn't support destruction/re-creation. This will eventually be fixed in KVM but in the meantime, update the error message and documentation to mention the nested case. While here, mention that in "No XIVE support in KVM" section that this can also happen with "guest OSes supporting XIVE" since we check this at init time before starting the guest. Reported-by: Satheesh Rajendran <sathnaga@linux.vnet.ibm.com> Buglink: https://bugs.launchpad.net/qemu/+bug/1890290 Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <159664243614.622889.18307368735989783528.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12docs: Update POWER9 XIVE support for nested guestsCédric Le Goater
It is not yet supported. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200804131639.407049-1-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12docs: adding NUMA documentation for pseriesDaniel Henrique Barboza
This patch adds a new documentation file, ppc-spapr-numa.rst, informing what developers and user can expect of the NUMA distance support for the pseries machine, up to QEMU 5.1. In the (hopefully soon) future, when we rework the NUMA mechanics of the pseries machine to at least attempt to contemplate user choice, this doc will be extended to inform about the new support. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200803133440.825276-1-danielhb413@gmail.com> Tested-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: Fix SPE unavailable exception triggeringMatthieu Bucchianeri
When emulating certain floating point instructions or vector instructions on PowerPC machines, QEMU did not properly generate the SPE/Embedded Floating- Point Unavailable interrupt. See the buglink further below for references to the relevant NXP documentation. This patch fixes the behavior of some evfs* instructions that were incorrectly emitting the interrupt. More importantly, this patch fixes the behavior of several efd* and ev* instructions that were not generating the interrupt. Triggering the interrupt for these instructions fixes lazy FPU/vector context switching on some operating systems like Linux. Without this patch, the result of some double-precision arithmetic could be corrupted due to the lack of proper saving and restoring of the upper 32-bit part of the general-purpose registers. Buglink: https://bugs.launchpad.net/qemu/+bug/1888918 Buglink: https://bugs.launchpad.net/qemu/+bug/1611394 Signed-off-by: Matthieu Bucchianeri <matthieu.bucchianeri@leostella.com> Message-Id: <20200727175553.32276-1-matthieu.bucchianeri@leostella.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: add vmulh{su}d instructionsLijun Pan
vmulhsd: Vector Multiply High Signed Doubleword vmulhud: Vector Multiply High Unsigned Doubleword Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200724045845.89976-5-ljp@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: add vmulh{su}w instructionsLijun Pan
vmulhsw: Vector Multiply High Signed Word vmulhuw: Vector Multiply High Unsigned Word Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200724045845.89976-4-ljp@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: add vmulld to INDEX_op_mul_vec caseLijun Pan
Group vmuluwm and vmulld. Make vmulld-specific changes since it belongs to new ISA 3.1. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200724045845.89976-3-ljp@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12Update PowerPC AT_HWCAP2 definitionLijun Pan
Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200724045845.89976-2-ljp@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-08-12ppc/xive: Fix some typos in commentsGustavo Romero
Fix some typos in comments about code modeling coalescing points in the XIVE routing engine (IVRE). Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> Message-Id: <1595461434-27725-1-git-send-email-gromero@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12spapr: Forbid nested KVM-HV in pre-power9 compat modeGreg Kurz
Nested KVM HV only works if the kernel is using the radix MMU mode, ie. the CPU is POWER9 and it is not running in some pre-power9 compat mode. Otherwise, the KVM HV module fails to load in the guest with -ENODEV. It might be painful for a user to discover this late that nested cannot work with their setup. Erroring out at machine init instead seems to be the best we can do. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <159491948127.188975.9621435875869177751.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12spapr: Use error_append_hint() in spapr_caps.cGreg Kurz
We have a dedicated error API for hints. Use it instead of embedding the hint in the error message, as recommanded in the "qapi/error.h" header file. While here, have cap_fwnmi_apply(), which already uses error_append_hint(), to call ERRP_GUARD() as well. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <159594297421.8262.14314530897345809924.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12ppc/spapr: Fix 32 bit logical memory block size assumptionsAnton Blanchard
When testing large LMB sizes (eg 4GB), I found a couple of places that assume they are 32bit in size. Signed-off-by: Anton Blanchard <anton@ozlabs.org> Message-Id: <20200715004228.1262681-1-anton@ozlabs.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: add vmulld instructionLijun Pan
vmulld: Vector Multiply Low Doubleword. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200701234344.91843-6-ljp@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: convert vmuluwm to tcg_gen_gvec_mulLijun Pan
Convert the original implementation of vmuluwm to the more generic tcg_gen_gvec_mul. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200701234344.91843-5-ljp@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: add byte-reverse br[dwh] instructionsLijun Pan
POWER ISA 3.1 introduces following byte-reverse instructions: brd: Byte-Reverse Doubleword X-form brw: Byte-Reverse Word X-form brh: Byte-Reverse Halfword X-form Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200701234344.91843-4-ljp@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: Enable Power ISA 3.1Lijun Pan
This patch enables the Power ISA 3.1 in QEMU. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200701234344.91843-3-ljp@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: Introduce Power ISA 3.1 flagLijun Pan
This flag will be used for Power10 instructions. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200701234344.91843-2-ljp@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: Fix TCG leak with the evmwsmiaa instructionMatthieu Bucchianeri
Fix double-call to tcg_temp_new_i64(), where a temp is allocated both at declaration time and further down the implementation of gen_evmwsmiaa(). Note that gen_evmwsmia() and gen_evmwsmiaa() are still not implemented correctly, as they invoke gen_evmwsmi() which may return early, but the return is not propagated. This will be fixed in my patch for bug #1888918. Signed-off-by: Matthieu Bucchianeri <matthieu.bucchianeri@leostella.com> Message-Id: <20200727172114.31415-1-matthieu.bucchianeri@leostella.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-11Update version for v5.1.0 releasev5.1.0Peter Maydell
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-05Update version for v5.1.0-rc3 releasev5.1.0-rc3Peter Maydell
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-05target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64Peter Maydell
When a coprocessor instruction in an AArch32 guest traps to AArch32 Hyp mode, the syndrome register (HSR) includes Rt and Rt2 fields which are simply copies of the Rt and Rt2 fields from the trapped instruction. However, if the instruction is trapped from AArch32 to an AArch64 higher exception level, the Rt and Rt2 fields in the syndrome register (ESR_ELx) must be the AArch64 view of the register. This makes a difference if the AArch32 guest was in a mode other than User or System and it was using r13 or r14, or if it was in FIQ mode and using r8-r14. We don't know at translate time which AArch32 CPU mode we are in, so we leave the values we generate in our prototype syndrome register value at translate time as the raw Rt/Rt2 from the instruction, and instead correct them to the AArch64 view when we find we need to take an exception from AArch32 to AArch64 with one of these syndrome values. Fixes: https://bugs.launchpad.net/qemu/+bug/1879587 Reported-by: Julien Freche <julien@bedrocksystems.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200804193903.31240-1-peter.maydell@linaro.org
2020-08-05qcow2-cluster: Fix integer left shift error in qcow2_alloc_cluster_link_l2()Tuguoyi
When calculating the offset, the result of left shift operation will be promoted to type int64 automatically because the left operand of + operator is uint64_t. but the result after integer promotion may be produce an error value for us and trigger the following asserting error. For example, consider i=0x2000, cluster_bits=18, the result of left shift operation will be 0x80000000. Cause argument i is of signed integer type, the result is automatically promoted to 0xffffffff80000000 which is not we expected The way to trigger the assertion error: qemu-img create -f qcow2 -o preallocation=full,cluster_size=256k tmpdisk 10G This patch fix it by casting @i to uint64_t before doing left shift operation Signed-off-by: Guoyi Tu <tu.guoyi@h3c.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Message-id: 81ba90fe0c014f269621c283269b42ad@h3c.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-05Merge remote-tracking branch ↵Peter Maydell
'remotes/huth-gitlab/tags/pull-request-2020-08-05' into staging * Test rx-softmmu, avr-softmmu, Centos7 and Debian on gitlab-CI * Fix compiler warning on 32-bit big endian systems * Remove remainders of libqemustub.a # gpg: Signature made Wed 05 Aug 2020 10:51:32 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth-gitlab/tags/pull-request-2020-08-05: Get rid of the libqemustub.a remainders target/riscv/vector_helper: Fix build on 32-bit big endian hosts gitlab-ci: Fix Avocado cache usage gitlab-ci.yml: Add build-system-debian and build-system-centos jobs tests/acceptance: Disable the rx sash and arm cubieboard replay test on Gitlab tests/docker: Add python3-venv and netcat to the debian-amd64 container Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-05Get rid of the libqemustub.a remaindersThomas Huth
libqemustub.a has been removed in commit ebedb37c8d ("Makefile: Remove libqemustub.a"). Some remainders have been missed. Remove them now. Message-Id: <20200804170055.2851-8-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-08-05target/riscv/vector_helper: Fix build on 32-bit big endian hostsThomas Huth
The code currently fails to compile on 32-bit big endian hosts: target/riscv/vector_helper.c: In function 'vext_clear': target/riscv/vector_helper.c:154:16: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1); ^ target/riscv/vector_helper.c:155:16: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2); ^ cc1: all warnings being treated as errors We should not use "long long" (i.e. 64-bit) values here to avoid the problem. Switch to our QEMU_ALIGN_PTR_DOWN/UP macros instead. Fixes: 751538d5da ("add vector stride load and store instructions") Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200804170055.2851-3-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-08-05gitlab-ci: Fix Avocado cache usageThomas Huth
In commit 6957fd98dc ("gitlab: add avocado asset caching") we tried to save the Avocado cache (as in commit c1073e44b4 with Travis-CI) however it doesn't work as expected. For some reason Avocado uses /root/avocado_cache/ which we can not select later. Manually generate a Avocado config to force the use of the current job's directory. This patch is based on an earlier version from Philippe Mathieu-Daudé. Message-Id: <20200730141326.8260-5-thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-08-05gitlab-ci.yml: Add build-system-debian and build-system-centos jobsThomas Huth
We were missing the two new targets avr-softmmu and rx-softmmu in the gitlab-CI so far, and did not add some of the "other endianess" targets like sh4eb-softmmu yet. Since the current build-system-* jobs run already for a very long time, let's do not add these missing targets there, but introduce two new additional build jobs, one running with Debian and one running with CentOS, and add the new targets there. Also move some targets from the old build-system-* jobs to these new targets, to distribute the load and reduce the runtime of the CI. Message-Id: <20200730141326.8260-4-thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-08-05tests/acceptance: Disable the rx sash and arm cubieboard replay test on GitlabThomas Huth
These tests always time out on Gitlab, not sure what's happening here. Let's disable them until somebody has enough spare time to debug the issues. Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Reviewed-by: Cleber Rosa <crosa@redhat.com> Message-Id: <20200730141326.8260-3-thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-08-05tests/docker: Add python3-venv and netcat to the debian-amd64 containerThomas Huth
Without python3-venv, I get the following message when trying to run the acceptance tests within the debian container: The virtual environment was not created successfully because ensurepip is not available. On Debian/Ubuntu systems, you need to install the python3-venv package using the following command. apt-get install python3-venv You may need to use sudo with that command. After installing the python3-venv package, recreate your virtual environment. Let's do it as the message suggests. And while we're at it, also add netcat here since it is required for some of the acceptance tests. Message-Id: <20200730141326.8260-2-thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-08-04Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200804' into staging target-arm queue: * Fix decode of LDRA[AB] instructions * docs/devel: Document decodetree no-overlap groups # gpg: Signature made Tue 04 Aug 2020 17:08:11 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200804: target/arm: Fix decode of LDRA[AB] instructions docs/devel: Document decodetree no-overlap groups Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-04Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
virtio: bugfix A last minute bugfix. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 04 Aug 2020 16:48:37 BST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: virtio-mem: Correct format specifier mismatch for RISC-V Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-04virtio-mem: Correct format specifier mismatch for RISC-VBruce Rogers
This likely affects other, less popular host architectures as well. Less common host architectures under linux get QEMU_VMALLOC_ALIGN (from which VIRTIO_MEM_MIN_BLOCK_SIZE is derived) define to a variable of type uintptr, which isn't compatible with the format specifier used to print a user message. Since this particular usage of the underlying data seems unique to this file, the simple fix is to just cast QEMU_VMALLOC_ALIGN to uint32_t, which corresponds to the format specifier used. Signed-off-by: Bruce Rogers <brogers@suse.com> Message-Id: <20200730130519.168475-1-brogers@suse.com> Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Pankaj Gupta <pankaj.gupta.linux@gmail.com>
2020-08-04target/arm: Fix decode of LDRA[AB] instructionsPeter Collingbourne
These instructions use zero as the discriminator, not SP. Signed-off-by: Peter Collingbourne <pcc@google.com> Message-id: 20200804002849.30268-1-pcc@google.com Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-04docs/devel: Document decodetree no-overlap groupsRichard Henderson
When support for this feature went in, the update to the documentation was forgotten. Fixes: 067e8b0f45d6 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200803205708.315829-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-04Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200804' into ↵Peter Maydell
staging xen patch Bug fix. # gpg: Signature made Tue 04 Aug 2020 10:24:51 BST # gpg: using RSA key F80C006308E22CFD8A92E7980CF5572FD7FB55AF # gpg: issuer "anthony.perard@citrix.com" # gpg: Good signature from "Anthony PERARD <anthony.perard@gmail.com>" [marginal] # gpg: aka "Anthony PERARD <anthony.perard@citrix.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 5379 2F71 024C 600F 778A 7161 D8D5 7199 DF83 42C8 # Subkey fingerprint: F80C 0063 08E2 2CFD 8A92 E798 0CF5 572F D7FB 55AF * remotes/aperard/tags/pull-xen-20200804: accel/xen: Fix xen_enabled() behavior on target-agnostic objects Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-04accel/xen: Fix xen_enabled() behavior on target-agnostic objectsPhilippe Mathieu-Daudé
CONFIG_XEN is generated by configure and stored in "config-target.h", which is (obviously) only include for target-specific objects. This is a problem for target-agnostic objects as CONFIG_XEN is never defined and xen_enabled() is always inlined as 'false'. Fix by following the KVM schema, defining CONFIG_XEN_IS_POSSIBLE when we don't know to force the call of the non-inlined function, returning the xen_allowed boolean. Fixes: da278d58a092 ("accel: Move Xen accelerator code under accel/xen/") Reported-by: Paul Durrant <pdurrant@amazon.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20200804074930.13104-2-philmd@redhat.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2020-08-04Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into ↵Peter Maydell
staging # gpg: Signature made Tue 04 Aug 2020 07:15:08 BST # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * remotes/jasowang/tags/net-pull-request: hw/net/net_tx_pkt: fix assertion failure in net_tx_pkt_add_raw_fragment() colo-compare: Remove superfluous NULL-pointer checks for s->iothread Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-04hw/net/net_tx_pkt: fix assertion failure in net_tx_pkt_add_raw_fragment()Mauro Matteo Cascella
An assertion failure issue was found in the code that processes network packets while adding data fragments into the packet context. It could be abused by a malicious guest to abort the QEMU process on the host. This patch replaces the affected assert() with a conditional statement, returning false if the current data fragment exceeds max_raw_frags. Reported-by: Alexander Bulekov <alxndr@bu.edu> Reported-by: Ziming Zhang <ezrakiez@gmail.com> Reviewed-by: Dmitry Fleytman <dmitry.fleytman@gmail.com> Signed-off-by: Mauro Matteo Cascella <mcascell@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2020-08-04colo-compare: Remove superfluous NULL-pointer checks for s->iothreadLukas Straub
s->iothread is checked for NULL on object creation in colo_compare_complete, so it's guaranteed not to be NULL. This resolves a false alert from Coverity (CID 1429969). Signed-off-by: Lukas Straub <lukasstraub2@web.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Zhang Chen <chen.zhang@intel.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2020-08-03Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200803' into staging target-arm queue: * hw/timer/imx_epit: Avoid assertion when CR.SWR is written * netduino2, netduinoplus2, microbit: set system_clock_scale so that SysTick running on the CPU clock works * target/arm: Avoid maybe-uninitialized warning with gcc 4.9 * target/arm: Fix AddPAC error indication * Make AIRCR.SYSRESETREQ actually reset the system for the microbit, mps2-*, musca-*, netduino* boards # gpg: Signature made Mon 03 Aug 2020 20:29:17 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200803: hw/timer/imx_epit: Avoid assertion when CR.SWR is written hw/arm/nrf51_soc: Set system_clock_scale target/arm: Avoid maybe-uninitialized warning with gcc 4.9 target/arm: Fix AddPAC error indication msf2-soc, stellaris: Don't wire up SYSRESETREQ hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ include/hw/irq.h: New function qemu_irq_is_connected() hw/arm/netduino2, netduinoplus2: Set system_clock_scale Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-03hw/timer/imx_epit: Avoid assertion when CR.SWR is writtenPeter Maydell
The imx_epit device has a software-controllable reset triggered by setting the SWR bit in the CR register. An error in commit cc2722ec83ad9 means that we will end up assert()ing if the guest does this, because the code in imx_epit_write() starts ptimer transactions, and then imx_epit_reset() also starts ptimer transactions, triggering "ptimer_transaction_begin: Assertion `!s->in_transaction' failed". The cleanest way to avoid this double-transaction is to move the start-transaction for the CR write handling down below the check of the SWR bit. Fixes: https://bugs.launchpad.net/qemu/+bug/1880424 Fixes: cc2722ec83ad944505fe Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200727154550.3409-1-peter.maydell@linaro.org
2020-08-03hw/arm/nrf51_soc: Set system_clock_scalePeter Maydell
The nrf51 SoC model wasn't setting the system_clock_scale global.which meant that if guest code used the systick timer in "use the processor clock" mode it would hang because time never advances. Set the global to match the documented CPU clock speed for this SoC. This SoC in fact doesn't have a SysTick timer (which is the only thing currently that cares about the system_clock_scale), because it's a configurable option in the Cortex-M0. However our Cortex-M0 and thus our nrf51 and our micro:bit board do provide a SysTick, so we ought to provide a functional one rather than a broken one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200727193458.31250-1-peter.maydell@linaro.org
2020-08-03target/arm: Avoid maybe-uninitialized warning with gcc 4.9Kaige Li
GCC version 4.9.4 isn't clever enough to figure out that all execution paths in disas_ldst() that use 'fn' will have initialized it first, and so it warns: /home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’: /home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used uninitialized in this function [-Werror=maybe-uninitialized] fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), ^ /home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared here AtomicThreeOpFn *fn; ^ Make it happy by initializing the variable to NULL. Signed-off-by: Kaige Li <likaige@loongson.cn> Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: Clean up commit message and note which gcc version this was] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-03target/arm: Fix AddPAC error indicationRichard Henderson
The definition of top_bit used in this function is one higher than that used in the Arm ARM psuedo-code, which put the error indication at top_bit - 1 at the wrong place, which meant that it wasn't visible to Auth. Fixing the definition of top_bit requires more changes, because its most common use is for the count of bits in top_bit:bot_bit, which would then need to be computed as top_bit - bot_bit + 1. For now, prefer the minimal fix to the error indication alone. Fixes: 63ff0ca94cb Reported-by: Derrick McKee <derrick.mckee@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200728195706.11087-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added comment about the divergence from the pseudocode] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-03msf2-soc, stellaris: Don't wire up SYSRESETREQPeter Maydell
The MSF2 SoC model and the Stellaris board code both wire SYSRESETREQ up to a function that just invokes qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); This is now the default action that the NVIC does if the line is not connected, so we can delete the handling code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200728103744.6909-4-peter.maydell@linaro.org
2020-08-03hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for ↵Peter Maydell
SYSRESETREQ The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals when the guest sets the SYSRESETREQ bit in the AIRCR register. This matches the hardware design (where the CPU has a signal of this name and it is up to the SoC to connect that up to an actual reset mechanism), but in QEMU it mostly results in duplicated code in SoC objects and bugs where SoC model implementors forget to wire up the SYSRESETREQ line. Provide a default behaviour for the case where SYSRESETREQ is not actually connected to anything: use qemu_system_reset_request() to perform a system reset. This will allow us to remove the implementations of SYSRESETREQ handling from the boards where that's exactly what it does, and also fixes the bugs in the board models which forgot to wire up the signal: * microbit * mps2-an385 * mps2-an505 * mps2-an511 * mps2-an521 * musca-a * musca-b1 * netduino * netduinoplus2 We still allow the board to wire up the signal if it needs to, in case we need to model more complicated reset controller logic or to model buggy SoC hardware which forgot to wire up the line itself. But defaulting to "reset the system" is more often going to be correct than defaulting to "do nothing". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200728103744.6909-3-peter.maydell@linaro.org
2020-08-03include/hw/irq.h: New function qemu_irq_is_connected()Peter Maydell
Mostly devices don't need to care whether one of their output qemu_irq lines is connected, because functions like qemu_set_irq() silently do nothing if there is nothing on the other end. However sometimes a device might want to implement default behaviour for the case where the machine hasn't wired the line up to anywhere. Provide a function qemu_irq_is_connected() that devices can use for this purpose. (The test is trivial but encapsulating it in a function makes it easier to see where we're doing it in case we need to change the implementation later.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200728103744.6909-2-peter.maydell@linaro.org
2020-08-03hw/arm/netduino2, netduinoplus2: Set system_clock_scalePeter Maydell
The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale global, which meant that if guest code used the systick timer in "use the processor clock" mode it would hang because time never advances. Set the global to match the documented CPU clock speed of these boards. Judging by the data sheet this is slightly simplistic because the SoC allows configuration of the SYSCLK source and frequency via the RCC (reset and clock control) module, but we don't model that. Fixes: https://bugs.launchpad.net/qemu/+bug/1876187 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200727162617.26227-1-peter.maydell@linaro.org
2020-08-03Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-08-03' ↵Peter Maydell
into staging bitmaps patches for 2020-08-03 - fix bitmap migration involving read-only bitmap from backing chain # gpg: Signature made Mon 03 Aug 2020 15:06:51 BST # gpg: using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" [full] # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" [full] # gpg: aka "[jpeg image of size 6874]" [full] # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-bitmaps-2020-08-03: iotests/169: Test source cont with backing bmap qcow2: Release read-only bitmaps when inactivated Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-03iotests/169: Test source cont with backing bmapMax Reitz
Test migrating from a VM with a persistent bitmap in the backing chain, and then continuing that VM after the migration Signed-off-by: Max Reitz <mreitz@redhat.com> Message-Id: <20200730120234.49288-3-mreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Eric Blake <eblake@redhat.com>
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