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2019-09-05target/arm: Convert CLZRichard Henderson
Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour. This matches the undocumented choice made by the legacy decoder. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert BX, BXJ, BLX (register)Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Cyclic Redundancy CheckRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert MRS/MSR (banked, register)Richard Henderson
The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert MSR (immediate) and hintsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Simplify op_smlawx for SMLAW*Richard Henderson
By shifting the 16-bit input left by 16, we can align the desired portion of the 48-bit product and use tcg_gen_muls2_i32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Simplify op_smlaxxx for SMLAL*Richard Henderson
Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_add2_i32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Halfword multiply and multiply accumulateRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Saturating addition and subtractionRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Simplify UMAALRichard Henderson
Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_mulu2_i32 and tcg_gen_add2_i32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert multiply and multiply accumulateRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Data Processing (immediate)Richard Henderson
Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Data Processing (reg-shifted-reg)Richard Henderson
Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Data Processing (register)Richard Henderson
Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Add stubs for aa32 decodetreeRichard Henderson
Add the infrastructure that will become the new decoder. No instructions adjusted so far. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Use store_reg_from_load in thumb2 codeRichard Henderson
This function already includes the test for an interworking write to PC from a load. Change the T32 LDM implementation to match the A32 LDM implementation. For LDM, the reordering of the tests does not change valid behaviour because the only case that differs is has rn == 15, which is UNPREDICTABLE. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20190904' into stagingPeter Maydell
Updates for arch v1.3. # gpg: Signature made Wed 04 Sep 2019 21:30:41 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-or1k-20190904: target/openrisc: Update cpu "any" to v1.3 target/openrisc: Implement l.adrp target/openrisc: Implement move to/from FPCSR target/openrisc: Implement unordered fp comparisons target/openrisc: Add support for ORFPX64A32 target/openrisc: Check CPUCFG_OF32S for float insns target/openrisc: Fix lf.ftoi.s target/openrisc: Add VR2 and AVR special processor registers target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init target/openrisc: Make VR and PPC read-only target/openrisc: Cache R0 in DisasContext target/openrisc: Replace cpu register array with a function target/openrisc: Add DisasContext parameter to check_r0_write Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04target/openrisc: Update cpu "any" to v1.3Richard Henderson
Now that the two updates from v1.3 are implemented, update the "any" cpu to enable it. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Implement l.adrpRichard Henderson
This was added to the 1.3 spec. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Implement move to/from FPCSRRichard Henderson
Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Implement unordered fp comparisonsRichard Henderson
These were added to the 1.3 spec. For OF32S, validate AVR. But OF64A32 is itself new to 1.3 so no extra check needed. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Add support for ORFPX64A32Richard Henderson
This is hardware support for double-precision floating-point using pairs of 32-bit registers. Fix latent bugs in the heretofore unused helper_itofd and helper_ftoid. Include the bit for cpu "any". Change the default cpu for linux-user to "any". Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson
Make sure the OF32S insns are enabled before allowing execution. Include the missing bit for cpu "any". Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Fix lf.ftoi.sRichard Henderson
The specification of this insn is round-to-zero. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Add VR2 and AVR special processor registersRichard Henderson
Update the CPUCFG bits to arch v1.3. Include support for AVRP for cpu "any". Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu initRichard Henderson
These registers are read-only and implementation specific. Initiailize VR for the first time; take the OR1200 values from the verilog source. Note that moving fields within CPUOpenRISCState does not affect migration. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Make VR and PPC read-onlyRichard Henderson
These SPRs are read-only. The writes can simply be ignored, as we already do for other read-only (or missing) registers. There is no reason to mask the value in env->vr. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Cache R0 in DisasContextRichard Henderson
Finish the race condition fix from the previous patch. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Replace cpu register array with a functionRichard Henderson
The writes to cpu_R[0] are now a race across threads, now that we do code generation in parallel. Stage the change by introducing a function to return the temp for R0. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Add DisasContext parameter to check_r0_writeRichard Henderson
We will need this context in the next patch. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
virtio,vhost: fixes, features, cleanups. FLR support. Misc fixes, cleanups. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 04 Sep 2019 12:53:35 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: libvhost-user: introduce and use vu_has_protocol_feature() libvhost-user: fix SLAVE_SEND_FD handling virtio-pci: Add Function Level Reset support virtio-rng: change default backend to rng-builtin virtio-rng: Keep the default backend out of VirtIORNGConf rng-builtin: add an RNG backend that uses qemu_guest_getrandom() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190903' into stagingPeter Maydell
Allow page table bit to swap endianness. Reorganize watchpoints out of i/o path. Return host address from probe_write / probe_access. # gpg: Signature made Tue 03 Sep 2019 16:47:50 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190903: (36 commits) tcg: Factor out probe_write() logic into probe_access() tcg: Make probe_write() return a pointer to the host page s390x/tcg: Pass a size to probe_write() in do_csst() hppa/tcg: Call probe_write() also for CONFIG_USER_ONLY mips/tcg: Call probe_write() for CONFIG_USER_ONLY as well tcg: Enforce single page access in probe_write() tcg: Factor out CONFIG_USER_ONLY probe_write() from s390x code s390x/tcg: Fix length calculation in probe_write_access() s390x/tcg: Use guest_addr_valid() instead of h2g_valid() in probe_write_access() tcg: Check for watchpoints in probe_write() cputlb: Handle watchpoints via TLB_WATCHPOINT cputlb: Remove double-alignment in store_helper cputlb: Fix size operand for tlb_fill on unaligned store exec: Factor out cpu_watchpoint_address_matches cputlb: Fold TLB_RECHECK into TLB_INVALID_MASK exec: Factor out core logic of check_watchpoint() exec: Move user-only watchpoint stubs inline target/sparc: sun4u Invert Endian TTE bit target/sparc: Add TLB entry with attributes cputlb: Byte swap memory transaction attribute ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04Merge remote-tracking branch 'remotes/juanquintela/tags/fail-pull-request' ↵Peter Maydell
into staging Fix multifd with big number of channels # gpg: Signature made Wed 04 Sep 2019 07:28:31 BST # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * remotes/juanquintela/tags/fail-pull-request: multifd: Use number of channels as listen backlog socket: Add num connections to qio_net_listener_open_sync() socket: Add num connections to qio_channel_socket_async() socket: Add num connections to qio_channel_socket_sync() socket: Add backlog parameter to socket_listen Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine + x86 queue, 2019-09-03 Bug fixes: * Fix die-id validation regression (Eduardo Habkost) * vmmouse: Properly reset state (Jan Kiszka) * hostmem-file: fix pmem file size check (Stefan Hajnoczi) * Keep query-hotpluggable-cpus output compatible with older QEMU if '-smp dies' is not set (Igor Mammedov) * migration: Do not re-read the clock on pre_save in case of paused guest (Maxiwell S. Garcia) Cleanups: * NUMA code cleanups (Tao Xu) * Remove stale externs from includes (Alex Bennée) Features: * qapi: report the default CPU type for each machine (Daniel P. Berrangé) # gpg: Signature made Tue 03 Sep 2019 21:57:37 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: migration: Do not re-read the clock on pre_save in case of paused guest x86: do not advertise die-id in query-hotpluggbale-cpus if '-smp dies' is not set i386/vmmouse: Properly reset state hostmem-file: fix pmem file size check qapi: report the default CPU type for each machine pc: Don't make die-id mandatory unless necessary pc: Improve error message when die-id is omitted pc: Fix error message on die-id validation numa: move numa global variable numa_info into MachineState numa: move numa global variable have_numa_distance into MachineState numa: move numa global variable nb_numa_nodes into MachineState hw/arm: simplify arm_load_dtb includes: remove stale [smp|max]_cpus externs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20190903' into staging target-arm queue: * Revert and correctly fix refactoring of unallocated_encoding() * Take exceptions on ATS instructions when needed * aspeed/timer: Provide back-pressure information for short periods * memory: Remove unused memory_region_iommu_replay_all() * hw/arm/smmuv3: Log a guest error when decoding an invalid STE * hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations * target/arm: Fix SMMLS argument order * hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate * hw/arm: Correct reference counting for creation of various objects * includes: remove stale [smp|max]_cpus externs * tcg/README: fix typo * atomic_template: fix indentation in GEN_ATOMIC_HELPER * include/exec/cpu-defs.h: fix typo * target/arm: Free TCG temps in trans_VMOV_64_sp() * target/arm: Don't abort on M-profile exception return in linux-user mode # gpg: Signature made Tue 03 Sep 2019 16:35:19 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190903: (21 commits) target/arm: Don't abort on M-profile exception return in linux-user mode target/arm: Free TCG temps in trans_VMOV_64_sp() include/exec/cpu-defs.h: fix typo atomic_template: fix indentation in GEN_ATOMIC_HELPER tcg/README: fix typo s/afterwise/afterwards/ includes: remove stale [smp|max]_cpus externs hw/net/xilinx_axi: Use object_initialize_child for correct ref. counting hw/dma/xilinx_axi: Use object_initialize_child for correct ref. counting hw/arm/fsl-imx: Add the cpu as child of the SoC object hw/arm: Use sysbus_init_child_obj for correct reference counting hw/arm: Use object_initialize_child for correct reference counting hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate target/arm: Fix SMMLS argument order hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations hw/arm/smmuv3: Log a guest error when decoding an invalid STE memory: Remove unused memory_region_iommu_replay_all() aspeed/timer: Provide back-pressure information for short periods target/arm: Take exceptions on ATS instructions when needed target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions target/arm: Factor out unallocated_encoding for aarch32 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04libvhost-user: introduce and use vu_has_protocol_feature()Johannes Berg
This simplifies the various has_feature() checks, we already have vu_has_feature() but it checks features, not protocol features. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Message-Id: <20190904065021.1360-1-johannes@sipsolutions.net> Reviewed-by: Tiwei Bie <tiwei.bie@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-09-04Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2019-09-03' ↵Peter Maydell
into staging Block patches: - qemu-io now accepts a file to read a write pattern from - Ensure that raw files have their first block allocated so we can probe the O_DIRECT alignment if necessary - Various fixes # gpg: Signature made Tue 03 Sep 2019 13:58:57 BST # gpg: using RSA key 91BEB60A30DB3E8857D11829F407DB0061D5CF40 # gpg: issuer "mreitz@redhat.com" # gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full] # Primary key fingerprint: 91BE B60A 30DB 3E88 57D1 1829 F407 DB00 61D5 CF40 * remotes/maxreitz/tags/pull-block-2019-09-03: iotests: Unify cache mode quoting tests/check-block: Skip iotests when sanitizers are enabled iotests: Check for enabled drivers before testing them iotests: Add -display none to the qemu options file-posix: fix request_alignment typo iotests: Disable 126 for flat vmdk subformats iotests: Disable 110 for vmdk.twoGbMaxExtentSparse iotests: Disable broken streamOptimized tests vmdk: Reject invalid compressed writes iotests: Keep testing broken relative extent paths vmdk: Use bdrv_dirname() for relative extent paths iotests: Fix _filter_img_create() iotests: Test allocate_first_block() with O_DIRECT block: posix: Always allocate the first block block: fix permission update in bdrv_replace_node qemu-io: add pattern file for write command Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04libvhost-user: fix SLAVE_SEND_FD handlingJohannes Berg
It doesn't look like this could possibly work properly since VHOST_USER_PROTOCOL_F_SLAVE_SEND_FD is defined to 10, but the dev->protocol_features has a bitmap. I suppose the peer this was tested with also supported VHOST_USER_PROTOCOL_F_LOG_SHMFD, in which case the test would always be false, but nevertheless the code seems wrong. Use has_feature() to fix this. Fixes: d84599f56c82 ("libvhost-user: support host notifier") Signed-off-by: Johannes Berg <johannes.berg@intel.com> Message-Id: <20190903200422.11693-1-johannes@sipsolutions.net> Reviewed-by: Tiwei Bie <tiwei.bie@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-09-04virtio-pci: Add Function Level Reset supportJulia Suvorova
Using FLR becomes convenient in cases where resetting the bus is impractical, for example, when debugging the behavior of individual functions. Signed-off-by: Julia Suvorova <jusual@redhat.com> Message-Id: <20190820163005.1880-1-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-09-04virtio-rng: change default backend to rng-builtinLaurent Vivier
Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20190820160615.14616-4-lvivier@redhat.com>
2019-09-04virtio-rng: Keep the default backend out of VirtIORNGConfMarkus Armbruster
The default backend is only used within virtio_rng_device_realize(). Replace VirtIORNGConf member default_backend by a local variable. Adjust its type to reduce conversions. While there, pass &error_abort instead of NULL when failure would be a programming error. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20190820160615.14616-3-lvivier@redhat.com>
2019-09-04rng-builtin: add an RNG backend that uses qemu_guest_getrandom()Laurent Vivier
Add a new RNG backend using QEMU builtin getrandom function. It can be created and used with something like: ... -object rng-builtin,id=rng0 -device virtio-rng,rng=rng0 ... Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20190820160615.14616-2-lvivier@redhat.com>
2019-09-04Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-gdbstub-gitdm-testing-020919-1' into staging Various maintainer updates - fixes for gdbstub regressions - bunch of gitdm/mailmap updates - module fixes for Travis - docker fixes for shippable # gpg: Signature made Mon 02 Sep 2019 11:19:04 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-gdbstub-gitdm-testing-020919-1: tests/docker: upgrade docker.py to python3 tests: fix modules-test with no default machine build-sys: build ui-spice-app as a module contrib/gitdm: Add RT-RK to the domain-map .mailmap/aliases: add some further commentary mailmap: Add many entries to improve 'git shortlog' statistics mailmap: Update philmd email address mailmap: Reorder by sections contrib/gitdm: Add armbru@pond.sub.org to group-map-redhat contrib/gitdm: filetype interface is not in order, fix gdbstub: Fix handler for 'F' packet gdbstub: Fix handling of '!' packet with new infra Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-29-2019' ↵Peter Maydell
into staging MIPS queue for August 29th, 2019 # gpg: Signature made Thu 29 Aug 2019 11:19:28 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-aug-29-2019: (31 commits) target/mips: Fix emulation of ST.W in system mode target/mips: Clean up handling of CP0 register 31 target/mips: Clean up handling of CP0 register 30 target/mips: Clean up handling of CP0 register 29 target/mips: Clean up handling of CP0 register 28 target/mips: Clean up handling of CP0 register 27 target/mips: Clean up handling of CP0 register 26 target/mips: Clean up handling of CP0 register 25 target/mips: Clean up handling of CP0 register 24 target/mips: Clean up handling of CP0 register 23 target/mips: Clean up handling of CP0 register 20 target/mips: Clean up handling of CP0 register 19 target/mips: Clean up handling of CP0 register 18 target/mips: Clean up handling of CP0 register 17 target/mips: Clean up handling of CP0 register 16 target/mips: Clean up handling of CP0 register 15 target/mips: Clean up handling of CP0 register 14 target/mips: Clean up handling of CP0 register 13 target/mips: Clean up handling of CP0 register 12 target/mips: Clean up handling of CP0 register 11 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04Merge remote-tracking branch 'remotes/kraxel/tags/usb-20190829-pull-request' ↵Peter Maydell
into staging usb: bugfixes for xhci and mtp. # gpg: Signature made Thu 29 Aug 2019 08:10:05 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20190829-pull-request: usb-mtp: add sanity checks on rootdir xhci: Fix memory leak in xhci_kick_epctx xhci: Fix memory leak in xhci_address_slot Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-03multifd: Use number of channels as listen backlogJuan Quintela
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2019-09-03socket: Add num connections to qio_net_listener_open_sync()Juan Quintela
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2019-09-03socket: Add num connections to qio_channel_socket_async()Juan Quintela
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2019-09-03socket: Add num connections to qio_channel_socket_sync()Juan Quintela
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2019-09-03socket: Add backlog parameter to socket_listenJuan Quintela
Current parameter was always one. We continue with that value for now in all callers. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> --- Moved trace to socket_listen
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-03 18:38:57 +0000