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2020-09-15qcow2: Make qcow2_free_any_clusters() free only one clusterAlberto Garcia
This function takes an L2 entry and a number of clusters to free. Although in principle it can free any type of cluster (using the L2 entry to determine its type) in practice the API is broken because compressed clusters have a variable size and there is no way to free more than one without having the L2 entry of each one of them. The good news all callers are passing nb_clusters=1 so we can simply get rid of that parameter. Signed-off-by: Alberto Garcia <berto@igalia.com> Message-Id: <77cea0f4616f921d37e971b3c5b18a2faa24b173.1599573989.git.berto@igalia.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qcow2: Handle QCowL2Meta on error in preallocate_co()Alberto Garcia
If qcow2_alloc_cluster_offset() or qcow2_alloc_cluster_link_l2() fail then this function simply returns the error code, potentially leaking the QCowL2Meta structure and leaving stale items in s->cluster_allocs. A second problem is that this function calls qcow2_free_any_clusters() on failure but passing a host cluster offset instead of an L2 entry. Luckily for normal uncompressed clusters a raw offset also works like a valid L2 entry so it works just the same, but we should be using qcow2_free_clusters() instead. This patch fixes both problems by using qcow2_handle_l2meta(). Signed-off-by: Alberto Garcia <berto@igalia.com> Message-Id: <cd3a6b9abd43f9c0b60be413d760f0cacc67eb66.1599573989.git.berto@igalia.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15block/vhdx: Support vhdx image only with 512 bytes logical sector sizeSwapnil Ingle
block/vhdx uses qemu block layer where sector size is always 512 bytes. This may have issues with 4K logical sector sized vhdx image. For e.g qemu-img convert on such images fails with following assert: $qemu-img convert -f vhdx -O raw 4KTest1.vhdx test.raw qemu-img: util/iov.c:388: qiov_slice: Assertion `offset + len <= qiov->size' failed. Aborted This patch adds an check to return ENOTSUP for vhdx images which have logical sector size other than 512 bytes. Signed-off-by: Swapnil Ingle <swapnil.ingle@nutanix.com> Message-Id: <1596794594-44531-1-git-send-email-swapnil.ingle@nutanix.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15iotests: Skip test_stream_parallel in test 030 when doing "make check"Thomas Huth
The test_stream_parallel test still occasionally fails in the CI. Thus let's disable it during "make check" for now so that it does not cause trouble during merge tests. We can enable it again once the problem has been resolved. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200907113824.134788-1-thuth@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qemu-img: Explicit number replaced by a constantYi Li
Signed-off-by: Yi Li <yili@winhong.com> Message-Id: <20200819013607.32280-1-yili@winhong.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qcow2: Rewrite the documentation of qcow2_alloc_cluster_offset()Alberto Garcia
The current text corresponds to an earlier, simpler version of this function and it does not explain how it works now. Signed-off-by: Alberto Garcia <berto@igalia.com> Message-Id: <bb5bd06f07c5a05b0818611de0d06ec5b66c8df3.1599150873.git.berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qcow2: Don't check nb_clusters when removing l2meta from the listAlberto Garcia
In the past, when a new cluster was allocated the l2meta structure was a variable in the stack so it was necessary to have a way to tell whether it had been initialized and contained valid data or not. The nb_clusters field was used for this purpose. Since commit f50f88b9fe this is no longer the case, l2meta (nowadays a pointer to a list) is only allocated when needed and nb_clusters is guaranteed to be > 0 so this check is unnecessary. Signed-off-by: Alberto Garcia <berto@igalia.com> Message-Id: <ab0b67c29c7ba26e598db35f12aa5ab5982539c1.1599150873.git.berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qcow2: Fix removal of list members from BDRVQcow2State.cluster_allocsAlberto Garcia
When a write request needs to allocate new clusters (or change the L2 bitmap of existing ones) a QCowL2Meta structure is created so the L2 metadata can be later updated and any copy-on-write can be performed if necessary. A write request can span a region consisting of an arbitrary combination of previously unallocated and allocated clusters, and if the unallocated ones can be put contiguous to the existing ones then QEMU will do so in order to minimize the number of write operations. In practice this means that a write request has not just one but a number of QCowL2Meta structures. All of them are added to the cluster_allocs list that is stored in BDRVQcow2State and is used to detect overlapping requests. After the write request finishes all its associated QCowL2Meta are removed from that list. calculate_l2_meta() takes care of creating and putting those structures in the list, and qcow2_handle_l2meta() takes care of removing them. The problem is that the error path in handle_alloc() also tries to remove an item in that list, a remnant from the time when this was handled there (that code would not even be correct anymore because it only removes one struct and not all the ones from the same write request). This can trigger a double removal of the same item from the list, causing a crash. This is not easy to reproduce in practice because it requires that do_alloc_cluster_offset() fails after a successful previous allocation during the same write request, but it can be reproduced with the included test case. Signed-off-by: Alberto Garcia <berto@igalia.com> Message-Id: <3440a1c4d53c4fe48312b478c96accb338cbef7c.1599150873.git.berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qcow2: Use macros for the L1, refcount and bitmap table entry sizesAlberto Garcia
This patch replaces instances of sizeof(uint64_t) in the qcow2 driver with macros that indicate what those sizes are actually referring to. Signed-off-by: Alberto Garcia <berto@igalia.com> Message-Id: <20200828110828.13833-1-berto@igalia.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qemu-img: avoid unaligned read requests during convertPeter Lieven
in case of large continous areas that share the same allocation status it happens that the value of s->sector_next_status is unaligned to the cluster size or even request alignment of the source. Avoid this by stripping down the s->sector_next_status position to cluster boundaries. Signed-off-by: Peter Lieven <pl@kamp.de> Message-Id: <20200901125129.6398-1-pl@kamp.de> [mreitz: Disable vhdx for 251] Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15block/quorum.c: stable children namesLukas Straub
If we remove the child with the highest index from the quorum, decrement s->next_child_index. This way we get stable children names as long as we only remove the last child. Signed-off-by: Lukas Straub <lukasstraub2@web.de> Fixes: https://bugs.launchpad.net/bugs/1881231 Reviewed-by: Zhang Chen <chen.zhang@intel.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Message-Id: <5d5f930424c1c770754041aa8ad6421dc4e2b58e.1596536719.git.lukasstraub2@web.de> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qemu-iotests: Simplify FilePath __init__Nir Soffer
Use list comprehension instead of append loop. Signed-off-by: Nir Soffer <nsoffer@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20200828232152.205833-6-nsoffer@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qemu-iotests: Merge FilePaths and FilePathNir Soffer
FilePath creates now one temporary file: with FilePath("a") as a: Or more: with FilePath("a", "b", "c") as (a, b, c): This is also the behavior of the file_path() helper, used by some of the tests. Now we have only 2 helpers for creating temporary files instead of 3. Signed-off-by: Nir Soffer <nsoffer@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20200828232152.205833-5-nsoffer@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qemu-iotests: Support varargs syntax in FilePathsNir Soffer
Accept variable number of names instead of a sequence: with FilePaths("a", "b", "c") as (a, b, c): The disadvantage is that base_dir must be used as kwarg: with FilePaths("a", "b", base_dir=soc_dir) as (sock1, sock2): But this is more clear and calling optional argument as positional arguments is bad idea anyway. Signed-off-by: Nir Soffer <nsoffer@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20200828232152.205833-4-nsoffer@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qemu-iotests: Fix FilePaths docstringNir Soffer
When this class was extracted from FilePath, the docstring was not updated for generating multiple files, and the example usage was referencing unrelated file. While fixing the docstring, add example for creating sockets, which should use iotests.sock_dir instead of the default base_dir. Fixes: de263986b5dc Signed-off-by: Nir Soffer <nsoffer@redhat.com> Message-Id: <20200828232152.205833-3-nsoffer@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-15qemu-iotests: Fix FilePaths cleanupNir Soffer
If os.remove() fails to remove one of the paths, for example if the file was removed by the test, the cleanup loop would exit silently, without removing the rest of the files. Fixes: de263986b5dc Signed-off-by: Nir Soffer <nsoffer@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20200828232152.205833-2-nsoffer@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-09-14Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200914-1' into staging * hw/misc/a9scu: Do not allow invalid CPU count * hw/misc/a9scu: Minor cleanups * hw/timer/armv7m_systick: assert that board code set system_clock_scale * decodetree: Improve identifier matching * target/arm: Clean up neon fp insn size field decode * target/arm: Remove KVM support for 32-bit Arm hosts * hw/arm/mps2: New board models mps2-an386, mps2-an500 * Deprecate Unicore32 port * Deprecate lm32 port * target/arm: Count PMU events when MDCR.SPME is set * hw/arm: versal-virt: Correct the tx/rx GEM clocks * New Nuvoton iBMC board models npcm750-evb, quanta-gsj # gpg: Signature made Mon 14 Sep 2020 16:02:06 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200914-1: (32 commits) tests/acceptance: console boot tests for quanta-gsj docs/system: Add Nuvoton machine documentation hw/arm/npcm7xx: add board setup stub for CPU and UART clocks hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj hw/ssi: NPCM7xx Flash Interface Unit device model hw/mem: Stubbed out NPCM7xx Memory Controller model hw/nvram: NPCM7xx OTP device model hw/arm: Load -bios image as a boot ROM for npcm7xx roms: Add virtual Boot ROM for NPCM7xx SoCs hw/arm: Add two NPCM7xx-based machines hw/arm: Add NPCM730 and NPCM750 SoC models hw/timer: Add NPCM7xx Timer device model hw/misc: Add NPCM7xx Clock Controller device model hw/misc: Add NPCM7xx System Global Control Registers device model hw/arm: versal-virt: Correct the tx/rx GEM clocks target/arm: Count PMU events when MDCR.SPME is set Deprecate lm32 port Deprecate Unicore32 port docs/system/arm/mps2.rst: Make board list consistent hw/arm/mps2: New board model mps2-an500 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14tests/acceptance: console boot tests for quanta-gsjHavard Skinnemoen
This adds two acceptance tests for the quanta-gsj machine. One test downloads a lightly patched openbmc flash image from github and verifies that it boots all the way to the login prompt. The other test downloads a kernel, initrd and dtb built from the same openbmc source and verifies that the kernel detects all CPUs and boots to the point where it can't find the root filesystem (because we have no flash image in this case). Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-15-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14docs/system: Add Nuvoton machine documentationHavard Skinnemoen
Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-14-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm/npcm7xx: add board setup stub for CPU and UART clocksHavard Skinnemoen
When booting directly into a kernel, bypassing the boot loader, the CPU and UART clocks are not set up correctly. This makes the system appear very slow, and causes the initrd boot test to fail when optimization is off. The UART clock must run at 24 MHz. The default 25 MHz reference clock cannot achieve this, so switch to PLL2/2 @ 480 MHz, which works perfectly with the default /20 divider. The CPU clock should run at 800 MHz, so switch it to PLL1/2. PLL1 runs at 800 MHz by default, so we need to double the feedback divider as well to make it run at 1600 MHz (so PLL1/2 runs at 800 MHz). We don't bother checking for PLL lock because we know our emulated PLLs lock instantly. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-13-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsjHavard Skinnemoen
This allows these NPCM7xx-based boards to boot from a flash image, e.g. one built with OpenBMC. For example like this: IMAGE=${OPENBMC}/build/tmp/deploy/images/gsj/image-bmc qemu-system-arm -machine quanta-gsj -nographic \ -drive file=${IMAGE},if=mtd,bus=0,unit=0,format=raw,snapshot=on Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200911052101.2602693-12-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/ssi: NPCM7xx Flash Interface Unit device modelHavard Skinnemoen
This implements a device model for the NPCM7xx SPI flash controller. Direct reads and writes, and user-mode transactions have been tested in various modes. Protection features are not implemented yet. All the FIU instances are available in the SoC's address space, regardless of whether or not they're connected to actual flash chips. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-11-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/mem: Stubbed out NPCM7xx Memory Controller modelHavard Skinnemoen
This just implements the bare minimum to cause the boot block to skip memory initialization. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-10-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/nvram: NPCM7xx OTP device modelHavard Skinnemoen
This supports reading and writing OTP fuses and keys. Only fuse reading has been tested. Protection is not implemented. Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-9-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Load -bios image as a boot ROM for npcm7xxHavard Skinnemoen
If a -bios option is specified on the command line, load the image into the internal ROM memory region, which contains the first instructions run by the CPU after reset. If -bios is not specified, the vbootrom included with qemu is loaded by default. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-8-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14roms: Add virtual Boot ROM for NPCM7xx SoCsHavard Skinnemoen
This is a minimalistic boot ROM written specifically for use with QEMU. It supports loading the second-stage loader from SPI flash into RAM, SMP boot, and not much else. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-7-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Add two NPCM7xx-based machinesHavard Skinnemoen
This adds two new machines, both supported by OpenBMC: - npcm750-evb: Nuvoton NPCM750 Evaluation Board. - quanta-gsj: A board with a NPCM730 chip. They rely on the NPCM7xx SoC device to do the heavy lifting. They are almost completely identical at the moment, apart from the SoC type, which currently only changes the reset contents of one register (GCR.MDLR), but they might grow apart a bit more as more functionality is added. Both machines can boot the Linux kernel into /bin/sh. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-6-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Add NPCM730 and NPCM750 SoC modelsHavard Skinnemoen
The Nuvoton NPCM7xx SoC family are used to implement Baseboard Management Controllers in servers. While the family includes four SoCs, this patch implements limited support for two of them: NPCM730 (targeted for Data Center applications) and NPCM750 (targeted for Enterprise applications). This patch includes little more than the bare minimum needed to boot a Linux kernel built with NPCM7xx support in direct-kernel mode: - Two Cortex-A9 CPU cores with built-in periperhals. - Global Configuration Registers. - Clock Management. - 3 Timer Modules with 5 timers each. - 4 serial ports. The chips themselves have a lot more features, some of which will be added to the model at a later stage. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-5-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/timer: Add NPCM7xx Timer device modelHavard Skinnemoen
The NPCM730 and NPCM750 SoCs have three timer modules each holding five timers and some shared registers (e.g. interrupt status). Each timer runs at 25 MHz divided by a prescaler, and counts down from a configurable initial value to zero. When zero is reached, the interrupt flag for the timer is set, and the timer is disabled (one-shot mode) or reloaded from its initial value (periodic mode). This implementation is sufficient to boot a Linux kernel configured for NPCM750. Note that the kernel does not seem to actually turn on the interrupts. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-4-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/misc: Add NPCM7xx Clock Controller device modelHavard Skinnemoen
Enough functionality to boot the Linux kernel has been implemented. This includes: - Correct power-on reset values so the various clock rates can be accurately calculated. - Clock enables stick around when written. In addition, a best effort attempt to implement SECCNT and CNTR25M was made even though I don't think the kernel needs them. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-3-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/misc: Add NPCM7xx System Global Control Registers device modelHavard Skinnemoen
Implement a device model for the System Global Control Registers in the NPCM730 and NPCM750 BMC SoCs. This is primarily used to enable SMP boot (the boot ROM spins reading the SCRPAD register) and DDR memory initialization; other registers are best effort for now. The reset values of the MDLR and PWRON registers are determined by the SoC variant (730 vs 750) and board straps respectively. Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-2-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: versal-virt: Correct the tx/rx GEM clocksEdgar E. Iglesias
Correct the GEMs tx/rx clocks to use the 125Mhz fixed-clock. This matches the setup with the fixed-link 100Mbit PHY. It also avoids the following warnings from the Linux kernel driver: eth0: unable to generate target frequency: 125000000 Hz Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20200909174647.662864-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14target/arm: Count PMU events when MDCR.SPME is setAaron Lindsay
This check was backwards when introduced in commit 033614c47de78409ad3fb39bb7bd1483b71c6789: target/arm: Filter cycle counter based on PMCCFILTR_EL0 Cc: qemu-stable@nongnu.org Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14Deprecate lm32 portPeter Maydell
Deprecate our lm32 target support. Michael Walle (former lm32 maintainer) suggested that we do this in 2019: https://www.mail-archive.com/qemu-devel@nongnu.org/msg605024.html because the only public user of the architecture is the many-years-dead milkymist project. (The Linux port to lm32 was never merged upstream.) In commit 4b4d96c776f552e (March 2020) we marked it as 'orphan' in the MAINTAINERS file, but didn't officially deprecate it. Mark it deprecated now, with the intention of removing it from QEMU in mid-2021 before the 6.1 release. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Michael Walle <michael@walle.cc> Message-id: 20200827113259.25064-1-peter.maydell@linaro.org
2020-09-14Deprecate Unicore32 portPeter Maydell
Deprecate our Unicore32 target support: * the Linux kernel dropped support for unicore32 in commit 05119217a9bd199c for its 5.9 release (with rationale in the cover letter: https://lkml.org/lkml/2020/8/3/232 ) * there is apparently no upstream toolchain that can create unicore32 binaries * the maintainer doesn't seem to have made any contributions to QEMU since the port first landed in 2012 * nobody else seems to have made changes to the unicore code except for generic cleanups either Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20200825172719.19422-1-peter.maydell@linaro.org
2020-09-14docs/system/arm/mps2.rst: Make board list consistentPeter Maydell
Make the list of MPS2 boards consistent in the phrasing of each entry, use the correct casing of "Arm", and move the mps2-an511 entry so the list is in numeric order. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-4-peter.maydell@linaro.org
2020-09-14hw/arm/mps2: New board model mps2-an500Peter Maydell
Implement a model of the MPS2 with the AN500 firmware. This is similar to the AN385, with the following differences: * Cortex-M7 CPU * PSRAM is at 0x6000_0000 * Ethernet is at 0xa000_0000 * No zbt_boot_ctrl remapping of the low 16K (but QEMU doesn't implement this anyway) * no "block RAM" at 0x01000000 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-3-peter.maydell@linaro.org
2020-09-14hw/arm/mps2: New board model mps2-an386Peter Maydell
Implement a model of the MPS2 with the AN386 firmware. This is essentially identical to the AN385 firmware, but it has a Cortex-M4 rather than a Cortex-M3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-2-peter.maydell@linaro.org
2020-09-14target/arm: Remove no-longer-reachable 32-bit KVM codePeter Maydell
Now that 32-bit KVM host support is gone, KVM can never be enabled unless CONFIG_AARCH64 is true, and some code paths are no longer reachable and can be deleted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200904154156.31943-3-peter.maydell@linaro.org
2020-09-14target/arm: Remove KVM support for 32-bit Arm hostsPeter Maydell
We deprecated the support for KVM on 32-bit Arm hosts in time for release 5.0, which means that our deprecation policy allows us to drop it in release 5.2. Remove the code. To repeat the rationale from the deprecation note: the Linux kernel dropped support for 32-bit Arm KVM hosts in 5.7. Running 32-bit guests on a 64-bit Arm host remains supported. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200904154156.31943-2-peter.maydell@linaro.org
2020-09-14target/arm: Convert VCMLA, VCADD size field to MO_* in decodePeter Maydell
The VCMLA and VCADD insns have a size field which is 0 for fp16 and 1 for fp32 (note that this is the reverse of the Neon 3-same encoding!). Convert it to MO_* values in decode for consistency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200903133209.5141-4-peter.maydell@linaro.org
2020-09-14target/arm: Convert Neon VCVT fp size field to MO_* in decodePeter Maydell
Convert the insns using the 2reg_vcvt and 2reg_vcvt_f16 formats to pass the size through to the trans function as a MO_* value rather than the '0==f32, 1==f16' used in the fp 3-same encodings. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200903133209.5141-3-peter.maydell@linaro.org
2020-09-14target/arm: Convert Neon 3-same-fp size field to MO_* in decodePeter Maydell
In the Neon instructions, some instruction formats have a 2-bit size field which corresponds exactly to QEMU's MO_8/16/32/64. However the floating-point insns in the 3-same group have a 1-bit size field which is "0 for 32-bit float and 1 for 16-bit float". Currently we pass these values directly through to trans_ functions, which means that when reading a particular trans_ function you need to know if that insn uses a 2-bit size or a 1-bit size. Move the handling of the 1-bit size to the decodetree file, so that all these insns consistently pass a size to the trans_ function which is an MO_8/16/32/64 value. In this commit we switch over the insns using the 3same_fp and 3same_fp_q0 formats. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200903133209.5141-2-peter.maydell@linaro.org
2020-09-14decodetree: Improve identifier matchingRichard Henderson
Only argument set members have to be C identifiers, everything else gets prefixed during conversion to C. Some places just checked the leading character, and some places matched a leading character plus a C identifier. Convert everything to match full identifiers, including the [&%@&] prefix, and drop the full C identifier requirement. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903192334.1603773-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/timer/armv7m_systick: assert that board code set system_clock_scalePeter Maydell
It is the responsibility of board code for an armv7m system to set system_clock_scale appropriately for the CPU speed of the core. If it forgets to do this, then QEMU will hang if the guest tries to use the systick timer in the "tick at the CPU clock frequency" mode. We forgot that in a couple of our boards (see commits ce4f70e81ed23c93f, e7e5a9595ab1136). Add an assertion in the systick reset method so we don't let any new boards in with the same bug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200825160847.18091-1-peter.maydell@linaro.org
2020-09-14hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)Philippe Mathieu-Daudé
Report unimplemented register accesses using qemu_log_mask(UNIMP). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200901144100.116742-5-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fieldsPhilippe Mathieu-Daudé
This model implementation is designed for 32-bit accesses. We can simplify setting the MemoryRegionOps::impl min/max fields to 32-bit (memory::access_with_adjusted_size() will take care of the 8/16-bit accesses). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200901144100.116742-4-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fieldsPhilippe Mathieu-Daudé
Per the datasheet (DDI0407 r2p0): "All SCU registers are byte accessible" and are 32-bit aligned. Set MemoryRegionOps::valid min/max fields and simplify the write() handler. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200901144100.116742-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/misc/a9scu: Do not allow invalid CPU countPhilippe Mathieu-Daudé
Per the datasheet (DDI0407 r2p0): "The SCU connects one to four Cortex-A9 processors to the memory system through the AXI interfaces." Change the instance_init() handler to a device_realize() one so we can verify the property is in range, and return an error to the caller if not. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200901144100.116742-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' ↵Peter Maydell
into staging EDK2 firmware: Adopt the edk2-stable202008 release Note from Laszlo Ersek [1] while addressing LP#1852196 [2]: Consume the following upstream edk2 releases: https://github.com/tianocore/edk2/releases/tag/edk2-stable201908 https://github.com/tianocore/edk2/releases/tag/edk2-stable201911 https://github.com/tianocore/edk2/releases/tag/edk2-stable202002 https://github.com/tianocore/edk2/releases/tag/edk2-stable202005 https://github.com/tianocore/edk2/releases/tag/edk2-stable202008 Worth mentioning (in random order): - various CVE fixes (see [2] and shortlog) - OpenSSL-1.1.1g - UEFI HTTPS Boot for ARM/AARCH64 - TPM2 for ARM/AARCH64 - VCPU hotplug with SMI - support for Linux v5.7+ initrd and mixed mode loading - Fusion-MPT SCSI driver in OVMF - VMware PVSCSI driver in OVMF - PXEv4 / PXEv6 boot possible to disable on the QEMU command line - SEV-ES support The IA32 and X64 binaries are now smaller -- the reason is that Laszlo built them with DevToolSet 9 (gcc-9) on RHEL7, and so this is the first time they've undergone LTO (with the GCC5 edk2 toolchain settings). CI jobs results: https://gitlab.com/philmd/qemu/-/pipelines/189394120 https://travis-ci.org/github/philmd/qemu/builds/726842542 https://app.shippable.com/github/philmd/qemu/runs/866/summary/console [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg738173.html [2] https://bugs.launchpad.net/qemu/+bug/1852196 # gpg: Signature made Mon 14 Sep 2020 08:15:37 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/edk2-next-20200914: tests: acpi: update "virt/SSDT.memhp" for edk2-stable202008 pc-bios: update the README file with edk2-stable202008 information pc-bios: refresh edk2 build artifacts for edk2-stable202008 roms/Makefile.edk2: enable new ARM/AARCH64 flags up to edk2-stable202008 roms/Makefile.edk2: complete replacing TPM2*_ENABLE macros roms/edk2: update submodule from edk2-stable201905 to edk2-stable202008 tests: acpi: tolerate "virt/SSDT.memhp" mismatch temporarily roms/Makefile.edk2: prepare for replacing TPM2*_ENABLE macros roms/efirom, tests/uefi-test-tools: update edk2's own submodules first Makefile: remove obsolete edk2 exception from "clean" rule Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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