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2023-03-01target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()Bin Meng
Since commit 94452ac4cf26 ("target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml") the 3 FPU CSRs are removed from the XML target decription. The original intent of that commit was based on the assumption that the 3 FPU CSRs will show up in the riscv-csr.xml so the ones in riscv-*-fpu.xml are redundant. But unforuantely that is not true. As the FPU CSR predicate() has a run-time check on MSTATUS.FS, at the time when CSR XML is generated MSTATUS.FS is unset, hence no FPU CSRs will be reported. The FPU CSR predicate() already considered such a case of being accessed by a debugger. All we need to do is to turn on debugger mode before calling predicate(). Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-12-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64Bin Meng
At present the odd-numbered PMP configuration registers for RV64 are reported in the CSR XML by QEMU gdbstub. However these registers do not exist on RV64 so trying to access them from gdb results in 'E14'. Move the pmpcfgX index check from the actual read/write routine to the PMP CSR predicate() routine, so that non-existent pmpcfgX won't be reported in the CSR XML for RV64. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-11-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Simplify getting RISCVCPU pointer from envBin Meng
Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-10-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Simplify {read, write}_pmpcfg() a little bitBin Meng
Use the register index that has already been calculated in the pmpcfg_csr_{read,write} call. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-9-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Use 'bool' type for read_onlyBin Meng
The read_only variable is currently declared as an 'int', but it should really be a 'bool'. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-8-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Coding style fixes in csr.cBin Meng
Fix various places that violate QEMU coding style: - correct multi-line comment format - indent to opening parenthesis Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-7-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabledBin Meng
There is no need to generate the CSR XML if the Zicsr extension is not enabled. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-6-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: gdbstub: Minor change for better readabilityBin Meng
Use a variable 'base_reg' to represent cs->gdb_num_regs so that the call to ricsv_gen_dynamic_vector_xml() can be placed in one single line for better readability. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-5-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Use g_assert() for the predicate() NULL checkBin Meng
At present riscv_csrrw_check() checks the CSR predicate() against NULL and throws RISCV_EXCP_ILLEGAL_INST if it is NULL. But this is a pure software check, and has nothing to do with the emulation of the hardware behavior, thus it is inappropriate to return illegal instruction exception when software forgets to install the hook. Change to use g_assert() instead. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Message-ID: <20230228104035.1879882-4-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Add some comments to clarify the priority policy of ↵Bin Meng
riscv_csrrw_check() The priority policy of riscv_csrrw_check() was once adjusted in commit eacaf4401956 ("target/riscv: Fix priority of csr related check in riscv_csrrw_check") whose commit message says the CSR existence check should come before the access control check, but the code changes did not agree with the commit message, that the predicate() check actually came after the read / write check. In fact this was intentional. Add some comments there so that people won't bother trying to change it without a solid reason. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Message-ID: <20230228104035.1879882-3-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: gdbstub: Check priv spec version before reporting CSRBin Meng
The gdbstub CSR XML is dynamically generated according to the result of the CSR predicate() result. This has been working fine until commit 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") introduced the privilege spec version check in riscv_csrrw_check(). When debugging the 'sifive_u' machine whose priv spec is at 1.10, gdbstub reports priv spec 1.12 CSRs like menvcfg in the XML, hence we see "remote failure reply 'E14'" message when examining all CSRs via "info register system" from gdb. Add the priv spec version check in the CSR XML generation logic to fix this issue. Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-2-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01Merge patch series "target/riscv: Some updates to float point related ↵Palmer Dabbelt
extensions" RISC-V defines a handful of extensions related to floating point, along with various relationships between these and other extensions. This patch set adds support for the Zvfh, Zvhfmin, and Zve64d extensions; along with a handful of fixes and cleanups related to the other floating-point extension relationships. * b4-shazam-merge target/riscv: Expose properties for Zv* extensions target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc target/riscv: Fix check for vector load/store instructions when EEW=64 target/riscv: Add support for Zvfh/zvfhmin extensions target/riscv: Remove rebundunt check for zve32f and zve64f target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc target/riscv: Simplify check for Zve32f and Zve64f target/riscv: Indent fixes in cpu.c target/riscv: Add propertie check for Zvfh{min} extensions target/riscv: Fix relationship between V, Zve*, F and D target/riscv: Add cfg properties for Zv* extensions target/riscv: Simplify the check for Zfhmin and Zhinxmin target/riscv: Fix the relationship between Zhinxmin and Zhinx target/riscv: Fix the relationship between Zfhmin and Zfh Message-ID: <20230215020539.4788-1-liweiwei@iscas.ac.cn> [Palmer: commit text] Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01Merge patch series "make write_misa a no-op and FEATURE_* cleanups"Palmer Dabbelt
Daniel Henrique Barboza <dbarboza@ventanamicro.com> says: The RISCV_FEATURES_* enum and the CPUArchState::features attribute were introduced 4+ years ago, as a way to retrieve the enabled hart features that aren't represented via MISA CSR bits. Time passed on, and RISCVCPUConfig was introduced. With it, we now have a centralized way of reading all hart features that are enabled/disabled by the user and the board. All recent features are reading their correspondent cpu->cfg.X flag. All but the 5 features in the RISCV_FEATURE_* enum. These features are still operating in the same way: set it during riscv_cpu_realize() using their cpu->cfg value, read it using riscv_feature() when needed. There is nothing special about them in comparison with all the other features and extensions to justify this special handling. This series then is doing two things: first we're actually allowing users to write the MISA CSR if they so choose. Then we're deprecate each RISC_FEATURE_* usage until, in patch 11, we remove everything related to it. All 5 existing RISCV_FEATURE_* features will be handled as everyone else. * b4-shazam-merge: target/riscv/cpu: remove CPUArchState::features and friends target/riscv: remove RISCV_FEATURE_MMU hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() target/riscv: remove RISCV_FEATURE_PMP target/riscv: remove RISCV_FEATURE_EPMP target/riscv/cpu.c: error out if EPMP is enabled without PMP target/riscv: remove RISCV_FEATURE_DEBUG target/riscv: allow MISA writes as experimental target/riscv: do not mask unsupported QEMU extensions in write_misa() target/riscv: introduce riscv_cpu_cfg() Message-ID: <20230222185205.355361-1-dbarboza@ventanamicro.com> [Palmer: use the text from the v1] Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Expose properties for Zv* extensionsWeiwei Li
Expose Zve64d,Zvfh,Zvfhmin properties. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-15-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Simplify check for EEW = 64 in trans_rvv.c.incWeiwei Li
Only V extension supports EEW = 64 in these cases: Zve64* extensions don't support EEW = 64 in these cases as commented before the check. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-14-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Fix check for vector load/store instructions when EEW=64Weiwei Li
The V extension supports all vector load and store instructions except the V extension does not support EEW=64 for index values when XLEN=32. (Section 18.3) Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-13-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Add support for Zvfh/zvfhmin extensionsWeiwei Li
Zvfh supports vector float point instructions with SEW = 16 and supports conversions between 8-bit integers and binary16 values. Zvfhmin supports vfwcvt.f.f.v and vfncvt.f.f.w instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-12-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Remove redundunt check for zve32f and zve64fWeiwei Li
Require_zve32/64f have been overlapped by require_rvf/require_scale_rvf. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-11-liweiwei@iscas.ac.cn> [Palmer: commit text] Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.incWeiwei Li
Check for Zve32f/Zve64d can overlap check for F/D. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-10-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li
V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-9-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Indent fixes in cpu.cWeiwei Li
Fix indent problems in vector related check. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-8-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Add property check for Zvfh{min} extensionsWeiwei Li
Add check for Zvfh and Zvfhmin. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-7-liweiwei@iscas.ac.cn> [Palmer: commit text] Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Fix relationship between V, Zve*, F and DWeiwei Li
Add dependence chain: * V => Zve64d => Zve64f => Zve32f => F * V => Zve64d => D Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-6-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Add cfg properties for Zv* extensionsWeiwei Li
Add properties for Zve64d,Zvfh,Zvfhmin extensions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-5-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Simplify the check for Zfhmin and ZhinxminWeiwei Li
We needn't check Zfh and Zhinx in these instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-4-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Fix the relationship between Zhinxmin and ZhinxWeiwei Li
Just like zfh and zfhmin, Zhinxmin is part of Zhinx so Zhinxmin will be enabled when Zhinx is enabled. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-3-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Fix the relationship between Zfhmin and ZfhWeiwei Li
Zfhmin is part of Zfh, so Zfhmin will be enabled when Zfh is enabled. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-2-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv/cpu: remove CPUArchState::features and friendsDaniel Henrique Barboza
The attribute is no longer used since we can retrieve all the enabled features in the hart by using cpu->cfg instead. Remove env->feature, riscv_feature() and riscv_set_feature(). We also need to bump vmstate_riscv_cpu version_id and minimal_version_id since 'features' is no longer being migrated. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-11-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza
RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use the flag directly instead. With this change the enum is also removed. It is worth noticing that this enum, and all the RISCV_FEATURES_* that were contained in it, predates the existence of the cpu->cfg object. Today, using cpu->cfg is an easier way to retrieve all the features and extensions enabled in the hart. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-10-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()Daniel Henrique Barboza
Read cpu_ptr->cfg.mmu directly. As a bonus, use cpu_ptr in riscv_isa_string(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-9-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-8-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: remove RISCV_FEATURE_EPMPDaniel Henrique Barboza
RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp flag. Use the flag directly. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-7-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv/cpu.c: error out if EPMP is enabled without PMPDaniel Henrique Barboza
Instead of silently ignoring the EPMP setting if there is no PMP available, error out informing the user that EPMP depends on PMP support: $ ./qemu-system-riscv64 -cpu rv64,pmp=false,x-epmp=true qemu-system-riscv64: Invalid configuration: EPMP requires PMP support This will force users to pick saner options in the QEMU command line. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-6-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza
RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-5-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: allow MISA writes as experimentalDaniel Henrique Barboza
At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, has always been a no-op as well because write_misa() will always exit earlier. This seems to be benign in the majority of cases. Booting an Ubuntu 'virt' guest and logging all the calls to 'write_misa' shows that no writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling RISC-V extensions after the machine is powered on, seems to be a niche use. After discussions in the mailing list, most notably in [1], we reached the consensus that this code is not suited to be exposed to users because it's not well tested, but at the same time removing it is a bit extreme because we would like to fix it, and it's easier to do so with the code available to use instead of fetching it from git log. The approach taken here is to get rid of RISCV_FEATURE_MISA altogether and use a new experimental flag called x-misa-w. The default value is false, meaning that we're keeping the existing behavior of doing nothing if a write_misa() is attempted. As with any existing experimental flag, x-misa-w is also a temporary flag that we need to remove once we fix write_misa(). [1] https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg05092.html Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: do not mask unsupported QEMU extensions in write_misa()Daniel Henrique Barboza
The masking done using env->misa_ext_mask already filters any extension that QEMU doesn't support. If the hart supports the extension then QEMU supports it as well. If the masking done by env->misa_ext_mask is somehow letting unsupported QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230222185205.355361-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: introduce riscv_cpu_cfg()Daniel Henrique Barboza
We're going to do changes that requires accessing the RISCVCPUConfig struct from the RISCVCPU, having access only to a CPURISCVState 'env' pointer. Add a helper to make the code easier to read. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230222185205.355361-2-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01readline: fix hmp completion issueDongli Zhang
The auto completion does not work in some cases. Case 1. 1. (qemu) info reg 2. Press 'Tab'. 3. It does not auto complete. Case 2. 1. (qemu) block_resize flo 2. Press 'Tab'. 3. It does not auto complete 'floppy0'. Since the readline_add_completion_of() may add any completion when strlen(pfx) is zero, we remove the check with (name[0] == '\0') because strlen() always returns zero in that case. Fixes: 52f50b1e9f8f ("readline: Extract readline_add_completion_of() from monitor") Cc: Joe Jin <joe.jin@oracle.com> Signed-off-by: Dongli Zhang <dongli.zhang@oracle.com> Message-Id: <20230207045241.8843-1-dongli.zhang@oracle.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2023-03-01Merge tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell
helper-head: Add fpu/softfloat-types.h softmmu: Use memmove in flatview_write_continue tcg: Add sign param to probe_access_flags, probe_access_full tcg: Convert TARGET_TB_PCREL to CF_PCREL tcg: Simplify temporary lifetimes for translators # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmP/jWUdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9TcQf7B7+K/lrWvUVhZ4By # 7zrNIJKGwsxuQhGq9mS2Nx9ds9es5mS8SQT1ieNG6a51n6Gq8S2B8yFCRFdlDZWD # /QrMSjxrs+4c6pNHZu4v20Huy/VW0y004eYdGc8Lu5cXTDpy1mUZ2PrZYlWNQEVY # 4Ts5rTWdSZHRU1+dbB8MTWlml9//++TPB+ZvzqSb8jnRJfw4z7ijVJjUEEb93gQg # 8S3JiPU6d1ZzoXzGMK7Wd0MMi4pQUZkaX1HOpzvmQXjeErSP87CZvvji/Cucm8iW # rJ4U7t99nmZDqG9W1zdZfYfKNp4nLlfVldQWFVIx45awSPS0mCzrmeBT5NHyrxYK # 4OtuNQ== # =vzqE # -----END PGP SIGNATURE----- # gpg: Signature made Wed 01 Mar 2023 17:37:41 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu: (62 commits) tcg: Update docs/devel/tcg-ops.rst for temporary changes tcg: Remove tcg_temp_local_new_*, tcg_const_local_* exec/gen-icount: Don't use tcg_temp_local_new_i32 target/xtensa: Don't use tcg_temp_local_new_* target/ppc: Don't use tcg_temp_local_new target/mips: Don't use tcg_temp_local_new target/i386: Don't use tcg_temp_local_new target/hppa: Don't use tcg_temp_local_new target/hexagon/idef-parser: Drop gen_tmp_local target/hexagon: Don't use tcg_temp_local_new_* target/cris: Don't use tcg_temp_local_new target/arm: Don't use tcg_temp_local_new_* target/arm: Drop copies in gen_sve_{ldr,str} tcg: Change default temp lifetime to TEMP_TB tcg: Don't re-use TEMP_TB temporaries accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers accel/tcg/plugin: Use tcg_temp_ebb_* tcg: Use tcg_constant_ptr in do_dup tcg: Use tcg_temp_ebb_new_* in tcg/ tcg: Add tcg_temp_ebb_new_{i32,i64,ptr} ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-01bsd-user: implement sysctlbyname(2)Kyle Evans
do_freebsd_sysctlbyname needs to translate the 'name' back down to a OID so we can intercept the special ones. Do that and call the common wrapper do_freebsd_sysctl_oid. Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01bsd-user: do_freebsd_sysctl helper for sysctl(2)Kyle Evans
Implement the wrapper function for sysctl(2). This puts the oid arguments into a standard form and calls the common do_freebsd_sysctl_oid. Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Co-Authored-by: Juergen Lock <nox@jelal.kn-bremen.de> Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Co-Authored-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Stacey Son <sson@FreeBSD.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01bsd-user: Start translation of arch-specific sysctlsJuergen Lock
Intercept some syscalls that we need to translate (like the archiecture we're running on) and translate them. These are only the simplest ones so far. Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Co-Authored-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Stacey Son <sson@FreeBSD.org> Co-Authored-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01bsd-user: common routine do_freebsd_sysctl_oid for all sysctl variantsJuergen Lock
do_freebsd_sysctl_oid filters out some of the binary and special sysctls where host != target. None of the sysctls that have to be translated from host to target are handled here. Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Co-Authored-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Stacey Son <sson@FreeBSD.org> Co-Authored-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01bsd-user: sysctl helper funtions: sysctl_name2oid and sysctl_oidfmtJuergen Lock
Helper functions for sysctl implementations. sysctl_name2oid and sysctl_oidfmt convert oids between host and targets Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01bsd-user: Helper routines oidfmtStacey Son
oidfmt uses undocumented system call to get the type of the sysctl. Co-Authored-by: Sean Bruno <sbruno@FreeBSD.org> Signed-off-by: Sean Bruno <sbruno@FreeBSD.org> Co-Authored-by: Juergen Lock <nox@jelal.kn-bremen.de> Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Co-Authored-by: Raphael Kubo da Costa <rakuco@FreeBSD.org> Signed-off-by: Raphael Kubo da Costa <rakuco@FreeBSD.org> Signed-off-by: Stacey Son <sson@FreeBSD.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01bsd-user: various helper routines for sysctlWarner Losh
cap_memory - Caps the memory to just below MAXINT scale_to_guest_pages - Account for difference in host / guest page size h2g_long_sat - converts a int64_t to a int32_t, saturating at max / min values h2g_ulong_sat - converts a uint64_t to a uint32_t, saturating at max value Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01bsd-user: Add sysarch syscallStacey Son
Connect up the sysarch system call. Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Co-authored-by: Juergen Lock <nox@jelal.kn-bremen.de> Signed-off-by: Stacey Son <sson@FreeBSD.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01build: Don't specify -no-pie for --static user-mode programsWarner Losh
When building with clang, -no-pie gives a warning on every single build, so remove it. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2023-03-01bsd-user: Don't truncate the return value from freebsd_syscallDoug Rabson
System call return values on FreeBSD are in a register (which is spelled abi_long in qemu). This was being assigned into an int variable which causes problems for 64bit targets. Resolves: https://github.com/qemu-bsd-user/qemu-bsd-user/issues/40 Signed-off-by: Doug Rabson <dfr@rabson.org> Reviewed-by: Warner Losh <imp@bsdimp.com> [ Edited commit message for upstreaming into qemu-project ] Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01tcg: Update docs/devel/tcg-ops.rst for temporary changesRichard Henderson
Rewrite the sections which talked about 'local temporaries'. Remove some assumptions which no longer hold. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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