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AgeCommit message (Expand)Author
2014-04-18tcg-s390: Remove W constraintRichard Henderson
2014-04-18tcg-sparc: Use the type parameter to tcg_target_const_matchRichard Henderson
2014-04-18tcg-ppc64: Use the type parameter to tcg_target_const_matchRichard Henderson
2014-04-18tcg-aarch64: Remove w constraintRichard Henderson
2014-04-18tcg: Add TCGType parameter to tcg_target_const_matchRichard Henderson
2014-04-18tcg: Fix out of range shift in deposit optimizationsRichard Henderson
2014-04-18tci: Mask shift counts to avoid undefined behaviorRichard Henderson
2014-04-18tcg: Mask shift quantities while foldingRichard Henderson
2014-04-18tcg: Use "unspecified behavior" for shiftsRichard Henderson
2014-04-18tcg: Fix warning (1 bit signed bitfield entry) and replace int by boolStefan Weil
2014-04-17Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140417-...Peter Maydell
2014-04-17target-arm: A64: fix unallocated test of scalar SQXTUNAlex Bennée
2014-04-17arm: translate.c: Fix smlald InstructionPeter Crosthwaite
2014-04-17net: cadence_gem: Make phy respond to broadcastPeter Crosthwaite
2014-04-17misc: zynq_slcr: Make DB_PRINTs always compilePeter Crosthwaite
2014-04-17misc: zynq_slcr: Convert SBD::init to object initPeter Crosthwaite
2014-04-17misc: zynq-slcr: RewritePeter Crosthwaite
2014-04-17allwinner-emac: update irq status after writes to interrupt registersBeniamino Galvani
2014-04-17allwinner-emac: set autonegotiation complete bit on link upBeniamino Galvani
2014-04-17allwinner-a10-pit: implement prescaler and source selectionBeniamino Galvani
2014-04-17allwinner-a10-pit: use level triggered interruptsBeniamino Galvani
2014-04-17allwinner-a10-pit: avoid generation of spurious interruptsBeniamino Galvani
2014-04-17allwinner-a10-pic: fix behaviour of pending registerBeniamino Galvani
2014-04-17allwinner-a10-pic: set vector address when an interrupt is pendingBeniamino Galvani
2014-04-17timer: cadence_ttc: Fix match register write logicPeter Crosthwaite
2014-04-17target-arm/gdbstub64.c: remove useless 'break' statement.Chen Gang
2014-04-17target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32Peter Maydell
2014-04-17target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pcPeter Maydell
2014-04-17target-arm: Make Cortex-A15 CBAR read-onlyPeter Maydell
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell
2014-04-17target-arm: Implement Cortex-A57 implementation-defined system registersPeter Maydell
2014-04-17target-arm: Implement RVBAR registerPeter Maydell
2014-04-17target-arm: Implement AArch64 address translation operationsPeter Maydell
2014-04-17target-arm: Implement auxiliary fault status registersPeter Maydell
2014-04-17target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8Peter Maydell
2014-04-17target-arm: Don't expose wildcard ID register definitions for ARMv8Peter Maydell
2014-04-17target-arm: Remove THUMB2EE feature from AArch64 'any' CPUPeter Maydell
2014-04-17target-arm: Implement ISR_EL1 registerPeter Maydell
2014-04-17target-arm: Implement AArch64 view of ACTLRPeter Maydell
2014-04-17target-arm: Implement AArch64 view of CONTEXTIDRPeter Maydell
2014-04-17target-arm: Implement AArch64 views of AArch32 ID registersPeter Maydell
2014-04-17target-arm: Add Cortex-A57 processorPeter Maydell
2014-04-17target-arm: Implement ARMv8 MVFR registersPeter Maydell
2014-04-17target-arm: Implement AArch64 EL1 exception handlingRob Herring
2014-04-17target-arm: Move arm_log_exception() into internals.hPeter Maydell
2014-04-17target-arm: Implement AArch64 SPSR_EL1Peter Maydell
2014-04-17target-arm: Implement SP_EL0, SP_EL1Peter Maydell
2014-04-17target-arm: Add AArch64 ELR_EL1 register.Peter Maydell
2014-04-17target-arm: Implement AArch64 views of fault status and data registersRob Herring
2014-04-17target-arm: Use dedicated CPU state fields for ARM946 access bit registersPeter Maydell
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