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2020-03-06qemu-doc: split CPU models doc between MIPS and x86 partsPaolo Bonzini
The MIPS CPU models end up in the middle of the PC documentation. Move them to a separate file so that they can be placed in the right section. The man page still includes both x86 and MIPS content. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200228153619.9906-5-peter.maydell@linaro.org Message-id: 20200226113034.6741-5-pbonzini@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-06texi2pod: parse @include directives outside "@c man" blocksPaolo Bonzini
This enables splitting the huge qemu-doc.texi file and keeping parallel Texinfo and rST versions of the documentation. texi2pod is not going to live much longer and hardly anyone cares about its upstream status, so the temporary fork should be acceptable. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200228153619.9906-4-peter.maydell@linaro.org Message-id: 20200226113034.6741-4-pbonzini@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-06qemu-doc: remove target OS documentationPaolo Bonzini
This section covers OSes up to Windows 2000, and as such it is mostly obsolete. Zap it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200228153619.9906-3-peter.maydell@linaro.org Message-id: 20200226113034.6741-3-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-06qemu-doc: convert user-mode emulation to a separate Sphinx manualPaolo Bonzini
The final addition to the set of QEMU manuals is the user-mode emulation manual, which right now is included in qemu-doc.texi. Extract it and convert it to rST, so that qemu-doc.texi covers only full system emulation. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200228153619.9906-2-peter.maydell@linaro.org Message-id: 20200226113034.6741-2-pbonzini@redhat.com [PMM: Fix makefile conflicts; add user manual to index.rst and index.html.in; don't specify empty man_pages list; fixed a few comments to say 'user' rather than 'system'] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf4' ↵Peter Maydell
into staging A single RISC-V fixup This is just a single patch, which fixes a bug found by Coverity. # gpg: Signature made Thu 05 Mar 2020 20:05:03 GMT # gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 # Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889 * remotes/palmer/tags/riscv-for-master-5.0-sf4: RISC-V: Add a missing "," in riscv_excp_names Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt
This would almost certainly cause the exception names to be reported incorrectly. Coverity found the issue (CID 1420223). As per Peter's suggestion, I've also added a comma at the end of the list to avoid the issue reappearing in the future. Fixes: ab67a1d07a ("target/riscv: Add support for the new execption numbers") Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-05Merge remote-tracking branch ↵Peter Maydell
'remotes/stefanberger/tags/pull-tpm-2020-03-04-2' into staging Merge tpm 2020/03/04 v2 # gpg: Signature made Thu 05 Mar 2020 17:21:05 GMT # gpg: using RSA key B818B9CADF9089C2D5CEC66B75AD65802A0B4211 # gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211 * remotes/stefanberger/tags/pull-tpm-2020-03-04-2: test: tpm-tis: Add Sysbus TPM-TIS device test test: tpm-tis: Get prepared to share tests between ISA and sysbus devices test: tpm: pass optional machine options to swtpm test functions docs/specs/tpm: Document TPM_TIS sysbus device for ARM hw/arm/virt: vTPM support tpm: Add the SysBus TPM TIS device tpm: Separate TPM_TIS and TPM_TIS_ISA configs tpm: Separate tpm_tis common functions from isa code tpm: Use TPMState as a common struct tpm: rename TPM_TIS into TPM_TIS_ISA Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05test: tpm-tis: Add Sysbus TPM-TIS device testEric Auger
The tests themselves are the same as the ISA device ones. Only the main() changes as the "tpm-tis-device" device gets instantiated. Also the base address of the device is not 0xFED40000 anymore but matches the base address of the ARM virt platform bus. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Message-id: 20200305165149.618-11-eric.auger@redhat.com Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2020-03-05test: tpm-tis: Get prepared to share tests between ISA and sysbus devicesEric Auger
ISA and sysbus TPM-TIS devices will share their tests. Only the main() will change (instantiation option is different). Also the base address of the TPM-TIS device is going to be different. on x86 it is located at 0xFED40000 while on ARM it can be located at any location, discovered through the device tree description. So we put shared test functions in a new object module. Each test needs to set tpm_tis_base_addr global variable. Also take benefit of this move to fix "block comments using a leading */ on a separate line" checkpatch warnings. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Message-id: 20200305165149.618-10-eric.auger@redhat.com Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2020-03-05test: tpm: pass optional machine options to swtpm test functionsEric Auger
We plan to use swtpm test functions on ARM for testing the sysbus TPM-TIS device. However on ARM there is no default machine type. So we need to explictly pass some machine options on startup. Let's allow this by adding a new parameter to both swtpm test functions and update all call sites. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Message-id: 20200305165149.618-9-eric.auger@redhat.com Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2020-03-05docs/specs/tpm: Document TPM_TIS sysbus device for ARMEric Auger
Update the documentation with recent changes related to the sysbus TPM_TIS device addition and add the command line to be used with arm VIRT. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Message-id: 20200305165149.618-8-eric.auger@redhat.com Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2020-03-05hw/arm/virt: vTPM supportEric Auger
Let the TPM TIS SYSBUS device be dynamically instantiable in ARM virt. A device tree node is dynamically created (TPM via MMIO). The TPM Physical Presence interface (PPI) is not supported. To run with the swtmp TPM emulator, the qemu command line must be augmented with: -chardev socket,id=chrtpm,path=swtpm-sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm \ -device tpm-tis-device,tpmdev=tpm0 \ swtpm/libtpms command line example: swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \ --ctrl type=unixio,path=swtpm-sock Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 20200305165149.618-7-eric.auger@redhat.com Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2020-03-05tpm: Add the SysBus TPM TIS deviceEric Auger
Introduce the tpm-tis-device which is a sysbus device and is bound to be used on ARM. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 20200305165149.618-6-eric.auger@redhat.com Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2020-03-05tpm: Separate TPM_TIS and TPM_TIS_ISA configsEric Auger
Let's separate the compilation of tpm_tis_common.c from the compilation of tpm_tis_isa.c The common part will be also compiled along with the tpm_tis_sysbus device. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 20200305165149.618-5-eric.auger@redhat.com Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2020-03-05tpm: Separate tpm_tis common functions from isa codeEric Auger
Move the device agnostic code into tpm_tis_common.c and put the ISA device specific code into tpm_tis_isa.c Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 20200305165149.618-4-eric.auger@redhat.com Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2020-03-05tpm: Use TPMState as a common structEric Auger
As we plan to introduce a SysBus TPM TIS device, let's make the TPMState a common struct usable by both the ISADevice and the SysBusDevice. TPMStateISA embeds the struct and inherits from the ISADevice. The prototype of functions bound to be used by both the ISA and SysBus devices is changed to take TPMState handle. A bunch of structs also are renamed to be specialized for the ISA device. Besides those transformations, no functional change is expected. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 20200305165149.618-3-eric.auger@redhat.com Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2020-03-05tpm: rename TPM_TIS into TPM_TIS_ISAEric Auger
As we plan to introduce a sysbus TPM_TIS, let's rename TPM_TIS into TPM_TIS_ISA. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 20200305165149.618-2-eric.auger@redhat.com Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2020-03-05Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200305' into staging * versal: Implement ADMA * Implement (trivially) ARMv8.2-TTCNP * hw/arm/smmu-common: a fix to smmu_find_smmu_pcibus * Remove unnecessary endianness-handling on some boards * Avoid minor memory leaks from timer_new in some devices * Honour more of the HCR_EL2 trap bits * Complain rather than ignoring bad command line options for cubieboard * Honour TBI for DC ZVA and exception return # gpg: Signature made Thu 05 Mar 2020 16:30:17 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200305: (37 commits) target/arm: Clean address for DC ZVA target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva target/arm: Move helper_dc_zva to helper-a64.c target/arm: Apply TBI to ESR_ELx in helper_exception_return target/arm: Introduce core_to_aa64_mmu_idx target/arm: Optimize cpu_mmu_index target/arm: Replicate TBI/TBID bits for single range regimes hw/arm/cubieboard: report error when using unsupported -bios argument hw/arm/cubieboard: restrict allowed RAM size to 512MiB and 1GiB hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8 hw/arm/cubieboard: use ARM Cortex-A8 as the default CPU in machine definition tests/tcg/aarch64: Add newline in pauth-1 printf target/arm: Honor the HCR_EL2.TTLB bit target/arm: Honor the HCR_EL2.TPU bit target/arm: Honor the HCR_EL2.TPCP bit target/arm: Honor the HCR_EL2.TACR bit target/arm: Honor the HCR_EL2.TSW bit target/arm: Honor the HCR_EL2.{TVM,TRVM} bits target/arm: Improve masking in arm_hcr_el2_eff target/arm: Remove EL2 and EL3 setup from user-only ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Clean address for DC ZVARichard Henderson
This data access was forgotten when we added support for cleaning addresses of TBI information. Fixes: 3a471103ac1823ba Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200302175829.2183-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Use DEF_HELPER_FLAGS for helper_dc_zvaRichard Henderson
The function does not write registers, and only reads them by implication via the exception path. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200302175829.2183-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Move helper_dc_zva to helper-a64.cRichard Henderson
This is an aarch64-only function. Move it out of the shared file. This patch is code movement only. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200302175829.2183-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Apply TBI to ESR_ELx in helper_exception_returnRichard Henderson
We missed this case within AArch64.ExceptionReturn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200302175829.2183-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Introduce core_to_aa64_mmu_idxRichard Henderson
If by context we know that we're in AArch64 mode, we need not test for M-profile when reconstructing the full ARMMMUIdx. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200302175829.2183-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Optimize cpu_mmu_indexRichard Henderson
We now cache the core mmu_idx in env->hflags. Rather than recompute from scratch, extract the field. All of the uses of cpu_mmu_index within target/arm are within helpers, and env->hflags is always stable within a translation block from whence helpers are called. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200302175829.2183-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Replicate TBI/TBID bits for single range regimesRichard Henderson
Replicate the single TBI bit from TCR_EL2 and TCR_EL3 so that we can unconditionally use pointer bit 55 to index into our composite TBI1:TBI0 field. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200302175829.2183-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/cubieboard: report error when using unsupported -bios argumentNiek Linnenbank
The Cubieboard machine does not support the -bios argument. Report an error when -bios is used and exit immediately. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200227220149.6845-5-nieklinnenbank@gmail.com Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/cubieboard: restrict allowed RAM size to 512MiB and 1GiBNiek Linnenbank
The Cubieboard contains either 512MiB or 1GiB of onboard RAM [1]. Prevent changing RAM to a different size which could break user programs. [1] http://linux-sunxi.org/Cubieboard Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200227220149.6845-4-nieklinnenbank@gmail.com Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8Niek Linnenbank
The Cubieboard has an ARM Cortex-A8. Instead of simply ignoring a bogus -cpu option provided by the user, give them an error message so they know their command line is wrong. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200227220149.6845-3-nieklinnenbank@gmail.com Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/cubieboard: use ARM Cortex-A8 as the default CPU in machine definitionNiek Linnenbank
The Cubieboard is a singleboard computer with an Allwinner A10 System-on-Chip [1]. As documented in the Allwinner A10 User Manual V1.5 [2], the SoC has an ARM Cortex-A8 processor. Currently the Cubieboard machine definition specifies the ARM Cortex-A9 in its description and as the default CPU. This patch corrects the Cubieboard machine definition to use the ARM Cortex-A8. The only user-visible effect is that our textual description of the machine was wrong, because hw/arm/allwinner-a10.c always creates a Cortex-A8 CPU regardless of the default value in the MachineClass struct. [1] http://docs.cubieboard.org/products/start#cubieboard1 [2] https://linux-sunxi.org/File:Allwinner_A10_User_manual_V1.5.pdf Fixes: 8a863c8120994981a099 Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200227220149.6845-2-nieklinnenbank@gmail.com Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [note in commit message that the bug didn't have much visible effect] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05tests/tcg/aarch64: Add newline in pauth-1 printfRichard Henderson
Make the output just a bit prettier when running by hand. Cc: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-13-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Honor the HCR_EL2.TTLB bitRichard Henderson
This bit traps EL1 access to tlb maintenance insns. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Honor the HCR_EL2.TPU bitRichard Henderson
This bit traps EL1 access to cache maintenance insns that operate to the point of unification. There are no longer any references to plain aa64_cacheop_access, so remove it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Honor the HCR_EL2.TPCP bitRichard Henderson
This bit traps EL1 access to cache maintenance insns that operate to the point of coherency or persistence. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Honor the HCR_EL2.TACR bitRichard Henderson
This bit traps EL1 access to the auxiliary control registers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Honor the HCR_EL2.TSW bitRichard Henderson
These bits trap EL1 access to set/way cache maintenance insns. Buglink: https://bugs.launchpad.net/bugs/1863685 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Honor the HCR_EL2.{TVM,TRVM} bitsRichard Henderson
These bits trap EL1 access to various virtual memory controls. Buglink: https://bugs.launchpad.net/bugs/1855072 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Improve masking in arm_hcr_el2_effRichard Henderson
Update the {TGE,E2H} == '11' masking to ARMv8.6. If EL2 is configured for aarch32, disable all of the bits that are RES0 in aarch32 mode. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Remove EL2 and EL3 setup from user-onlyRichard Henderson
We have disabled EL2 and EL3 for user-only, which means that these registers "don't exist" and should not be set. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Disable has_el2 and has_el3 for user-onlyRichard Henderson
In arm_cpu_reset, we configure many system registers so that user-only behaves as it should with a minimum of ifdefs. However, we do not set all of the system registers as required for a cpu with EL2 and EL3. Disabling EL2 and EL3 mean that we will not look at those registers, which means that we don't have to worry about configuring them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Add HCR_EL2 bit definitions from ARMv8.6Richard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05target/arm: Improve masking of HCR/HCR2 RES0 bitsRichard Henderson
Don't merely start with v8.0, handle v7VE as well. Ensure that writes from aarch32 mode do not change bits in the other half of the register. Protect reads of aa64 id registers with ARM_FEATURE_AARCH64. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/timer/cadence_ttc: move timer_new from init() into realize() to avoid ↵Pan Nengyuan
memleaks There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200227025055.14341-7-pannengyuan@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/strongarm: move timer_new from init() into realize() to avoid memleaksPan Nengyuan
There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com> Message-id: 20200227025055.14341-5-pannengyuan@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/spitz: move timer_new from init() into realize() to avoid memleaksPan Nengyuan
There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com> Message-id: 20200227025055.14341-4-pannengyuan@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/pxa2xx: move timer_new from init() into realize() to avoid memleaksPan Nengyuan
There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com> Message-id: 20200227025055.14341-3-pannengyuan@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/musicpal: Simplify since the machines are little-endian onlyPhilippe Mathieu-Daudé
We only build the little-endian softmmu configurations. Checking for big endian is pointless, remove the unused code. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/z2: Simplify since the machines are little-endian onlyPhilippe Mathieu-Daudé
We only build the little-endian softmmu configurations. Checking for big endian is pointless, remove the unused code. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/omap_sx1: Simplify since the machines are little-endian onlyPhilippe Mathieu-Daudé
We only build the little-endian softmmu configurations. Checking for big endian is pointless, remove the unused code. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/mainstone: Simplify since the machines are little-endian onlyPhilippe Mathieu-Daudé
We only build the little-endian softmmu configurations. Checking for big endian is pointless, remove the unused code. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-05hw/arm/gumstix: Simplify since the machines are little-endian onlyPhilippe Mathieu-Daudé
As the Connex and Verdex machines only boot in little-endian, we can simplify the code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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