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2018-05-18target/mips: Honor CPU_DUMP_FPURichard Henderson
Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-18target/alpha: Honor CPU_DUMP_FPURichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-18Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20180518' into staging target-arm queue: * Initial part of SVE implementation (currently disabled) * smmuv3: fix some minor Coverity issues * add model of Xilinx ZynqMP generic DMA controller * expose (most) Arm coprocessor/system registers to gdb via QEMU's gdbstub, for reads only # gpg: Signature made Fri 18 May 2018 18:18:27 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180518: (32 commits) target/arm: Implement SVE Permute - Extract Group target/arm: Implement SVE Integer Wide Immediate - Predicated Group target/arm: Implement SVE Bitwise Immediate Group target/arm: Implement SVE Element Count Group target/arm: Implement SVE floating-point trig select coefficient target/arm: Implement SVE floating-point exponential accelerator target/arm: Implement SVE Compute Vector Address Group target/arm: Implement SVE Bitwise Shift - Unpredicated Group target/arm: Implement SVE Stack Allocation Group target/arm: Implement SVE Index Generation Group target/arm: Implement SVE Integer Arithmetic - Unpredicated Group target/arm: Implement SVE Integer Multiply-Add Group target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group target/arm: Implement SVE bitwise shift by wide elements (predicated) target/arm: Implement SVE bitwise shift by vector (predicated) target/arm: Implement SVE bitwise shift by immediate (predicated) target/arm: Implement SVE Integer Reduction Group target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group target/arm: Implement SVE Predicate Misc Group target/arm: Implement SVE Predicate Logical Operations Group ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Permute - Extract GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Integer Wide Immediate - Predicated GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Bitwise Immediate GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Element Count GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE floating-point trig select coefficientRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE floating-point exponential acceleratorRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Compute Vector Address GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Bitwise Shift - Unpredicated GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Stack Allocation GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Index Generation GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Integer Arithmetic - Unpredicated GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Integer Multiply-Add GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Integer Arithmetic - Unary Predicated GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE bitwise shift by wide elements (predicated)Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE bitwise shift by vector (predicated)Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE bitwise shift by immediate (predicated)Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Integer Reduction GroupRichard Henderson
Excepting MOVPRFX, which isn't a reduction. Presumably it is placed within the group because of its encoding. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Integer Binary Arithmetic - Predicated GroupRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Predicate Misc GroupRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Predicate Logical Operations GroupRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE predicate testRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE load vector/predicateRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Implement SVE Bitwise Logical - Unpredicated GroupRichard Henderson
These were the instructions that were stubbed out when introducing the decode skeleton. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Add SVE decode skeletonRichard Henderson
Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Introduce translate-a64.hRichard Henderson
Move some stuff that will be common to both translate-a64.c and translate-sve.c. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18hw/arm/smmu-common: Fix coverity issue in get_block_pte_addressEric Auger
Coverity points out that this can overflow if n > 31, because it's only doing 32-bit arithmetic. Let's use 1ULL instead of 1. Also the formulae used to compute n can be replaced by the level_shift() macro. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1526493784-25328-3-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18hw/arm/smmuv3: Fix Coverity issue in smmuv3_record_eventEric Auger
Coverity complains about use of uninitialized Evt struct. The EVT_SET_TYPE and similar setters use deposit32() on fields in the struct, so they read the uninitialized existing values. In cases where we don't set all the fields in the event struct we'll end up leaking random uninitialized data from QEMU's stack into the guest. Initializing the struct with "Evt evt = {};" ought to satisfy Coverity and fix the data leak. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reported-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1526493784-25328-2-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18xlnx-zynqmp: Connect the ZynqMP GDMA and ADMAFrancisco Iglesias
The ZynqMP contains two instances of a generic DMA, the GDMA, located in the FPD (full power domain), and the ADMA, located in LPD (low power domain). This patch adds these two DMAs to the ZynqMP board. Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20180503214201.29082-3-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMAFrancisco Iglesias
Add a model of the generic DMA found on Xilinx ZynqMP. Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20180503214201.29082-2-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Add the XML dynamic generationAbdallah Bouassida
Generate an XML description for the cp-regs. Register these regs with the gdb_register_coprocessor(). Add arm_gdb_get_sysreg() to use it as a callback to read those regs. Add a dummy arm_gdb_set_sysreg(). Signed-off-by: Abdallah Bouassida <abdallah.bouassida@lauterbach.com> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1524153386-3550-4-git-send-email-abdallah.bouassida@lauterbach.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Add "_S" suffix to the secure version of a sysregAbdallah Bouassida
This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. Add "_S" suffix to the secure version of sysregs that have both S and NS views Replace (S) and (NS) by _S and _NS for the register that are manually defined, so all the registers follow the same convention. Signed-off-by: Abdallah Bouassida <abdallah.bouassida@lauterbach.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1524153386-3550-3-git-send-email-abdallah.bouassida@lauterbach.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo typeAbdallah Bouassida
This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. A register has ARM_CP_NO_GDB enabled will not be shown in the dynamic XML. This bit is enabled automatically when creating CP_ANY wildcard aliases. This bit could be enabled manually for any register we want to remove from the dynamic XML description. Signed-off-by: Abdallah Bouassida <abdallah.bouassida@lauterbach.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1524153386-3550-2-git-send-email-abdallah.bouassida@lauterbach.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18Merge remote-tracking branch ↵Peter Maydell
'remotes/famz/tags/docker-and-block-pull-request' into staging Docker and block patches Two fairly small fixes. # gpg: Signature made Fri 18 May 2018 10:17:06 BST # gpg: using RSA key CA35624C6A9171C6 # gpg: Good signature from "Fam Zheng <famz@redhat.com>" # Primary key fingerprint: 5003 7CB7 9706 0F76 F021 AD56 CA35 624C 6A91 71C6 * remotes/famz/tags/docker-and-block-pull-request: iothread: fix epollfd leak in the process of delIOThread docker: Fix trivial typo Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180518-pull-request' ↵Peter Maydell
into staging usb: two smartcard reader fixes. # gpg: Signature made Fri 18 May 2018 08:50:01 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20180518-pull-request: hw/usb/dev-smartcard-reader: Handle 64 B USB packets ccid-card-passthru: fix regression in realize() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18Merge remote-tracking branch 'remotes/kraxel/tags/ui-20180518-pull-request' ↵Peter Maydell
into staging ui: bugfixes, move x11 dependency to modules. # gpg: Signature made Fri 18 May 2018 08:40:41 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20180518-pull-request: sdl: Move use of surface pointer below check for whether it is NULL ui: add x_keymap.o to modules console: Avoid segfault in screendump Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18Merge remote-tracking branch 'remotes/rth/tags/pull-fpu-20180517' into stagingPeter Maydell
Roundup of softfloat patches # gpg: Signature made Thu 17 May 2018 23:44:04 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-fpu-20180517: (28 commits) fpu/softfloat: Define floatN_silence_nan in terms of parts_silence_nan fpu/softfloat: Clean up parts_default_nan fpu/softfloat: Define floatN_default_nan in terms of parts_default_nan fpu/softfloat: Pass FloatClass to pickNaNMulAdd fpu/softfloat: Pass FloatClass to pickNaN fpu/softfloat: Make is_nan et al available to softfloat-specialize.h fpu/softfloat: Specialize on snan_bit_is_one fpu/softfloat: Remove floatX_maybe_silence_nan fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN target/s390x: Remove floatX_maybe_silence_nan from conversions target/riscv: Remove floatX_maybe_silence_nan from conversions target/mips: Remove floatX_maybe_silence_nan from conversions target/m68k: Use floatX_silence_nan when we have already checked for SNaN target/hppa: Remove floatX_maybe_silence_nan from conversions target/arm: Remove floatX_maybe_silence_nan from conversions target/arm: Use floatX_silence_nan when we have already checked for SNaN fpu/softfloat: re-factor float to float conversions fpu/softfloat: Partial support for ARM Alternative half-precision target/arm: squash FZ16 behaviour for conversions target/arm: convert conversion helpers to fpst/ahp_flag ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18iothread: fix epollfd leak in the process of delIOThreadJie Wang
When we call addIOThread, the epollfd created in aio_context_setup, but not close it in the process of delIOThread, so the epollfd will leak. Reorder the code in aio_epoll_disable and reuse it. Signed-off-by: Jie Wang <wangjie88@huawei.com> Message-Id: <1526517763-11108-1-git-send-email-wangjie88@huawei.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> [Mention change to aio_epoll_disable in commit message. - Fam] Signed-off-by: Fam Zheng <famz@redhat.com>
2018-05-18docker: Fix trivial typoPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180508144358.13530-1-f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-05-18hw/usb/dev-smartcard-reader: Handle 64 B USB packetsJakub Jelen
The current code was not correctly handling 64 B (Max USB 1.1 payload size) packets and therefore preventing some of the messages from smart card to pass through to the guest. If the smart card in host responded with 34 B of data in APDU layer, the CCID headers added up to 64 B. The packet was send, but not correctly committed per USB specification (8.5.3.2 Variable-length Data Stage): > When all of the data structure is returned to the host, the function > should indicate that the Data stage is ended by returning a packet > that is shorter than the MaxPacketSize for the pipe. If the data > structure is an exact multiple of wMaxPacketSize for the pipe, the > function will return a zero-length packet to indicate the end of the > Data stage. This lead the guest applications to timeout while waiting for the rest of data (the emulation layer is answering with NAK until the timeout). This patch is checking the current maximum packet size and if the payload of this size is detected, the message buffer is not yet released. With the next call, the empty buffer is sent and the message buffer is finally released. Signed-off-by: Jakub Jelen <jjelen@redhat.com> Message-id: 20180516115544.3897-2-jjelen@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-05-18ccid-card-passthru: fix regression in realize()Marc-André Lureau
Since cc847bfd16d894fd8c1a2ce25f31772f6cdbbc74, CCID card-passthru fails to intialize, because it changed a debug line to an error, probably by mistake. Change it back to a DPRINTF debug. (solves Boxes creating VM with smartcard passthru failing to start) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180515153039.27514-1-marcandre.lureau@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-05-18sdl: Move use of surface pointer below check for whether it is NULLPeter Maydell
In commit 2ab858c6c38ee1 we added a use of the 'surf' variable in sdl2_2d_update() that was unfortunately placed above the early-exit-if-NULL check. Move it to where it ought to be. Fixes: Coverity CID 1390598 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180515185814.1374-1-peter.maydell@linaro.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-05-18ui: add x_keymap.o to modulesPaolo Bonzini
x_keymap.o is common to the SDL and GTK+ modules, and it causes the QEMU binary to link to the X11 libraries. Add it separately to the modules to keep the main QEMU binary smaller. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1526560782-18732-1-git-send-email-pbonzini@redhat.com [ kraxel: fix lm32 target build (milkymist-tmu2) ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-05-18console: Avoid segfault in screendumpMichal Privoznik
After f771c5440e04626f1 it is possible to select device and head which to take screendump from. And even though we check if provided head number falls within range, it may still happen that the console has no surface yet leading to SIGSEGV: qemu.git $ ./x86_64-softmmu/qemu-system-x86_64 \ -qmp stdio \ -device virtio-vga,id=video0,max_outputs=4 {"execute":"qmp_capabilities"} {"execute":"screendump", "arguments":{"filename":"/tmp/screen.ppm", "device":"video0", "head":1}} Segmentation fault #0 0x00005628249dda88 in ppm_save (filename=0x56282826cbc0 "/tmp/screen.ppm", ds=0x0, errp=0x7fff52a6fae0) at ui/console.c:304 #1 0x00005628249ddd9b in qmp_screendump (filename=0x56282826cbc0 "/tmp/screen.ppm", has_device=true, device=0x5628276902d0 "video0", has_head=true, head=1, errp=0x7fff52a6fae0) at ui/console.c:375 #2 0x00005628247740df in qmp_marshal_screendump (args=0x562828265e00, ret=0x7fff52a6fb68, errp=0x7fff52a6fb60) at qapi/qapi-commands-ui.c:110 Here, @ds from frame #0 (or @surface from frame #1) is dereferenced at the very beginning of ppm_save(). And because it's NULL crash happens. Signed-off-by: Michal Privoznik <mprivozn@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: cb05bb1909daa6ba62145c0194aafa05a14ed3d1.1526569138.git.mprivozn@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-05-17fpu/softfloat: Define floatN_silence_nan in terms of parts_silence_nanRichard Henderson
Isolate the target-specific choice to 3 functions instead of 6. The code in floatx80_default_nan tried to be over-general. There are only two targets that support this format: x86 and m68k. Thus there is no point in inventing a mechanism for snan_bit_is_one. Move routines that no longer have ifdefs out of softfloat-specialize.h. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17fpu/softfloat: Clean up parts_default_nanRichard Henderson
Reduce the number of ifdefs. Correct the result for OpenRISC and TriCore (although TriCore fixed in target-specific code). Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17fpu/softfloat: Define floatN_default_nan in terms of parts_default_nanRichard Henderson
Isolate the target-specific choice to 2 functions instead of 6. The code in float16_default_nan was only correct for ARM, MIPS, and X86. Though float16 support is rare among our targets. The code in float128_default_nan was arguably wrong for Sparc. While QEMU supports the Sparc 128-bit insns, no real cpu enables it. The code in floatx80_default_nan tried to be over-general. There are only two targets that support this format: x86 and m68k. Thus there is no point in inventing a value for snan_bit_is_one. Move routines that no longer have ifdefs out of softfloat-specialize.h. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17fpu/softfloat: Pass FloatClass to pickNaNMulAddRichard Henderson
For each operand, pass a single enumeration instead of a pair of booleans. The commit also merges multiple different ifdef-selected implementations of pickNaNMulAdd into a single function whose body is ifdef-selected. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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