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2018-10-12sdl2: Support all virtio-gpu formatsMax Reitz
There are some 2D resource formats that can be used through virtio-gpu, but which are not supported by SDL2 when used for a scanout; these are all alpha-channel formats and also XBGR (RGBX in non-BE pixman). Add these formats in the switch converting pixman to SDL format constants so a guest cannot crash the VM by triggering the g_assert_not_reached() with an unsupported format. Signed-off-by: Max Reitz <mreitz@redhat.com> Message-id: 20181008185013.19371-1-mreitz@redhat.com [ kraxel: also update sdl2_2d_check_format() ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-10-12gtk: Don't vte_terminal_set_encoding() on new VTE versionsKevin Wolf
The function vte_terminal_set_encoding() is deprecated since VTE 0.54, so stop calling it from that version on. This fixes a build error because of our use of warning flags [-Werror=deprecated-declarations]. Fixes: https://bugs.launchpad.net/bugs/1794939 Reported-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20181011153039.2324-1-kwolf@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-10-11Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-10-10' into ↵Peter Maydell
staging Miscellaneous patches for 2018-10-10 # gpg: Signature made Wed 10 Oct 2018 07:03:10 BST # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-misc-2018-10-10: ivshmem: Fix unplug of device "ivshmem-plain" libqtest: Inline g_assert_no_errno() tests: Restore check-qdict unit test qapi/misc.json: Remove superfluous words in CpuModelExpansionType tests/check-qjson: fix a leak Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-10ivshmem: Fix unplug of device "ivshmem-plain"Markus Armbruster
Commit 2aece63c8a "hostmem: detect host backend memory is being used properly" fixed "ivshmem-plain" to reject memory backends that are already in use, and to block their deletion while in use. Two bugs escaped review: * New ivshmem_plain_exit() fails to call ivshmem_exit(). This breaks unplug. Reproducer: migration after unplug still fails with "Migration is disabled when using feature 'peer mode' in device 'ivshmem'". * It failed to update legacy "ivshmem". Harmless, because it creates the memory backend itself, and nothing else should use it. Fix by moving the two host_memory_backend_set_mapped() calls into ivshmem_common_realize() and ivshmem_exit(), guarded by s->hostmem. Fixes: 2aece63c8a9d2c3a8ff41d2febc4cdeff2633331 Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180926163709.22876-1-armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-10libqtest: Inline g_assert_no_errno()Markus Armbruster
Macro g_assert_no_errno() intrudes into GLib's namespace. It's also pretty pointless. Inline. At one call site, its redundancy is now obvious. Delete it there. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180926122933.3858-1-armbru@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2018-10-10tests: Restore check-qdict unit testMarkus Armbruster
Commit 0bcc8e5bd8d accidentally dropped check-qdict from the list of unit tests (again, see commit 4429532b48a). Put it back, and fix up the test. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180926122309.30631-1-armbru@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2018-10-09qapi/misc.json: Remove superfluous words in CpuModelExpansionTypeKashyap Chamarthy
Remove repetition of 'independent of'. While at it, s/QMU/QEMU in @CpuDefinitionInfo. Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> Message-Id: <20181003104605.8477-1-kchamart@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [Commit message updated as requested by Kashyap] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-10-09tests/check-qjson: fix a leakMarc-André Lureau
Spotted by ASAN: ================================================================= ==11893==ERROR: LeakSanitizer: detected memory leaks Direct leak of 1120 byte(s) in 28 object(s) allocated from: #0 0x7fd0515b0c48 in malloc (/lib64/libasan.so.5+0xeec48) #1 0x7fd050ffa3c5 in g_malloc (/lib64/libglib-2.0.so.0+0x523c5) #2 0x559e708b56a4 in qstring_from_str /home/elmarco/src/qq/qobject/qstring.c:66 #3 0x559e708b4fe0 in qstring_new /home/elmarco/src/qq/qobject/qstring.c:23 #4 0x559e708bda7d in parse_string /home/elmarco/src/qq/qobject/json-parser.c:143 #5 0x559e708c1009 in parse_literal /home/elmarco/src/qq/qobject/json-parser.c:484 #6 0x559e708c1627 in parse_value /home/elmarco/src/qq/qobject/json-parser.c:547 #7 0x559e708c1c67 in json_parser_parse /home/elmarco/src/qq/qobject/json-parser.c:573 #8 0x559e708bc0ff in json_message_process_token /home/elmarco/src/qq/qobject/json-streamer.c:92 #9 0x559e708d1655 in json_lexer_feed_char /home/elmarco/src/qq/qobject/json-lexer.c:292 #10 0x559e708d1fe1 in json_lexer_feed /home/elmarco/src/qq/qobject/json-lexer.c:339 #11 0x559e708bc856 in json_message_parser_feed /home/elmarco/src/qq/qobject/json-streamer.c:121 #12 0x559e708b8b4b in qobject_from_jsonv /home/elmarco/src/qq/qobject/qjson.c:69 #13 0x559e708b8d02 in qobject_from_json /home/elmarco/src/qq/qobject/qjson.c:83 #14 0x559e708a74ae in from_json_str /home/elmarco/src/qq/tests/check-qjson.c:30 #15 0x559e708a9f83 in utf8_string /home/elmarco/src/qq/tests/check-qjson.c:781 #16 0x7fd05101bc49 in test_case_run gtestutils.c:2255 #17 0x7fd05101bc49 in g_test_run_suite_internal gtestutils.c:2339 Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20180901211917.10372-1-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-10-09s390x/tcg: always enable AFP for linux-userDavid Hildenbrand
linux-user should always enable AFP, otherwise our emulated binary might crash once it tries to make use of additional floating-point registers or instructions. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Alex Bennée <alex.bennee@linaro.org> Fixes: db0504154e ("s390x/tcg: check for AFP-register, BFP and DFP data exceptions") Reported-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Tested-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20181008' into staging target-arm queue: * target/arm: fix error in a code comment * virt: Suppress external aborts on virt-2.10 and earlier * target/arm: Correct condition for v8M callee stack push * target/arm: Don't read r4 from v8M exception stackframe twice * target/arm: Support SVE in system emulation mode * target/arm: Implement v8M hardware stack limit checking * hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow # gpg: Signature made Mon 08 Oct 2018 14:58:53 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20181008: (33 commits) hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow target/arm: Add v8M stack checks for MSR to SP_NS target/arm: Add v8M stack checks for VLDM/VSTM target/arm: Add v8M stack checks for Thumb push/pop target/arm: Add v8M stack checks for T32 load/store single target/arm: Add v8M stack checks for Thumb2 LDM/STM target/arm: Add v8M stack checks for LDRD/STRD (imm) target/arm: Add v8M stack limit checks on NS function calls target/arm: Add v8M stack checks on exception entry target/arm: Add some comments in Thumb decode target/arm: Add v8M stack checks on ADD/SUB/MOV of SP target/arm: Move v7m_using_psp() to internals.h target/arm: Define new EXCP type for v8M stack overflows target/arm: Define new TBFLAG for v8M stack checking target/arm: Pass TCGMemOpIdx to sve memory helpers target/arm: Rewrite vector gather first-fault loads target/arm: Rewrite vector gather stores target/arm: Rewrite vector gather loads target/arm: Split contiguous stores for endianness target/arm: Split contiguous loads for endianness ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08hw/display/bcm2835_fb: Silence Coverity warning about multiply overflowPeter Maydell
Coverity complains (CID 1395628) that the multiply in the calculation of the framebuffer base is performed as 32x32 but then used in a context that takes a 64-bit hwaddr. This can't actually ever overflow the 32-bit result, because of the constraints placed on the s->config values in bcm2835_fb_validate_config(). But we can placate Coverity anyway, by explicitly casting one of the inputs to a hwaddr, so the whole expression is calculated with 64-bit arithmetic. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20181005133012.26490-1-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks for MSR to SP_NSPeter Maydell
Updating the NS stack pointer via MSR to SP_NS should include a check whether the new SP value is below the stack limit. No other kinds of update to the various stack pointer and limit registers via MSR should perform a check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-14-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks for VLDM/VSTMPeter Maydell
Add the v8M stack checks for the VLDM/VSTM (aka VPUSH/VPOP) instructions. This code is currently unreachable because we haven't yet implemented M profile floating point support, but since the change is simple, we add it now because otherwise we're likely to forget to do it later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-13-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks for Thumb push/popPeter Maydell
Add v8M stack checks for the 16-bit Thumb push/pop encodings: STMDB, STMFD, LDM, LDMIA, LDMFD. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-12-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks for T32 load/store singlePeter Maydell
Add v8M stack checks for the instructions in the T32 "load/store single" encoding class: these are the "immediate pre-indexed" and "immediate, post-indexed" LDR and STR instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-11-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks for Thumb2 LDM/STMPeter Maydell
Add the v8M stack checks for: * LDM (T2 encoding) * STM (T2 encoding) This includes the 32-bit encodings of the instructions listed in v8M ARM ARM rule R_YVWT as * LDM, LDMIA, LDMFD * LDMDB, LDMEA * POP (multiple registers) * PUSH (muliple registers) * STM, STMIA, STMEA * STMDB, STMFD We perform the stack limit before doing any other part of the load or store. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-10-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks for LDRD/STRD (imm)Peter Maydell
Add the v8M stack checks for: * LDRD (immediate) * STRD (immediate) Loads and stores are more complicated than ADD/SUB/MOV, because we must ensure that memory accesses below the stack limit are not performed, so we can't simply do the check when we actually update SP. For these instructions, if the stack limit check triggers we must not: * perform any memory access below the SP limit * update PC, SP or the load/store base register but it is IMPDEF whether we: * perform any accesses above or equal to the SP limit * update destination registers for loads For QEMU we choose to always check the limit before doing any other part of the load or store, so we won't update any registers or perform any memory accesses. It is UNKNOWN whether the limit check triggers for a load or store where the initial SP value is below the limit and one of the stores would be below the limit, but the writeback moves SP to above the limit. For QEMU we choose to trigger the check in this situation. Note that limit checks happen only for loads and stores which update SP via writeback; they do not happen for loads and stores which simply use SP as a base register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-9-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack limit checks on NS function callsPeter Maydell
Check the v8M stack limits when pushing the frame for a non-secure function call via BLXNS. In order to be able to generate the exception we need to promote raise_exception() from being local to op_helper.c so we can call it from helper.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-8-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks on exception entryPeter Maydell
Add checks for breaches of the v8M stack limit when the stack pointer is decremented to push the exception frame for exception entry. Note that the exception-entry case is unique in that the stack pointer is updated to be the limit value if the limit is hit (per rule R_ZLZG). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-7-peter.maydell@linaro.org
2018-10-08target/arm: Add some comments in Thumb decodePeter Maydell
Add some comments to the Thumb decoder indicating what bits of the instruction have been decoded at various points in the code. This is not an exhaustive set of comments; we're gradually adding comments as we work with particular bits of the code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-6-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks on ADD/SUB/MOV of SPPeter Maydell
Add code to insert calls to a helper function to do the stack limit checking when we handle these forms of instruction that write to SP: * ADD (SP plus immediate) * ADD (SP plus register) * SUB (SP minus immediate) * SUB (SP minus register) * MOV (register) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-5-peter.maydell@linaro.org
2018-10-08target/arm: Move v7m_using_psp() to internals.hPeter Maydell
We're going to want v7m_using_psp() in op_helper.c in the next patch, so move it from helper.c to internals.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-4-peter.maydell@linaro.org
2018-10-08target/arm: Define new EXCP type for v8M stack overflowsPeter Maydell
Define EXCP_STKOF, and arrange for it to cause us to take a UsageFault with CFSR.STKOF set. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-3-peter.maydell@linaro.org
2018-10-08target/arm: Define new TBFLAG for v8M stack checkingPeter Maydell
The Arm v8M architecture includes hardware stack limit checking. When certain instructions update the stack pointer, if the new value of SP is below the limit set in the associated limit register then an exception is taken. Add a TB flag that tracks whether the limit-checking code needs to be emitted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20181002163556.10279-2-peter.maydell@linaro.org
2018-10-08target/arm: Pass TCGMemOpIdx to sve memory helpersRichard Henderson
There is quite a lot of code required to compute cpu_mem_index, or even put together the full TCGMemOpIdx. This can easily be done at translation time. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite vector gather first-fault loadsRichard Henderson
This implements the feature for softmmu, and moves the main loop out of a macro and into a function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite vector gather storesRichard Henderson
This fixes the endianness problem for softmmu, and moves the main loop out of a macro and into an inlined function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite vector gather loadsRichard Henderson
This fixes the endianness problem for softmmu, and moves the main loop out of a macro and into an inlined function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Split contiguous stores for endiannessRichard Henderson
We can choose the endianness at translation time, rather than re-computing it at execution time. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Split contiguous loads for endiannessRichard Henderson
We can choose the endianness at translation time, rather than re-computing it at execution time. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite helper_sve_st[1234]*_rRichard Henderson
This fixes the endianness problem for softmmu, and moves the main loop out of a macro and into an inlined function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite helper_sve_ld[234]*_rRichard Henderson
Use the same *_tlb primitives as we use for ld1. For linux-user, this hoists the set of helper_retaddr. For softmmu, hoists the computation of the current mmu_idx outside the loop, fixes the endianness problem, and moves the main loop out of a macro and into an inlined function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite helper_sve_ld1*_r using pagesRichard Henderson
Uses tlb_vaddr_to_host for correct operation with softmmu. Optimize for accesses within a single page or pair of pages. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Clear unused predicate bits for LD1RQRichard Henderson
The 16-byte load only uses 16 predicate bits. But while reusing the other load infrastructure, we find other bits that are set and trigger an assert. To avoid this and retain the assert, zero-extend the predicate that we pass to the LD1 helper. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Adjust aarch64_cpu_dump_state for system mode SVERichard Henderson
Use the existing helpers to determine if (1) the fpu is enabled, (2) sve state is enabled, and (3) the current sve vector length. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Handle SVE vector length changes in system modeRichard Henderson
SVE vector length can change when changing EL, or when writing to one of the ZCR_ELn registers. For correctness, our implementation requires that predicate bits that are inaccessible are never set. Which means noticing length changes and zeroing the appropriate register bits. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Pass in current_el to fp and sve_exception_elRichard Henderson
We are going to want to determine whether sve is enabled for EL other than current. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Adjust sve_exception_elRichard Henderson
Check for EL3 before testing CPTR_EL3.EZ. Return 0 when the exception should be routed via AdvSIMDFPAccessTrap. Mirror the structure of CheckSVEEnabled more closely. Fixes: 5be5e8eda78 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Define ID_AA64ZFR0_EL1Richard Henderson
Given that the only field defined for this new register may only be 0, we don't actually need to change anything except the name. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Don't read r4 from v8M exception stackframe twicePeter Maydell
A cut-and-paste error meant we were reading r4 from the v8M callee-saves exception stack frame twice. This is harmless since it just meant we did two memory accesses to the same location, but it's unnecessary. Delete it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002150304.2287-1-peter.maydell@linaro.org
2018-10-08target/arm: Correct condition for v8M callee stack pushPeter Maydell
In v7m_exception_taken() we were incorrectly using a "LR bit EXCRET.ES is 1" check when it should be 0 (compare the pseudocode ExceptionTaken() function). This meant we didn't stack the callee-saved registers when tailchaining from a NonSecure to a Secure exception. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002145940.30931-1-peter.maydell@linaro.org
2018-10-08virt: Suppress external aborts on virt-2.10 and earlierPeter Maydell
In commit c79c0a314c43b78 we enabled emulation of external aborts when the guest attempts to access a physical address with no mapped device. In commit 4672cbd7bed88dc6 we suppress this for most legacy boards to prevent breakage of previously working guests, but we didn't suppress it in the 'virt' board, with the rationale "we know that guests won't try to prod devices that we don't describe in the device tree or ACPI tables". This is mostly true, but we've had a report of a Linux guest image that this did break. The problem seems to be that the guest is (incorrectly) configured with a DEBUG_UART_PHYS value that tells it there is a uart at 0x10009000 (which is true for vexpress but not for virt), so in early bootup the kernel probes this bogus address. This is a misconfigured guest, so we don't need to worry about it too much, but we can arrange that guests that ran on QEMU v2.10 (before c79c0a314c43b78) will still run on the "virt-2.10" board model, by suppressing external aborts only for that version and earlier. This seems a reasonable compromise: "virt-2.10" is supposed to behave the same way that "virt" did in the 2.10 release, and making it do that provides a usable workaround for guests with bugs like this. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180925144127.31965-1-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2018-10-08target/arm: fix code comments errorDongjiu Geng
The parameter of kvm_arm_init_cpreg_list() is ARMCPU instead of CPUState, so correct the note to make it match the code. Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> Message-id: 1538069046-5757-1-git-send-email-gengdongjiu@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08Merge remote-tracking branch 'remotes/rth/tags/pull-fpu-20181005' into stagingPeter Maydell
Testing infrastructure for softfpu (not run by default). Drop countLeadingZeros. Fix div_floats. Add udiv_qrnnd specializations for x86_64, s390x, ppc64 hosts. # gpg: Signature made Fri 05 Oct 2018 19:00:09 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-fpu-20181005: softfloat: Specialize udiv_qrnnd for ppc64 softfloat: Specialize udiv_qrnnd for s390x softfloat: Specialize udiv_qrnnd for x86_64 softfloat: Fix division softfloat: Replace countLeadingZeros32/64 with clz32/64 tests/fp/fp-test: add floating point tests gitmodules: add berkeley's softfloat + testfloat version 3 softfloat: remove float64_trunc_to_int Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into ↵Peter Maydell
staging slirp updates Andrew Oates (1): slirp: fix ICMP handling on macOS hosts Gavin Grant (1): slirp: Propagate host TCP RST packet to the guest after socket disconnected Peter Maydell (1): slirp: document mbuf pointers and sizes # gpg: Signature made Sun 07 Oct 2018 19:04:13 BST # gpg: using RSA key E3F65A9E9560DB4C # gpg: Good signature from "Samuel Thibault <samuel.thibault@aquilenet.fr>" # gpg: aka "Samuel Thibault <sthibault@debian.org>" # gpg: aka "Samuel Thibault <samuel.thibault@gnu.org>" # gpg: aka "Samuel Thibault <samuel.thibault@inria.fr>" # gpg: aka "Samuel Thibault <samuel.thibault@labri.fr>" # gpg: aka "Samuel Thibault <samuel.thibault@ens-lyon.org>" # gpg: aka "Samuel Thibault <samuel.thibault@u-bordeaux.fr>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 900C B024 B679 31D4 0F82 304B D017 8C76 7D06 9EE6 # Subkey fingerprint: 33FA 7B64 6195 01F8 CE9C 8F97 E3F6 5A9E 9560 DB4C * remotes/thibault/tags/samuel-thibault: slirp: Propagate host TCP RST packet to the guest after socket disconnected slirp: fix ICMP handling on macOS hosts slirp: document mbuf pointers and sizes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08Merge remote-tracking branch 'remotes/elmarco/tags/option-pull-request' into ↵Peter Maydell
staging CLI help improvements PULLv2: - fix uninitialized "seentype" variable in qom-test # gpg: Signature made Fri 05 Oct 2018 13:28:21 BST # gpg: using RSA key DAE8E10975969CE5 # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * remotes/elmarco/tags/option-pull-request: vl: list user creatable properties when 'help' is argument hostmem: add some properties description vl: handle -object help tests/qom-proplist: check class properties iterator tests/qom-proplist: check properties are not listed multiple times tests/qom-proplist: check duplicate "bv" property registration failed qom/object: register 'type' property as class property qom/object: fix iterating properties over a class qemu-option: improve qemu_opts_print_help() output qemu-option: add help fallback to print the list of options cutils: add qemu_pstrcmp0() qdev-monitor: print help to stdout Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-07slirp: Propagate host TCP RST packet to the guest after socket disconnectedGavin Grant
Commit 27d92ebc5ed1bb0b518d0ebc4c609182ad20a799 handled the case where the TCP connection is abruptly closed via a RST packet, by checking for the ECONNRESET errno. However it does not consider the case where the connection has been half-closed by the host (FIN/ACK), then the host socket is disconnected. For example, if the host application calls close() on the socket, then the application exits. In this case, the socket still exists due to the file descriptor in SLIRP, but it is disconnected. recv() does not indicate an error since an orderly socket close has previously occurred. The socket will then be stuck in FIN_WAIT_2, until the peer sends FIN/ACK or a timeout occurs. Instead we can send a RST to the peer and transition to the CLOSED state. Signed-off-by: Gavin Grant <gavingrant@protonmail.com> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2018-10-07slirp: fix ICMP handling on macOS hostsAndrew Oates
On Linux, SOCK_DGRAM+IPPROTO_ICMP sockets give only the ICMP packet when read from. On macOS, however, the socket acts like a SOCK_RAW socket and includes the IP header as well. This change strips the extra IP header from the received packet on macOS before sending it to the guest. SOCK_DGRAM ICMP sockets aren't supported on other BSDs, but we enable this behavior for them as well to treat the sockets the same as raw sockets. Signed-off-by: Andrew Oates <aoates@google.com> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2018-10-07slirp: document mbuf pointers and sizesPeter Maydell
and fix confusing datasize name into gapsize in m_inc. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2018-10-05softfloat: Specialize udiv_qrnnd for ppc64Richard Henderson
The ISA has a 128/64-bit division instruction, though it assumes the low 64-bits of the numerator are 0, and so requires a bit more fixup than a full 128-bit division insn. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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