aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2022-11-05xen/pt: fix syntax error that causes FTBFS in some configurationsChuck Zmudzinski
When Qemu is built with --enable-xen and --disable-xen-pci-passthrough and the target os is linux, the build fails with: meson.build:3477:2: ERROR: File xen_pt_stub.c does not exist. Fixes: 582ea95f5f93 ("meson: convert hw/xen") Signed-off-by: Chuck Zmudzinski <brchuckz@aol.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <5f1342a13c09af77b1a7b0aeaba5955bcea89731.1667242033.git.brchuckz@aol.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-11-05Fix some typos in documentation and commentsStefan Weil
Most of them were found and fixed using codespell. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20221030105944.311940-1-sw@weilnetz.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-11-05qapi: virtio: Fix the introduced versionHan Han
The items of qapi/virtio.json are introduced at a5ebce38576. They will be in the version 7.2 not 7.1. Signed-off-by: Han Han <hhan@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20221101014647.3000801-1-hhan@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-11-05Merge tag 'vfio-fixes-v7.2-rc0.0' of https://gitlab.com/alex.williamson/qemu ↵Stefan Hajnoczi
into staging VFIO fixes for v7.2-rc0 * Correct initial migration device state using correct v1 protocol enum (Avihai Horon) # -----BEGIN PGP SIGNATURE----- # # iQJPBAABCAA5FiEEQvbATlQL0amee4qQI5ubbjuwiyIFAmNkOh4bHGFsZXgud2ls # bGlhbXNvbkByZWRoYXQuY29tAAoJECObm247sIsiIG8P/2W+Fqz4DrkWUk2MO14G # djx6S/He7yZURlBLxfdQuGFcGzVQt1gFy7CD3JzMhDPzThIqyMHzMVVVVARODCHo # NQEss2c2oYAodap/I5NPXxFA9EHqgrHZ8kfJ8ioZbqU0L3eLmMApBZMXz3tK5f6u # XtKCpF9U2MfJCb+Rzxwa4bKidJJEtzAhX/v0gfWKYfp7hT1iRaNr9bS/IqBny+wV # Mdf5NVZibjlv8e1e1FAf5X9dMaT9NItBqBMl42X0Pfyy0dDpq9KVpyhewIeeqMGM # iuMeYadgRGWLuAhdkXSZrj06rLoHWxagIyPhCW57i9b7IXpaV4kkh2pHEx56MrV7 # bruM3znY7Xj3axS0HCM3DGP4OL2bc1MGjHcgNwjB6aMqxUN2rKan9wbvj+c1U0ms # OjnG9ZTIVnROncL0jaEkulFwi+0MEIWYJiVAh81Miv8iHmpj1Krmn15N0R0XI7bx # sEQaFrE3gyufgzAuwOht2oz6Qg84bWpwpJT0kQXXaANGfvq1nS1dHk5+4jmExQ+P # TSE+V3q1q29EEcy/U8nMb1HmRUUdrWdZnV2RWunDbqEvW6KOnLdSX2xq5HKSuS9Y # H1oqv15gjNBDpJDlelkjlVTQ7MPCcV9MQDBgFMkZRS9TIAHQ/3lRLhCNNCN76GMK # d1YNd9iZn+Fewb/Knm3+aTxS # =Nw9N # -----END PGP SIGNATURE----- # gpg: Signature made Thu 03 Nov 2022 18:01:02 EDT # gpg: using RSA key 42F6C04E540BD1A99E7B8A90239B9B6E3BB08B22 # gpg: issuer "alex.williamson@redhat.com" # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [full] # gpg: aka "Alex Williamson <alex@shazbot.org>" [full] # gpg: aka "Alex Williamson <alwillia@redhat.com>" [full] # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" [full] # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * tag 'vfio-fixes-v7.2-rc0.0' of https://gitlab.com/alex.williamson/qemu: vfio/migration: Fix wrong enum usage Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-04Merge tag 'pull-target-arm-20221104' of ↵Stefan Hajnoczi
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Fix regression booting Trusted Firmware * Honor HCR_E2H and HCR_TGE in ats_write64() * Copy the entire vector in DO_ZIP * Fix Privileged Access Never (PAN) for aarch32 * Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB * Set SCR_EL3.HXEn when direct booting kernel * Set SME and SVE EL3 vector lengths when direct booting kernel # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmNk+KkZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vUsD/9SYZP3ne2OZxBe8he98jJ5 # 6apODiBksBLUM+1bKEoYW8Kw4XpS10I1Tbnxe7n0bNAfIiZlsZ7HJAJaYWy4MX4k # Bq0v1EIFo+Obumocc14ZzWcw9yPpHOGavKHXfPxTtIw0amtOmh3aMBPuOZKiMSaq # TdI/8654DbAOY3Hp/r6WnXwEgAc23kx/PtGhQFdU4iWhzTdeQeFkgCCsVMO02zFQ # ZM4wiAATpfNfgf5+Wxoin6RQ8nI9PF+Xf7HhN3d1CiXju3vOl+geYNkubJzIopv1 # itLcnvduYE6+5oJsnXZ4FDNO6/nnqWRNqtyDf0/NjLROfj84BPJpZqMX+FR6Q0I0 # d+4/oEw4A46qfaS5b4/YelbJOiUgiViWU1Xs3g2dkeTMT8CyGfDrJ2HRDKN7AaHo # llL7s1calkX2oSs+gU0BAw8xRETGwMBSOpF6JmPVh277LjvWfN1vsJzVUG3wrSXL # G7qa2h+fHV5Xu876sc/i0+d4qHuqcE/EU86VQ6X40f+dRzN02rkSCPAxzGFwLXOr # 8fl5MsX6z5pqcubnzxkhi66ZHc6fXsvtUjKBxyrVpMyjMlV9PTJ2Q1RCgVctErXk # lDzsLuplzPSjZBy3Peib/rLnmYUxJHyPe0RFYIumzZv/UHwL4GjZgkI842UVBpAL # FvIGblcCXHhdP4UFvqgZhw== # =Fcb4 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 04 Nov 2022 07:34:01 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20221104' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm: Two fixes for secure ptw target/arm: Honor HCR_E2H and HCR_TGE in ats_write64() target/arm: Copy the entire vector in DO_ZIP target/arm: Fix Privileged Access Never (PAN) for aarch32 target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB hw/arm/boot: Set SCR_EL3.HXEn when booting kernel hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-04Merge tag 'pull-loongarch-20221104' of https://gitlab.com/gaosong/qemu into ↵Stefan Hajnoczi
staging pull-loongarch-20221104 v2: - fix win32 build error; - Add Rui Wang' patches. # -----BEGIN PGP SIGNATURE----- # # iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCY2TZsAAKCRBAov/yOSY+ # 30kyA/9VEYvFQaXM9RP78OoiK0bANiByTCQMXCAuos1wXui/FwAcqE9YWXZStzH0 # MHdT2PyH680w9aKjhHuPbGs5xU911cQ94SPWzcTtM4HfEH+3N7RBfF0gS7MA+DLa # 92vLqEIDC6SbAlY4/CRJVJmOl58d4uhEUUpq6eVzmJHcA3W5qw== # =wblG # -----END PGP SIGNATURE----- # gpg: Signature made Fri 04 Nov 2022 05:21:52 EDT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20221104' of https://gitlab.com/gaosong/qemu: target/loongarch: Fix emulation of float-point disable exception target/loongarch: Adjust the layout of hardware flags bit fields target/loongarch: Fix raise_mmu_exception() set wrong exception_index target/loongarch: Add exception subcode hw/loongarch: Add TPM device for LoongArch virt machine hw/loongarch: Improve fdt for LoongArch virt machine hw/loongarch: Load FDT table into dram memory space hw/intc: Fix LoongArch extioi coreisr accessing hw/intc: Convert the memops to with_attrs in LoongArch extioi Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-04target/arm: Two fixes for secure ptwRichard Henderson
Reversed the sense of non-secure in get_phys_addr_lpae, and failed to initialize attrs.secure for ARMMMUIdx_Phys_S. Fixes: 48da29e4 ("target/arm: Add ptw_idx to S1Translate") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1293 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-11-04target/arm: Honor HCR_E2H and HCR_TGE in ats_write64()Ake Koomsin
We need to check HCR_E2H and HCR_TGE to select the right MMU index for the correct translation regime. To check for EL2&0 translation regime: - For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE - For S1E2* ops, check only HCR_E2H Signed-off-by: Ake Koomsin <ake@igel.co.jp> Message-id: 20221101064250.12444-1-ake@igel.co.jp Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-11-04target/arm: Copy the entire vector in DO_ZIPRichard Henderson
With odd_ofs set, we weren't copying enough data. Fixes: 09eb6d7025d1 ("target/arm: Move sve zip high_ofs into simd_data") Reported-by: Idan Horowitz <idan.horowitz@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221031054144.3574-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-11-04target/arm: Fix Privileged Access Never (PAN) for aarch32Timofey Kutergin
When we implemented the PAN support we theoretically wanted to support it for both AArch32 and AArch64, but in practice several bugs made it essentially unusable with an AArch32 guest. Fix all those problems: - Use CPSR.PAN to check for PAN state in aarch32 mode - throw permission fault during address translation when PAN is enabled and kernel tries to access user acessible page - ignore SCTLR_XP bit for armv7 and armv8 (conflicts with SCTLR_SPAN). Signed-off-by: Timofey Kutergin <tkutergin@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20221027112619.2205229-1-tkutergin@gmail.com [PMM: tweak commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-11-04target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLBPeter Maydell
The HCR_EL2.TTLB bit is supposed to trap all EL1 execution of TLB maintenance instructions. However we have added new TLB insns for FEAT_TLBIOS and FEAT_TLBIRANGE, and forgot to set their accessfn to access_ttlb. Add the missing accessfns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-11-04hw/arm/boot: Set SCR_EL3.HXEn when booting kernelPeter Maydell
When we direct boot a kernel on a CPU which emulates EL3, we need to set up the EL3 system registers as the Linux kernel documentation specifies: https://www.kernel.org/doc/Documentation/arm64/booting.rst For CPUs with FEAT_HCX support this includes: - SCR_EL3.HXEn (bit 38) must be initialised to 0b1. but we forgot to do this when implementing FEAT_HCX, which would mean that a guest trying to access the HCRX_EL2 register would crash. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221027140207.413084-3-peter.maydell@linaro.org
2022-11-04hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernelPeter Maydell
When we direct boot a kernel on a CPU which emulates EL3, we need to set up the EL3 system registers as the Linux kernel documentation specifies: https://www.kernel.org/doc/Documentation/arm64/booting.rst For SVE and SME this includes: - ZCR_EL3.LEN must be initialised to the same value for all CPUs the kernel is executed on. - SMCR_EL3.LEN must be initialised to the same value for all CPUs the kernel will execute on. Although we are technically compliant with this, the "same value" we currently use by default is the reset value of 0. This will end up forcing the guest kernel's SVE and SME vector length to be only the smallest supported length. Initialize the vector length fields to their maximum possible value, which is 0xf. If the implementation doesn't actually support that vector length then the effective vector length will be constrained down to the maximum supported value at point of use. This allows the guest to use all the vector lengths the emulated CPU supports (by programming the _EL2 and _EL1 versions of these registers.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221027140207.413084-2-peter.maydell@linaro.org
2022-11-04target/loongarch: Fix emulation of float-point disable exceptionRui Wang
We need to emulate it to generate a floating point disable exception when CSR.EUEN.FPE is zero. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Rui Wang <wangrui@loongson.cn> Message-Id: <20221104040517.222059-3-wangrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-11-04target/loongarch: Adjust the layout of hardware flags bit fieldsRui Wang
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Rui Wang <wangrui@loongson.cn> Message-Id: <20221104040517.222059-2-wangrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-11-04target/loongarch: Fix raise_mmu_exception() set wrong exception_indexSong Gao
When the address is invalid address, We should set exception_index according to MMUAccessType, and EXCCODE_ADEF need't update badinstr. Otherwise, The system enters an infinite loop. e.g: run test.c on system mode test.c: #include<stdio.h> void (*func)(int *); int main() { int i = 8; void *ptr = (void *)0x4000000000000000; func = ptr; func(&i); return 0; } Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20221101073210.3934280-2-gaosong@loongson.cn>
2022-11-04target/loongarch: Add exception subcodeSong Gao
We need subcodes to distinguish the same excode cs->exception_indexs, such as EXCCODE_ADEF/EXCCODE_ADEM. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20221101073210.3934280-1-gaosong@loongson.cn>
2022-11-04hw/loongarch: Add TPM device for LoongArch virt machineXiaojuan Yang
Add TPM device for LoongArch virt machine, including establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS to dynamic_sysbus_devices list. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20221028014007.2718352-4-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-11-04hw/loongarch: Improve fdt for LoongArch virt machineXiaojuan Yang
Add new items into LoongArch FDT, including rtc and uart info. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20221028014007.2718352-3-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-11-04hw/loongarch: Load FDT table into dram memory spaceXiaojuan Yang
Load FDT table into dram memory space, and the addr is 2 MiB. Since lowmem region starts from 0, FDT base address is located at 2 MiB to avoid NULL pointer access. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Acked-by: Song Gao <gaosong@loongson.cn> Message-Id: <20221028014007.2718352-2-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-11-04hw/intc: Fix LoongArch extioi coreisr accessingXiaojuan Yang
1. When cpu read or write extioi COREISR reg, it should access the reg belonged to itself, so the cpu index of 's->coreisr' is current cpu number. Using MemTxAttrs' requester_id to get the cpu index. 2. it need not to mask 0x1f when calculate the coreisr array index. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221021015307.2570844-3-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-11-04hw/intc: Convert the memops to with_attrs in LoongArch extioiXiaojuan Yang
Converting the MemoryRegionOps read/write handlers to with_attrs in LoongArch extioi emulation. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221021015307.2570844-2-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-11-03vfio/migration: Fix wrong enum usageAvihai Horon
vfio_migration_init() initializes VFIOMigration->device_state using enum of VFIO migration protocol v2. Current implemented protocol is v1 so v1 enum should be used. Fix it. Fixes: 429c72800654 ("vfio/migration: Fix incorrect initialization value for parameters in VFIOMigration") Signed-off-by: Avihai Horon <avihaih@nvidia.com> Reviewed-by: Zhang Chen <chen.zhang@intel.com> Link: https://lore.kernel.org/r/20221016085752.32740-1-avihaih@nvidia.com Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2022-11-03Merge tag 'linux-user-for-7.2-pull-request' of ↵Stefan Hajnoczi
https://gitlab.com/laurent_vivier/qemu into staging linux-user pull request 20221103 Fix recvmsg Fix hppa exception handler Add close_range Add strace for timer_settime64 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmNjgI0SHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L7485noP/jx8c5ytN+K5JbTLIdGYAbTJLm82Pnl5 # PP6mzaiII+gqBsmsTmmZhJ92xWjyX9kZmwCY7jD5XYXHQ2jFg3fU96ktYum7q8BU # XaPP4Cd6TfDE4q8H34PD/4byTGEkHP6o7EhAkIVAKsRQcQgZnsc3tvZetXxncltZ # UypPqAjvTy3s3uJFRmI4z9sYiAvjEflgk8doci/i5dOSgEBUmcCw/tFUx2GFrHiR # TdX8BRGaGEt+TPyKAo6sVBgTs1KiU4RzOqrPoxZO8aEClwPCRTLqNw/IONtHmx9f # EevuwDS7ZdoMdXi7YANDVy17JkmPBU3g8DFSWYGYObRpdmexmD66aW4kCeUYL0BC # y5aqxRWEi/7Kjvb6QlO3sJnAMfXaOQcCNn1++Tk1V8/O7f3k/xakya700fiMRIaQ # vyrW+g0TrCWEOgWl1Nyd0yDayX0wCM8CV/5SoO21QHjjzG+zmPxvroDpfVHcwbAl # V+wzVBj6AE5QBZKXUSE4b5DalcASF3pbUTorB5Xv/HDdsM1cRGZLBo7KECXqLKaa # L5VLgDdrZdSJz60f4P7Ldyhv0grb3C38JNqYg8fi8gWdj6dEc5M4coX84lA3JE7v # +Vf3Ys+lGC+DCSp2Qsh5FJvgsRn740ROToLJcXu3jxYPlquEsZpS1hpC+WOTRXOU # l2tnZIV9/SyH # =UZJY # -----END PGP SIGNATURE----- # gpg: Signature made Thu 03 Nov 2022 04:49:17 EDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'linux-user-for-7.2-pull-request' of https://gitlab.com/laurent_vivier/qemu: linux-user: always translate cmsg when recvmsg linux-user: Add strace output for timer_settime64() syscall linux-user: Add close_range() syscall linux-user/hppa: Detect glibc ABORT_INSTRUCTION and EXCP_BREAK handler Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-03Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi
* bug fixes * reduced memory footprint for IPI virtualization on Intel processors * asynchronous teardown support (Linux only) # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmNiVykUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroN0Swf/YxjphCtFgYYSO14WP+7jAnfRZLhm # 0xWChWP8rco5I352OBFeFU64Av5XoLGNn6SZLl8lcg86lQ/G0D27jxu6wOcDDHgw # 0yTDO1gevj51UKsbxoC66OWSZwKTEo398/BHPDcI2W41yOFycSdtrPgspOrFRVvf # 7M3nNjuNPsQorZeuu8NGr3jakqbt99ZDXcyDEWbrEAcmy2JBRMbGgT0Kdnc6aZfW # CvL+1ljxzldNwGeNBbQW2QgODbfHx5cFZcy4Daze35l5Ra7K/FrgAzr6o/HXptya # 9fEs5LJQ1JWI6JtpaWwFy7fcIIOsJ0YW/hWWQZSDt9JdAJFE5/+vF+Kz5Q== # =CgrO # -----END PGP SIGNATURE----- # gpg: Signature made Wed 02 Nov 2022 07:40:25 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: target/i386: Fix test for paging enabled util/log: Close per-thread log file on thread termination target/i386: Set maximum APIC ID to KVM prior to vCPU creation os-posix: asynchronous teardown for shutdown on Linux target/i386: Fix calculation of LOCK NEG eflags Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-03Merge tag 'nvme-fixes-pull-request' of git://git.infradead.org/qemu-nvme ↵Stefan Hajnoczi
into staging hw/nvme fixes Two small fixes. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmNiKUkACgkQTeGvMW1P # DenBuAf/fwznY98HVg8zYQ/chLGMCmjAa80buf867usnL5Iuhms1XCkxpETFfMAZ # HR5gg+52vHZg/FCGbQ3E8d/ZLwDZHboiEuZDPo9aYI4uTj3gs66j9S0y6DUVkn5I # 7Ad+BYW7/d4++8fZAdaUV67rmo89OvjgSqOs+O094nGAPIEgJnsL7HrOFniKnNqu # MMWvFlK1bAz/iPKPf2WWVeuAs1cMs+TPsjE+ZHhUEYaZAiB1myKVPIAVyOHx5yoT # 6VTsNMLvNEi5+4Ucg1TkIwb/dAXrYYEvreo8ri1yuHCVOqw4lU9FfPhmiz5h76Sc # sI0cMiNL/RW5pk6rnDLkPZyjTKw30A== # =s2fM # -----END PGP SIGNATURE----- # gpg: Signature made Wed 02 Nov 2022 04:24:41 EDT # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * tag 'nvme-fixes-pull-request' of git://git.infradead.org/qemu-nvme: hw/nvme: Abort copy command when format is one while pif hw/nvme: reenable cqe batching Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-02linux-user: always translate cmsg when recvmsgIcenowy Zheng
It's possible that a message contains both normal payload and ancillary data in the same message, and even if no ancillary data is available this information should be passed to the target, otherwise the target cmsghdr will be left uninitialized and the target is going to access uninitialized memory if it expects cmsg. Always call the function that translate cmsg when recvmsg, because that function should be empty-cmsg-safe (it creates an empty cmsg in the target). Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20221028081220.1604244-1-uwu@icenowy.me> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-11-02linux-user: Add strace output for timer_settime64() syscallHelge Deller
Add missing timer_settime64() strace output and specify format for timer_settime(). Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <Y1b5eIXFoMRDcDL9@p100> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-11-02linux-user: Add close_range() syscallHelge Deller
Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <Y1dLJoEDhJ2AAYDn@p100> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-11-02linux-user/hppa: Detect glibc ABORT_INSTRUCTION and EXCP_BREAK handlerHelge Deller
The glibc on the hppa platform uses the "iitlbp %r0,(%sr0, %r0)" assembler instruction as ABORT_INSTRUCTION. If this (in userspace context) illegal assembler statement is found, dump the registers and report the failure to userspace the same way as the Linux kernel on physical hardware. For other illegal instructions report TARGET_ILL_ILLOPC instead of TARGET_ILL_ILLOPN as si_code. Additionally add the missing EXCP_BREAK exception handler which occurs when the "break x,y" assembler instruction is executed and report EXCP_ASSIST traps. Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <Y1osHVsylkuZNUnY@p100> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-11-02target/i386: Fix test for paging enabledRichard Henderson
If CR0.PG is unset, pg_mode will be zero, but it will also be zero for non-PAE/non-PSE page tables with CR0.WP=0. Restore the correct test for paging enabled. Fixes: 98281984a37 ("target/i386: Add MMU_PHYS_IDX and MMU_NESTED_IDX") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1269 Reported-by: Andreas Gustafsson <gson@gson.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221102091232.1092552-1-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-11-02MAINTAINERS: add myself as the maintainer for acpi biosbits avocado testsAni Sinha
I wrote the biosbits avocado tests for testing QEMU's ACPI/SMBIOS implementation and all the related changes including fixes in biosbits software itself. Making myself as the maintainer for QEMU's biosbits related files and test scripts. Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Maydell Peter <peter.maydell@linaro.org> Cc: John Snow <jsnow@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Igor Mammedov <imammedo@redhat.com> Cc: Michael Tsirkin <mst@redhat.com> Signed-off-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221021095108.104843-8-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02acpi/tests/avocado/bits/doc: add a doc file to describe the acpi bits testAni Sinha
A doc file is added under docs/devel that describes the purpose of the various test files and gives guidance to developers on where and how to make changes. Cc: Daniel P. Berrange" <berrange@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Maydell Peter <peter.maydell@linaro.org> Cc: John Snow <jsnow@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Igor Mammedov <imammedo@redhat.com> Cc: Michael Tsirkin <mst@redhat.com> Signed-off-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20221021095108.104843-7-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02acpi/tests/avocado/bits: add acpi and smbios avocado tests that uses biosbitsAni Sinha
This introduces QEMU acpi/smbios biosbits avocado test which is run from within the python virtual environment. When the bits tests are run, bits binaries are downloaded from an external repo/location, bios bits iso is regenerated containing the acpi/smbios bits tests that are maintained as a part of the QEMU source under tests/avocado/acpi-bits/bits-test . When the VM is spawned with the iso, it runs the tests in batch mode and the results are pushed out from the VM to the test machine where they are analyzed by this script and pass/fail results are reported. Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Maydell Peter <peter.maydell@linaro.org> Cc: John Snow <jsnow@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Igor Mammedov <imammedo@redhat.com> Cc: Michael Tsirkin <mst@redhat.com> Signed-off-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20221021095108.104843-6-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02acpi/tests/avocado/bits: add biosbits config file for running bios testsAni Sinha
This change adds initial biosbits config file that instructs biosbits to run bios test suits in batch mode. Additionally acpi and smbios structures are also dumped. Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Maydell Peter <peter.maydell@linaro.org> Cc: John Snow <jsnow@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Igor Mammedov <imammedo@redhat.com> Cc: Michael Tsirkin <mst@redhat.com> Signed-off-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221021095108.104843-5-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02acpi/tests/avocado/bits: disable acpi PSS tests that are failing in biosbitsAni Sinha
PSS tests in acpi test suite seems to be failing in biosbits. This is because the test is unable to find PSS support in QEMU bios. Let us disable them for now so that make check does not fail. We can fix the tests and re-enable them later. Example failure: ---- ACPI _PSS (Pstate) table conformance tests ---- [assert] _PSS must exist FAIL \_SB_.CPUS.C000 No _PSS exists Summary: 1 passed, 1 failed ---- ACPI _PSS (Pstate) runtime tests ---- [assert] _PSS must exist FAIL \_SB_.CPUS.C000 No _PSS exists Summary: 0 passed, 1 failed Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Maydell Peter <peter.maydell@linaro.org> Cc: John Snow <jsnow@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Igor Mammedov <imammedo@redhat.com> Cc: Michael Tsirkin <mst@redhat.com> Signed-off-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221021095108.104843-4-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02acpi/tests/avocado/bits: initial commit of test scripts that are run by biosbitsAni Sinha
This is initial commit of cpuid, acpi and smbios python test scripts for biosbits to execute. No change has been made to them from the original code written by the biosbits author Josh Triplett. They are required to be installed into the bits iso file and then run from within the virtual machine booted off with biosbits iso. The test scripts have a ".py2" extension in order to prevent avocado from loading them. They are written in python 2.7 and are run from within bios bits. There is no need for avocado to try to load them and call out errors on python3 specific syntaxes. The original location of these tests are here: https://github.com/biosbits/bits/blob/master/python/testacpi.py https://github.com/biosbits/bits/blob/master/python/smbios.py https://github.com/biosbits/bits/blob/master/python/testcpuid.py For QEMU, we maintain a fork of the above repo here with numerious fixes: https://gitlab.com/qemu-project/biosbits-bits The acpi test for example is maintained here in the fork: https://gitlab.com/qemu-project/biosbits-bits/-/raw/master/python/testacpi.py Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Maydell Peter <peter.maydell@linaro.org> Cc: John Snow <jsnow@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Igor Mammedov <imammedo@redhat.com> Cc: Michael Tsirkin <mst@redhat.com> Signed-off-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221021095108.104843-2-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02cryptodev: Add a lkcf-backend for cryptodevLei He
cryptodev: Added a new type of backend named lkcf-backend for cryptodev. This backend upload asymmetric keys to linux kernel, and let kernel do the accelerations if possible. The lkcf stands for Linux Kernel Cryptography Framework. Signed-off-by: lei he <helei.sig11@bytedance.com> Message-Id: <20221008085030.70212-5-helei.sig11@bytedance.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02crypto: Support export akcipher to pkcs8Lei He
crypto: support export RSA private keys with PKCS#8 standard. So that users can upload this private key to linux kernel. Signed-off-by: lei he <helei.sig11@bytedance.com> Message-Id: <20221008085030.70212-4-helei.sig11@bytedance.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2022-11-02crypto: Support DER encodingsLei He
Add encoding interfaces for DER encoding: 1. support decoding of 'bit string', 'octet string', 'object id' and 'context specific tag' for DER encoder. 2. implemented a simple DER encoder. 3. add more testsuits for DER encoder. Signed-off-by: lei he <helei.sig11@bytedance.com> Message-Id: <20221008085030.70212-3-helei.sig11@bytedance.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2022-11-02virtio-crypto: Support asynchronous modeLei He
virtio-crypto: Modify the current interface of virtio-crypto device to support asynchronous mode. Signed-off-by: lei he <helei.sig11@bytedance.com> Message-Id: <20221008085030.70212-2-helei.sig11@bytedance.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02test/acpi/bios-tables-test: SSDT: update golden master binariesRobert Hoo
And empty bios-tables-test-allowed-diff.h. Diff of ASL form, from qtest testlog.txt: @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180629 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/pc/SSDT.dimmpxm, Thu Sep 22 18:25:06 2022 + * Disassembly of /tmp/aml-YYZZS1, Thu Sep 22 18:25:06 2022 * * Original Table Header: * Signature "SSDT" - * Length 0x000002DE (734) + * Length 0x00000717 (1815) * Revision 0x01 - * Checksum 0x56 + * Checksum 0xBC * OEM ID "BOCHS " * OEM Table ID "NVDIMM" * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) { Scope (\_SB) { Device (NVDR) { Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID Method (NCAL, 5, Serialized) { Local6 = MEMA /* \MEMA */ @@ -49,52 +49,52 @@ ODAT, 32736 } If ((Arg4 == Zero)) { Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba") } ElseIf ((Arg4 == 0x00010000)) { Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62") } Else { Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66") } - If (((Local6 == Zero) | (Arg0 != Local0))) + If (((Local6 == Zero) || (Arg0 != Local0))) { If ((Arg2 == Zero)) { Return (Buffer (One) { 0x00 // . }) } Return (Buffer (One) { 0x01 // . }) } HDLE = Arg4 REVS = Arg1 FUNC = Arg2 - If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One))) + If (((ObjectType (Arg3) == 0x04) && (SizeOf (Arg3) == One))) { Local2 = Arg3 [Zero] Local3 = DerefOf (Local2) FARG = Local3 } NTFI = Local6 Local1 = (RLEN - 0x04) If ((Local1 < 0x08)) { Local2 = Zero Name (TBUF, Buffer (One) { 0x00 // . }) Local7 = Buffer (Zero){} @@ -161,45 +161,234 @@ Else { If ((Local1 == Zero)) { Return (Local2) } Local3 += Local1 Concatenate (Local2, Local0, Local2) } } } Device (NV00) { Name (_ADR, One) // _ADR: Address + Method (_LSI, 0, Serialized) // _LSI: Label Storage Information + { + Local0 = NCAL (ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66"), One, 0x04, Zero, One) + CreateDWordField (Local0, Zero, STTS) + CreateDWordField (Local0, 0x04, SLSA) + CreateDWordField (Local0, 0x08, MAXT) + Local1 = Package (0x03) + { + STTS, + SLSA, + MAXT + } + Return (Local1) + } + + Method (_LSR, 2, Serialized) // _LSR: Label Storage Read + { + Name (INPT, Buffer (0x08) + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // ........ + }) + CreateDWordField (INPT, Zero, OFST) + CreateDWordField (INPT, 0x04, LEN) + OFST = Arg0 + LEN = Arg1 + Local0 = Package (0x01) + { + INPT + } + Local3 = NCAL (ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66"), One, 0x05, Local0, One) + CreateDWordField (Local3, Zero, STTS) + CreateField (Local3, 0x20, (LEN << 0x03), LDAT) + Name (LSA, Buffer (Zero){}) + ToBuffer (LDAT, LSA) /* \_SB_.NVDR.NV00._LSR.LSA_ */ + Local1 = Package (0x02) + { + STTS, + LSA + } + Return (Local1) + } + + Method (_LSW, 3, Serialized) // _LSW: Label Storage Write + { + Local2 = Arg2 + Name (INPT, Buffer (0x08) + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // ........ + }) + CreateDWordField (INPT, Zero, OFST) + CreateDWordField (INPT, 0x04, TLEN) + OFST = Arg0 + TLEN = Arg1 + Concatenate (INPT, Local2, INPT) /* \_SB_.NVDR.NV00._LSW.INPT */ + Local0 = Package (0x01) + { + INPT + } + Local3 = NCAL (ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66"), One, 0x06, Local0, One) + CreateDWordField (Local3, Zero, STTS) + Return (STTS) /* \_SB_.NVDR.NV00._LSW.STTS */ + } + (iterates in each NV) Message-Id: <20220922122155.1326543-6-robert.hu@linux.intel.com> Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02acpi/nvdimm: Implement ACPI NVDIMM Label MethodsRobert Hoo
Recent ACPI spec [1] has defined NVDIMM Label Methods _LS{I,R,W}, which deprecates corresponding _DSM Functions defined by PMEM _DSM Interface spec [2]. Since the semantics of the new Label Methods are almost same as old _DSM methods, the implementations here simply wrapper old ones. ASL form diff can be found in next patch of updating golden master binaries. [1] ACPI Spec v6.4, 6.5.10 NVDIMM Label Methods https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf [2] Intel PMEM _DSM Interface Spec v2.0, 3.10 Deprecated Functions https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <20220922122155.1326543-5-robert.hu@linux.intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02acpi/nvdimm: define macro for NVDIMM Device _DSMRobert Hoo
Since it will be heavily used in next patch, define macro NVDIMM_DEVICE_DSM_UUID for "4309AC30-0D11-11E4-9191-0800200C9A66", which is NVDIMM device specific method uuid defined in NVDIMM _DSM interface spec, Section 3. [1] No functional changes in this patch. [1] https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220922122155.1326543-4-robert.hu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02acpi/ssdt: Fix aml_or() and aml_and() in if clauseRobert Hoo
In If condition, using bitwise and/or, rather than logical and/or. The result change in AML code: If (((Local6 == Zero) | (Arg0 != Local0))) ==> If (((Local6 == Zero) || (Arg0 != Local0))) If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One))) ==> If (((ObjectType (Arg3) == 0x04) && (SizeOf (Arg3) == One))) Fixes: 90623ebf603 ("nvdimm acpi: check UUID") Fixes: 4568c948066 ("nvdimm acpi: save arg3 of _DSM method") Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Reviewed-by: Jingqi Liu <jingqi.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220922122155.1326543-3-robert.hu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02tests/acpi: allow SSDT changesRobert Hoo
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Reviewed-by: Jingqi Liu <jingqi.liu@intel.com> Message-Id: <20220922122155.1326543-2-robert.hu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02hw/i386/e820: remove legacy reserved entries for e820Ani Sinha
e820 reserved entries were used before the dynamic entries with fw config files were intoduced. Please see the following change: 7d67110f2d9a6("pc: add etc/e820 fw_cfg file") Identical support was introduced into seabios as well with the following commit: ce39bd4031820 ("Add support for etc/e820 fw_cfg file") Both the above commits are now quite old. QEMU machines 1.7 and newer no longer use the reserved entries. Seabios uses fw config files and dynamic e820 entries by default and only falls back to using reserved entries when it has to work with old qemu (versions earlier than 1.7). Please see functions qemu_cfg_e820() and qemu_early_e820(). It is safe to remove legacy FW_CFG_E820_TABLE and associated code now as QEMU 7.0 has deprecated i440fx machines 1.7 and older. It would be incredibly rare to run the latest qemu version with a very old version of seabios that did not support fw config files for e820. As far as I could see, edk2/ovfm never supported reserved entries and uses fw config files from the beginning. So there should be no incompatibilities with ovfm as well. CC: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Ani Sinha <ani@anisinha.ca> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220831045311.33083-1-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-02hw/nvme: Abort copy command when format is one while pifFrancis Pravin Antony Michael Raj
As per the NVMe Command Set specification Section 3.2.2, if i) The namespace is formatted to use 16b Guard Protection Information (i.e., pif = 0) and ii) The Descriptor Format is not cleared to 0h Then the copy command should be aborted with the status code of Invalid Namespace or Format Fixes: 44219b6029fc ("hw/nvme: 64-bit pi support") Signed-off-by: Francis Pravin Antony Michael Raj <francis.michael@solidigm.com> Signed-off-by: Jonathan Derrick <jonathan.derrick@solidigm.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-11-02hw/nvme: reenable cqe batchingKlaus Jensen
Commit 2e53b0b45024 ("hw/nvme: Use ioeventfd to handle doorbell updates") had the unintended effect of disabling batching of CQEs. This patch changes the sq/cq timers to bottom halfs and instead of calling nvme_post_cqes() immediately (causing an interrupt per cqe), we defer the call. | iops -----------------+------ baseline | 138k +cqe batching | 233k Fixes: 2e53b0b45024 ("hw/nvme: Use ioeventfd to handle doorbell updates") Reviewed-by: Keith Busch <kbusch@kernel.org> Reviewed-by: Jinhao Fan <fanjinhao21s@ict.ac.cn> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-11-01Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into stagingStefan Hajnoczi
Pull request Note that we're still discussing "block/blkio: Make driver nvme-io_uring take a "path" instead of a "filename"". I have sent the pull request now so everything is ready for the soft freeze tomorrow if we decide to go ahead with the patch. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmNgGQkACgkQnKSrs4Gr # c8hLFgf/dnszoHO02hjoJCN2LPAxDalyYKzog+ZU8U5VdzJn2gione1jVlf3Xb0l # mhTgrioSbKLKXavGZTSwWUki/xRgCJMtG3m07EFmMsLX0QiSOIyzLr0DslQawYdZ # FlXyCCyAVTUILz7oUXBqORlfTKsGPHms6nlXQYhitTOsDbPyqbT9nNPKAlfGkqfj # Pwn+oWJmjLC0aARpcrB1bXCMbqQrtZGh4bBgfIXRUJmprWqk227bkFvXNCuXU16x # PC4oH552+6nyQyRxGpHc3o1W/8gqlxU9DTBb5arDUQaDvsDTKVkuGe2HdDI7knAT # /m57/BFVUnA35SYOxX+0piiEbawI6Q== # =UWL7 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 31 Oct 2022 14:50:49 EDT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [ultimate] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [ultimate] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * tag 'block-pull-request' of https://gitlab.com/stefanha/qemu: block/blkio: Make driver nvme-io_uring take a "path" instead of a "filename" block/blkio: Tolerate device size changes block/blkio: Add virtio-blk-vfio-pci BlockDriver Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 10:01:24 +0000