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2020-12-18qdev: Avoid unnecessary DeviceState* variable at set_prop_arraylen()Eduardo Habkost
2020-12-18qdev: Rename qdev_get_prop_ptr() to object_field_prop_ptr()Eduardo Habkost
2020-12-18qdev: Move qdev_prop_tpm declaration to tpm_prop.hEduardo Habkost
2020-12-18qdev: Make qdev_class_add_property() more flexibleEduardo Habkost
2020-12-18qdev: Make PropertyInfo.create return ObjectProperty*Eduardo Habkost
2020-12-18qdev: Move dev->realized check to qdev_property_set()Eduardo Habkost
2020-12-18qdev: Wrap getters and setters in separate helpersEduardo Habkost
2020-12-18qdev: Add name argument to PropertyInfo.create methodEduardo Habkost
2020-12-18qdev: Add name parameter to qdev_class_add_property()Eduardo Habkost
2020-12-18qdev: Avoid using prop->name unnecessarilyEduardo Habkost
2020-12-18qdev: Get just property name at error_set_from_qdev_prop_error()Eduardo Habkost
2020-12-18sparc: Use DEFINE_PROP for nwindows propertyEduardo Habkost
2020-12-18qdev: Reuse DEFINE_PROP in all DEFINE_PROP_* macrosEduardo Habkost
2020-12-18qdev: Move softmmu properties to qdev-properties-system.hEduardo Habkost
2020-12-18Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201...Peter Maydell
2020-12-17riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis
2020-12-17target/riscv: cpu: Set XLEN independently from targetAlistair Francis
2020-12-17target/riscv: csr: Remove compile time XLEN checksAlistair Francis
2020-12-17target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis
2020-12-17target/riscv: cpu: Remove compile time XLEN checksAlistair Francis
2020-12-17target/riscv: Specify the XLEN for CPUsAlistair Francis
2020-12-17target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis
2020-12-17target/riscv: fpu_helper: Match function defs in HELPER macrosAlistair Francis
2020-12-17hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: spike: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: virt: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis
2020-12-17riscv: virt: Remove target macro conditionalsAlistair Francis
2020-12-17riscv: spike: Remove target macro conditionalsAlistair Francis
2020-12-17target/riscv: Add a TYPE_RISCV_CPU_BASE CPUAlistair Francis
2020-12-17hw/riscv: Expand the is 32-bit check to support more CPUsAlistair Francis
2020-12-17intc/ibex_plic: Clear interrupts that occur during claim processAlistair Francis
2020-12-17target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSRAlex Richardson
2020-12-17target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang
2020-12-17hw/core/register.c: Don't use '#' flag of printf formatXinhao Zhang
2020-12-17hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool
2020-12-17hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel
2020-12-17Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request'...Peter Maydell
2020-12-16cpu: Remove unnecessary noop methodsEduardo Habkost
2020-12-16tcg: Make CPUClass.debug_excp_handler optionalEduardo Habkost
2020-12-16tcg: make CPUClass.cpu_exec_* optionalEduardo Habkost
2020-12-16tcg: cpu_exec_{enter,exit} helpersEduardo Habkost
2020-12-16i386: tcg: remove inline from cpu_load_eflagsClaudio Fontana
2020-12-16i386: move TCG cpu class initialization to tcg/Claudio Fontana
2020-12-16x86/cpu: Add AVX512_FP16 cpu featureCathy Zhang
2020-12-16i386: move hyperv_limits initialization to x86_cpu_realizefn()Vitaly Kuznetsov
2020-12-16i386: move hyperv_version_id initialization to x86_cpu_realizefn()Vitaly Kuznetsov
2020-12-16i386: move hyperv_interface_id initialization to x86_cpu_realizefn()Vitaly Kuznetsov
2020-12-16i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()Vitaly Kuznetsov