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2016-06-16qcow2: Implement .bdrv_co_preadv()Kevin Wolf
Reading from qcow2 images is now byte granularity. Most of the affected code in qcow2 actually gets simpler with this change. The only exception is encryption, which is fixed on 512 bytes blocks; in order to keep this working, bs->request_alignment is set for encrypted images. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-06-16qcow2: Work with bytes in qcow2_get_cluster_offset()Kevin Wolf
This patch changes the units that qcow2_get_cluster_offset() uses internally, without touching the interface just yet. This will be done in another patch. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-06-16Merge remote-tracking branch ↵Peter Maydell
'remotes/amit-migration/tags/migration-for-2.7-4' into staging Migration: - Fixes for TLS series - Postcopy: Add stats, fix, test case # gpg: Signature made Thu 16 Jun 2016 05:40:09 BST # gpg: using RSA key 0xEB0B4DFC657EF670 # gpg: Good signature from "Amit Shah <amit@amitshah.net>" # gpg: aka "Amit Shah <amit@kernel.org>" # gpg: aka "Amit Shah <amitshah@gmx.net>" # Primary key fingerprint: 48CA 3722 5FE7 F4A8 B337 2735 1E9A 3B5F 8540 83B6 # Subkey fingerprint: CC63 D332 AB8F 4617 4529 6534 EB0B 4DFC 657E F670 * remotes/amit-migration/tags/migration-for-2.7-4: migration: rename functions to starting migrations migration: fix typos in qapi-schema from latest migration additions Postcopy: Check for support when setting the capability tests: fix libqtest socket timeouts test: Postcopy Postcopy: Add stats on page requests Migration: Split out ram part of qmp_query_migrate Postcopy: Avoid 0 length discards Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-16migration: rename functions to starting migrationsDaniel P. Berrange
Apply the following renames for starting incoming migration: process_incoming_migration -> migration_fd_process_incoming migration_set_incoming_channel -> migration_channel_process_incoming migration_tls_set_incoming_channel -> migration_tls_channel_process_incoming and for starting outgoing migration: migration_set_outgoing_channel -> migration_channel_connect migration_tls_set_outgoing_channel -> migration_tls_channel_connect Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 1464776234-9910-3-git-send-email-berrange@redhat.com Message-Id: <1464776234-9910-3-git-send-email-berrange@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-16migration: fix typos in qapi-schema from latest migration additionsDaniel P. Berrange
Recent migration QAPI enhancements had a few spelling mistakes and also incorrect version number in a few places. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 1464776234-9910-2-git-send-email-berrange@redhat.com Message-Id: <1464776234-9910-2-git-send-email-berrange@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-16Postcopy: Check for support when setting the capabilityDr. David Alan Gilbert
Knowing whether the destination host supports migration with postcopy can be tricky. The destination doesn't need the capability set, however if we set it then use the opportunity to do the test and tell the user/management layer early. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 1465816605-29488-7-git-send-email-dgilbert@redhat.com Message-Id: <1465816605-29488-7-git-send-email-dgilbert@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-16tests: fix libqtest socket timeoutsAndrea Arcangeli
I kept getting timeouts and unix socket accept failures under high load, the patch fixes it. Signed-off-by: Andrea Arcangeli <aarcange@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Message-id: 1465816605-29488-6-git-send-email-dgilbert@redhat.com Message-Id: <1465816605-29488-6-git-send-email-dgilbert@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-16test: PostcopyDr. David Alan Gilbert
This is a postcopy test (x86 only) that actually runs the guest and checks the memory contents. The test runs from an x86 boot block with the hex embedded in the test; the source for this is: ........... .code16 .org 0x7c00 .file "fill.s" .text .globl start .type start, @function start: # at 0x7c00 ? cli lgdt gdtdesc mov $1,%eax mov %eax,%cr0 # Protected mode enable data32 ljmp $8,$0x7c20 .org 0x7c20 .code32 # A20 enable - not sure I actually need this inb $0x92,%al or $2,%al outb %al, $0x92 # set up DS for the whole of RAM (needed on KVM) mov $16,%eax mov %eax,%ds mov $65,%ax mov $0x3f8,%dx outb %al,%dx # bl keeps a counter so we limit the output speed mov $0, %bl mainloop: # Start from 1MB mov $(1024*1024),%eax innerloop: incb (%eax) add $4096,%eax cmp $(100*1024*1024),%eax jl innerloop inc %bl jnz mainloop mov $66,%ax mov $0x3f8,%dx outb %al,%dx jmp mainloop # GDT magic from old (GPLv2) Grub startup.S .p2align 2 /* force 4-byte alignment */ gdt: .word 0, 0 .byte 0, 0, 0, 0 /* -- code segment -- * base = 0x00000000, limit = 0xFFFFF (4 KiB Granularity), present * type = 32bit code execute/read, DPL = 0 */ .word 0xFFFF, 0 .byte 0, 0x9A, 0xCF, 0 /* -- data segment -- * base = 0x00000000, limit 0xFFFFF (4 KiB Granularity), present * type = 32 bit data read/write, DPL = 0 */ .word 0xFFFF, 0 .byte 0, 0x92, 0xCF, 0 gdtdesc: .word 0x27 /* limit */ .long gdt /* addr */ /* I'm a bootable disk */ .org 0x7dfe .byte 0x55 .byte 0xAA ........... and that can be assembled by the following magic: as --32 -march=i486 fill.s -o fill.o objcopy -O binary fill.o fill.boot dd if=fill.boot of=bootsect bs=256 count=2 skip=124 xxd -i bootsect Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Message-id: 1465816605-29488-5-git-send-email-dgilbert@redhat.com Message-Id: <1465816605-29488-5-git-send-email-dgilbert@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-16Postcopy: Add stats on page requestsDr. David Alan Gilbert
On the source, add a count of page requests received from the destination. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Denis V. Lunev <den@openvz.org> Message-id: 1465816605-29488-4-git-send-email-dgilbert@redhat.com Message-Id: <1465816605-29488-4-git-send-email-dgilbert@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-16Migration: Split out ram part of qmp_query_migrateDr. David Alan Gilbert
The RAM section of qmp_query_migrate is reasonably complex and repeated 3 times. Split it out into a helper. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 1465816605-29488-3-git-send-email-dgilbert@redhat.com Reviwed-by: Denis V. Lunev <den@openvz.org> Message-Id: <1465816605-29488-3-git-send-email-dgilbert@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-16Postcopy: Avoid 0 length discardsDr. David Alan Gilbert
The discard code in migration/ram.c would send request for zero length discards in the case where no discards were needed. It doesn't appear to have had any bad effect. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Denis V. Lunev <den@openvz.org> Message-id: 1465816605-29488-2-git-send-email-dgilbert@redhat.com Message-Id: <1465816605-29488-2-git-send-email-dgilbert@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-15Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell
staging X86 queue, 2016-06-14 (v2) # gpg: Signature made Tue 14 Jun 2016 22:29:04 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: target-i386: Consolidate calls of object_property_parse() in x86_cpu_parse_featurestr target-i386: Use cpu_generic_init() in cpu_x86_init() target-i386: Move xcc->kvm_required check to realize time target-i386: Remove assert(kvm_enabled()) from host_x86_cpu_initfn() target-i386: Move features logic that requires CPUState to realize time target-i386: Remove xlevel & hv-spinlocks option fixups target-i386: Implement CPUID[0xB] (Extended Topology Enumeration) pc: Add 2.7 machine target-i386: add Skylake-Client cpu model Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14target-i386: Consolidate calls of object_property_parse() in ↵Eduardo Habkost
x86_cpu_parse_featurestr Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-14target-i386: Use cpu_generic_init() in cpu_x86_init()Igor Mammedov
Now cpu_x86_init() does nothing more or less than duplicating cpu_generic_init() logic. So simplify it by using cpu_generic_init(). Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-14target-i386: Move xcc->kvm_required check to realize timeIgor Mammedov
It will allow to drop custom cpu_x86_init() and use cpu_generic_init() instead, reducing cpu_x86_create() to a simple 3-liner. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-14target-i386: Remove assert(kvm_enabled()) from host_x86_cpu_initfn()Eduardo Habkost
The code will be changed to allow creation of the CPU object and report kvm_required errors only at realizefn, so we need to make the instance_init function more flexible. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-14target-i386: Move features logic that requires CPUState to realize timeIgor Mammedov
Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-14target-i386: Remove xlevel & hv-spinlocks option fixupsEduardo Habkost
The "fixup will be removed in future versions" warnings are present since QEMU 1.7.0, at least, so users should have fixed their scripts and configurations, already. In the case of libvirt users, libvirt doesn't use the "xlevel" option, and already rejects HyperV spinlock retry count < 0xFFF. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-14target-i386: Implement CPUID[0xB] (Extended Topology Enumeration)Radim Krčmář
I looked at a dozen Intel CPU that have this CPUID and all of them always had Core offset as 1 (a wasted bit when hyperthreading is disabled) and Package offset at least 4 (wasted bits at <= 4 cores). QEMU uses more compact IDs and it doesn't make much sense to change it now. I keep the SMT and Core sub-leaves even if there is just one thread/core; it makes the code simpler and there should be no harm. Signed-off-by: Radim Krčmář <rkrcmar@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-14pc: Add 2.7 machineIgor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-14target-i386: add Skylake-Client cpu modelEduardo Habkost
Introduce Skylake-Client cpu mode which inherits the features from Broadwell and supports some additional features that are: MPX, XSAVEC, and XGETBV1. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-14Merge remote-tracking branch 'remotes/sstabellini/tags/xen-20160614-tag' ↵Peter Maydell
into staging Xen 2016/06/14 # gpg: Signature made Tue 14 Jun 2016 16:01:52 BST # gpg: using RSA key 0x894F8F4870E1AE90 # gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" # Primary key fingerprint: D04E 33AB A51F 67BA 07D3 0AEA 894F 8F48 70E1 AE90 * remotes/sstabellini/tags/xen-20160614-tag: xen: Clean up includes xen/blkif: avoid double access to any shared ring request fields Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20160614-2' into staging target-arm queue: * add PMU support for virt machine under KVM * fix reset and migration of TTBCR(S) * add virt-2.7 machine type * QOMify various ARM devices * implement xilinx DisplayPort device * don't permit ARMv8-only Neon insns to work on ARMv7 # gpg: Signature made Tue 14 Jun 2016 16:01:45 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20160614-2: (30 commits) target-arm: Don't permit ARMv8-only Neon insns on ARMv7 arm: xlnx-zynqmp: Add xlnx-dp and xlnx-dpdma introduce xlnx-dp introduce xlnx-dpdma hw/i2c-ddc.c: Implement DDC I2C slave introduce dpcd module introduce aux-bus i2c: Factor our send() and recv() common logic i2c: implement broadcast write i2cbus: remove unused dev field hw/sd: QOM'ify pl181.c hw/dma: QOM'ify pxa2xx_dma.c hw/misc: QOM'ify mst_fpga.c hw/misc: QOM'ify exynos4210_pmu.c hw/misc: QOM'ify arm_l2x0.c hw/gpio: QOM'ify zaurus.c hw/gpio: QOM'ify pl061.c hw/gpio: QOM'ify omap_gpio.c hw/i2c: QOM'ify versatile_i2c.c hw/i2c: QOM'ify omap_i2c.c ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14target-arm: Don't permit ARMv8-only Neon insns on ARMv7Peter Maydell
The Neon instructions VCVTA, VCVTM, VCVTN, VCVTP, VRINTA, VRINTM, VRINTN, VRINTP, VRINTX, and VRINTZ were only introduced with ARMv8, so they need a guard to make them UNDEF if the CPU only supports ARMv7. (We got this right for all the other new-in-v8 insns, but forgot it for these Neon 2-reg-misc ops.) Reported-by: Christophe Lyon <christophe.lyon@linaro.org> Tested-by: Christophe Lyon <christophe.lyon@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465492511-9333-1-git-send-email-peter.maydell@linaro.org
2016-06-14arm: xlnx-zynqmp: Add xlnx-dp and xlnx-dpdmaKONRAD Frederic
This adds the DP and the DPDMA to the Zynq MP platform. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> Message-id: 1465833014-21982-10-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14introduce xlnx-dpKONRAD Frederic
This is the implementation of the DisplayPort. It has an aux-bus to access dpcd and edid. Graphic plane is connected to the channel 3. Video plane is connected to the channel 0. Audio stream are connected to the channels 4 and 5. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1465833014-21982-9-git-send-email-fred.konrad@greensocs.com [PMM: fixed format strings] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14introduce xlnx-dpdmaKONRAD Frederic
This is the implementation of the DPDMA. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> Message-id: 1465833014-21982-8-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/i2c-ddc.c: Implement DDC I2C slavePeter Maydell
Implement an I2C slave which implements DDC and returns the EDID data for an attached monitor. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Message-id: 1465833014-21982-7-git-send-email-fred.konrad@greensocs.com - Rebased on the current master. - Modified for QOM. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> [PMM: actually wire up the vmstate to dc->vmsd] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14introduce dpcd moduleKONRAD Frederic
This introduces dpcd module. It wires on a aux-bus and can be accessed by the driver to get lane-speed, etc. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> Message-id: 1465833014-21982-6-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14introduce aux-busKONRAD Frederic
This introduces a new bus: aux-bus. It contains an address space for aux slaves devices and a bridge to an I2C bus for I2C through AUX transactions. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1465833014-21982-5-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14i2c: Factor our send() and recv() common logicPeter Crosthwaite
Most of the control flow logic between send and recv (error checking etc) is the same. Factor this out into a common send_recv() API. This is then usable by clients, where the control logic for send and receive differs only by a boolean. E.g. if (send) i2c_send(...): else i2c_recv(...); becomes: i2c_send_recv(... , send); Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Message-id: 1465833014-21982-4-git-send-email-fred.konrad@greensocs.com Changes from FK: * Rebased on master. * Rebased on my i2c broadcast patch. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14i2c: implement broadcast writeKONRAD Frederic
This does a write to every slaves when the I2C bus get a write to address 0. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> Message-id: 1465833014-21982-3-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14i2cbus: remove unused dev fieldKONRAD Frederic
The dev field in i2cbus is not used. So just drop it. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> Message-id: 1465833014-21982-2-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/sd: QOM'ify pl181.cxiaoqiang zhao
split the old SysBus init function into an instance_init and a Device realize function Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-13-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/dma: QOM'ify pxa2xx_dma.cxiaoqiang zhao
split the old SysBus init function into an instance_init and a Device realize function Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-12-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/misc: QOM'ify mst_fpga.cxiaoqiang zhao
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-11-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/misc: QOM'ify exynos4210_pmu.cxiaoqiang zhao
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-10-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/misc: QOM'ify arm_l2x0.cxiaoqiang zhao
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-9-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/gpio: QOM'ify zaurus.cxiaoqiang zhao
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-8-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/gpio: QOM'ify pl061.cxiaoqiang zhao
* Merge the pl061_initfn into pl061_init * Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-7-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/gpio: QOM'ify omap_gpio.cxiaoqiang zhao
* Split the old SysBus init into an instance_init and DeviceClass::realize function * Drop the SysBus init function Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-6-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/i2c: QOM'ify versatile_i2c.cxiaoqiang zhao
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-5-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/i2c: QOM'ify omap_i2c.cxiaoqiang zhao
* Split the omap_i2c_init into an instance_init and realize function * Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-4-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/i2c: QOM'ify exynos4210_i2c.cxiaoqiang zhao
* Rename the exynos4210_i2c_realize to exynos4210_i2c_init * Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-3-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/i2c: QOM'ify bitbang_i2c.cxiaoqiang zhao
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-2-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/arm/virt: create the 2.7 machine typeAndrew Jones
Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 1465746713-30414-5-git-send-email-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/arm/virt: introduce DEFINE_VIRT_MACHINE_AS_LATESTAndrew Jones
Create two variants of DEFINE_VIRT_MACHINE. One, just called DEFINE_VIRT_MACHINE, that does not set properties that only the latest machine type should have, and another that does. This will hopefully reduce potential for errors when adding new versions. Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 1465746713-30414-4-git-send-email-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/arm/virt: introduce DEFINE_VIRT_MACHINEAndrew Jones
Use DEFINE_VIRT_MACHINE to generate versioned machine type info. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465746713-30414-3-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/arm/virt: separate versioned type-init codeAndrew Jones
Rename machvirt_info (which is specifically for 2.6 TypeInfo) to machvirt_2_6_info, and separate the type registration of the abstract machine type from the versioned type. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465746713-30414-2-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14target-arm: Fix reset and migration of TTBCR(S)Peter Maydell
Commit 6459b94c26dd666badb3 broke reset and migration of the AArch32 TTBCR(S) register if the guest used non-LPAE page tables. This is because the AArch32 TTBCR register definition is marked as ARM_CP_ALIAS, meaning that the AArch64 variant has to handle migration and reset. Although AArch64 TCR_EL3 doesn't need to care about the mask and base_mask fields, AArch32 may do so, and so we must use the special TTBCR reset and raw write functions to ensure they are set correctly. This doesn't affect TCR_EL2, because the AArch32 equivalent of that is HTCR, which never uses the non-LPAE page table variant. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Pranith Kumar <bobby.prani+qemu@gmail.com> Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org> Message-id: 1465488181-31977-1-git-send-email-peter.maydell@linaro.org
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-25 15:23:56 +0000