aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2016-03-05chardev: Drop useless ChardevDummy typeEric Blake
Commit d0d7708b made ChardevDummy be an empty wrapper type around ChardevCommon. But there is no technical reason for this indirection, so simplify the code by directly using the base type. Also change the fallback assignment to assign u.null rather than u.data, since a future patch will remove the data member of the C struct generated for QAPI unions. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Message-Id: <1457106160-23614-1-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-03-05qapi: Avoid use of 'data' member of QAPI unionsEric Blake
QAPI code generators currently create a 'void *data' member as part of the anonymous union embedded in the C struct corresponding to a QAPI union. However, directly assigning to this member of the union feels a bit fishy, when we can assign to another member of the struct instead. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Message-Id: <1457021813-10704-9-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-03-05ui: Shorten references into InputEventEric Blake
An upcoming patch will alter how simple unions, like InputEvent, are laid out, which will impact all lines of the form 'evt->u.XXX' (expanding it to the longer 'evt->u.XXX.data'). For better legibility in that patch, and less need for line wrapping, it's better to use a temporary variable to reduce the effect of a layout change to just the variable initializations, rather than every reference within an InputEvent. There was one instance in hid.c:hid_pointer_event() where the code was referring to evt->u.rel inside the case label where evt->u.abs is the correct name; thankfully, both members of the union have the same type, so it happened to work, but it is now cleaner. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <1457021813-10704-8-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-03-05util: Shorten references into SocketAddressEric Blake
An upcoming patch will alter how simple unions, like SocketAddress, are laid out, which will impact all lines of the form 'addr->u.XXX' (expanding it to the longer 'addr->u.XXX.data'). For better legibility in that patch, and less need for line wrapping, it's better to use a temporary variable to reduce the effect of a layout change to just the variable initializations, rather than every reference within a SocketAddress. Also, take advantage of some C99 initialization where it makes sense (simplifying g_new0() to g_new()). Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <1457021813-10704-7-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-03-05chardev: Shorten references into ChardevBackendEric Blake
An upcoming patch will alter how simple unions, like ChardevBackend, are laid out, which will impact all lines of the form 'backend->u.XXX' (expanding it to the longer 'backend->u.XXX.data'). For better legibility in that patch, and less need for line wrapping, it's better to use a temporary variable to reduce the effect of a layout change to just the variable initializations, rather than every reference within a ChardevBackend. It doesn't hurt that this also makes the code more consistent: some clients touched here already had a temporary variable but weren't using it. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-By: Daniel P. Berrange <berrange@redhat.com> Message-Id: <1457021813-10704-6-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-03-05qapi: Update docs to match recent generator changesEric Blake
Several commits have been changing the generator, but not updating the docs to match: - The implicit tag member is named "type", not "kind". Screwed up in commit 39a1815. - Commit 9f08c8ec made list types lazy, and thereby dropped UserDefOneList if nothing explicitly uses the list type. - Commit 51e72bc1 switched the parameter order with 'name' occurring earlier. - Commit e65d89bf changed the layout of UserDefOneList. - Prefer the term 'member' over 'field'. - We now expose visit_type_FOO_members() for objects. - etc. Rework the examples to show slightly more output (we don't want to show too much; that's what the testsuite is for), and regenerate the output to match all recent changes. Also, rearrange output to show .h files before .c (understanding the interface first often makes the implementation easier to follow). Reported-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Eric Blake <eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <1457021813-10704-5-git-send-email-eblake@redhat.com>
2016-03-05qapi-visit: Expose visit_type_FOO_members()Eric Blake
Dan Berrange reported a case where he needs to work with a QCryptoBlockOptions union type using the OptsVisitor, but only visit one of the branches of that type (the discriminator is not visited directly, but learned externally). When things were boxed, it was easy: just visit the variant directly, which took care of both allocating the variant and visiting its members, then store that pointer in the union type. But now that things are unboxed, we need a way to visit the members without allocation, done by exposing visit_type_FOO_members() to the user. Before the patch, we had quite a bit of code associated with object_members_seen to make sure that a declaration of the helper was in scope before any use of the function. But now that the helper is public and declared in the header, the .c file no longer needs to worry about topological sorting (the helper is always in scope), which leads to some nice cleanups. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <1457021813-10704-4-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-03-05qapi: Rename 'fields' to 'members' in generated C codeEric Blake
C types and JSON objects don't have fields, but members. We shouldn't gratuitously invent terminology. This patch is a strict renaming of static genarated functions, plus the naming of the dummy filler member for empty structs, before the next patch exposes some of that naming to the rest of the code base. Suggested-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <1457021813-10704-3-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-03-05qapi: Rename 'fields' to 'members' in generatorEric Blake
C types and JSON objects don't have fields, but members. We shouldn't gratuitously invent terminology. This patch is a strict renaming of generator code internals (including testsuite comments), before later patches rename C interfaces. No change to generated code with this patch. Suggested-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <1457021813-10704-2-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-03-04qapi-dealloc: Reduce use outside of generated codeEric Blake
No need to roll our own use of the dealloc visitors when we can just directly use the qapi_free_FOO() functions that do what we want in one line. In net.c, inline net_visit() into its remaining lone caller. After this patch, test-visitor-serialization.c is the only non-generated file that needs to use a dealloc visitor, because it is testing low level aspects of the visitor interface. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <1456262075-3311-2-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-03-04qmp-shell: fix pretty printing of JSON responsesDaniel P. Berrange
Pretty printing of JSON responses is important to be able to understand large responses from query commands in particular. Unfortunately this was broken during the addition of the verbose flag in commit 1ceca07e48ead0dd2e41576c81d40e6a91cafefd Author: John Snow <jsnow@redhat.com> Date: Wed Apr 29 15:14:04 2015 -0400 scripts: qmp-shell: Add verbose flag This is because that change turned the python data structure into a formatted JSON string before the pretty print was given it. So we're just pretty printing a string, which is a no-op. The original pretty printer would output python objects. (QEMU) query-chardev { u'return': [ { u'filename': u'vc', u'frontend-open': False, u'label': u'parallel0'}, { u'filename': u'vc', u'frontend-open': True, u'label': u'serial0'}, { u'filename': u'unix:/tmp/qemp,server', u'frontend-open': True, u'label': u'compat_monitor0'}]} This fixes the problem by switching to outputting pretty formatted JSON text instead. This has the added benefit that the pretty printed output is now valid JSON text. Due to the way the verbose flag was handled, the pretty printing now applies to the command sent, as well as its response: (QEMU) query-chardev { "execute": "query-chardev", "arguments": {} } { "return": [ { "frontend-open": false, "label": "parallel0", "filename": "vc" }, { "frontend-open": true, "label": "serial0", "filename": "vc" }, { "frontend-open": true, "label": "compat_monitor0", "filename": "unix:/tmp/qmp,server" } ] } Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-Id: <1456224706-1591-1-git-send-email-berrange@redhat.com> Tested-by: Kashyap Chamarthy <kchamart@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> [Bonus fix: multiple -p now work] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-03-04Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20160304' into staging target-arm queue: * Correct handling of writes to CPSR from gdbstub in user mode * virt: lift maximum RAM limit to 255GB * sdhci: implement reset * virt: if booting in Secure mode, provide secure-only RAM, make first flash device secure-only, and assume the EL3 boot rom will handle PSCI * bcm2835: use explicit endianness accessors rather than ldl/stl_phys * support big-endian in system mode for ARM * implement SETEND instruction * arm_gic: implement the GICv2 GICC_DIR register * fix SRS bug: only trap from S-EL1 to EL3 if specified mode is Mon # gpg: Signature made Fri 04 Mar 2016 11:38:53 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20160304: (30 commits) target-arm: Only trap SRS from S-EL1 if specified mode is MON hw/intc/arm_gic.c: Implement GICv2 GICC_DIR arm: boot: Support big-endian elfs loader: Add data swap option to load-elf loader: load_elf(): Add doc comment loader: add API to load elf header target-arm: implement BE32 mode in system emulation target-arm: implement setend target-arm: introduce tbflag for endianness target-arm: a64: Add endianness support target-arm: introduce disas flag for endianness target-arm: pass DisasContext to gen_aa32_ld*/st* target-arm: implement SCTLR.EE linux-user: arm: handle CPSR.E correctly in strex emulation linux-user: arm: set CPSR.E/SCTLR.E0E correctly for BE mode arm: cpu: handle BE32 user-mode as BE target-arm: cpu: Move cpu_is_big_endian to header target-arm: implement SCTLR.B, drop bswap_code linux-user: arm: pass env to get_user_code_* linux-user: arm: fix coding style for some linux-user signal functions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: Only trap SRS from S-EL1 if specified mode is MONRalf-Philipp Weinmann
Commit cbc0326b6fb9 caused SRS instructions executed from Secure EL1 to trap to EL3 even if the specified mode was not monitor mode. According to the ARMv8 Architecture reference manual [F6.1.203], ALL of the following conditions need to be met for SRS to trap to EL3: * It is executed at Secure PL1. * The specified mode is monitor mode. * EL3 is using AArch64. Correct the condition governing the trap to EL3 to check the specified mode. Signed-off-by: Ralf-Philipp Weinmann <ralf+devel@comsecuris.com> Message-id: 20160222224251.GA11654@beta.comsecuris.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked comment text to read 'specified mode'; edited commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04hw/intc/arm_gic.c: Implement GICv2 GICC_DIRPeter Maydell
The GICv2 introduces a new CPU interface register GICC_DIR, which allows an OS to split the "priority drop" and "deactivate interrupt" parts of interrupt completion. Implement this register. (Note that the register is at offset 0x1000 in the CPU interface, which means it is on a different 4K page from all the other registers.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1456854176-7813-1-git-send-email-peter.maydell@linaro.org
2016-03-04arm: boot: Support big-endian elfsPeter Crosthwaite
Support ARM big-endian ELF files in system-mode emulation. When loading an elf, determine the endianness mode expected by the elf, and set the relevant CPU state accordingly. With this, big-endian modes are now fully supported via system-mode LE, so there is no need to restrict the elf loading to the TARGET endianness so the ifdeffery on TARGET_WORDS_BIGENDIAN goes away. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fix typo in comments] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04loader: Add data swap option to load-elfPeter Crosthwaite
Some CPUs are of an opposite data-endianness to other components in the system. Sometimes elfs have the data sections layed out with this CPU data-endianness accounting for when loaded via the CPU, so byte swaps (relative to other system components) will occur. The leading example, is ARM's BE32 mode, which is is basically LE with address manipulation on half-word and byte accesses to access the hw/byte reversed address. This means that word data is invariant across LE and BE32. This also means that instructions are still LE. The expectation is that the elf will be loaded via the CPU in this endianness scheme, which means the data in the elf is reversed at compile time. As QEMU loads via the system memory directly, rather than the CPU, we need a mechanism to reverse elf data endianness to implement this possibility. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04loader: load_elf(): Add doc commentPeter Crosthwaite
Document the usage of load_elf() for clarity on current features. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04loader: add API to load elf headerPeter Crosthwaite
Add an API to load an elf header header from a file. Populates a buffer with the header contents, as well as a boolean for whether the elf is 64b or not. Both arguments are optional. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: Fix typo in comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: implement BE32 mode in system emulationPaolo Bonzini
System emulation only has a little-endian target; BE32 mode is implemented by adjusting the low bits of the address for every byte and halfword load and store. 64-bit accesses flip the low and high words. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [PC changes: * rebased against master (Jan 2016) ] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: implement setendPaolo Bonzini
Since this is not a high-performance path, just use a helper to flip the E bit and force a lookup in the hash table since the flags have changed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: introduce tbflag for endiannessPeter Crosthwaite
Introduce a tbflags for endianness, set based upon the CPUs current endianness. This in turn propagates through to the disas endianness flag. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: a64: Add endianness supportPeter Crosthwaite
Set the dc->mo_endianness flag for AA64 and use it in all ldst ops. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: introduce disas flag for endiannessPaolo Bonzini
Introduce a disas flag for setting the CPU data endianness. This allows control of the endianness from the CPU state rather than hard-coding it to TARGET_WORDS_BIGENDIAN. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [ PC changes: * Split off as new patch from original: "target-arm: introduce tbflag for CPSR.E" * Wrote commit message from scratch ] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: pass DisasContext to gen_aa32_ld*/st*Paolo Bonzini
We'll need the DisasContext in the next patch to retrieve the desired endianness, so pass it as a whole to gen_aa32_ld*/st*. Unfortunately we cannot let those functions call get_mem_index, because of user-mode load/store instructions. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [ PC changes: * Fix long lines ] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: implement SCTLR.EEPeter Crosthwaite
Implement SCTLR.EE bit which controls data endianess for exceptions and page table translations. SCTLR.EE is mirrored to the CPSR.E bit on exception entry. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04linux-user: arm: handle CPSR.E correctly in strex emulationPaolo Bonzini
Now that CPSR.E is set correctly, prepare for when setend will be able to change it; bswap data in and out of strex manually by comparing SCTLR.B, CPSR.E and TARGET_WORDS_BIGENDIAN (we do not have the luxury of using TCGMemOps). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [ PC changes: * Moved SCTLR/CPSR logic to arm_cpu_data_is_big_endian ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04linux-user: arm: set CPSR.E/SCTLR.E0E correctly for BE modePeter Crosthwaite
If doing big-endian linux-user mode, set both the CPSR.E and SCTLR.E0E bits. This sets big-endian mode for data accesses. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04arm: cpu: handle BE32 user-mode as BEPeter Crosthwaite
endian with address manipulations on subword accesses (to give the illusion of BE). But user-mode cannot tell the difference and is already implemented as straight BE. So handle the difference in the endianess query, where USER mode is BE and system is not. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: cpu: Move cpu_is_big_endian to headerPeter Crosthwaite
There is a CPU data endianness test that is used to drive the virtio_big_endian test. Move this up to the header so it can be more generally used for endian tests. The KVM specific cpu_syncronize_state call is left behind in the virtio specific function. Rename it arm_cpu-data_is_big_endian() to more accurately capture that this is for data accesses only. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini
bswap_code is a CPU property of sorts ("is the iside endianness the opposite way round to TARGET_WORDS_BIGENDIAN?") but it is not the actual CPU state involved here which is SCTLR.B (set for BE32 binaries, clear for BE8). Replace bswap_code with SCTLR.B, and pass that to arm_ld*_code. The next patches will make data fetches honor both SCTLR.B and CPSR.E appropriately. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [PC changes: * rebased on master (Jan 2016) * s/TARGET_USER_ONLY/CONFIG_USER_ONLY * Use bswap_code() for disas_set_info() instead of raw sctlr_b ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04linux-user: arm: pass env to get_user_code_*Paolo Bonzini
This matches the idiom used by get_user_data_* later in the series, and will help when bswap_code will be replaced by SCTLR.B. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04linux-user: arm: fix coding style for some linux-user signal functionsPaolo Bonzini
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04bcm2835_mbox/property: replace ldl_phys/stl_phys with endian-specific accessesAndrew Baumann
PMM pointed out that ldl_phys and stl_phys are dependent on the CPU's endianness, whereas device model code should be independent of it. This changes the relevant Raspberry Pi devices to explicitly call the little-endian variants. Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456880233-22568-1-git-send-email-Andrew.Baumann@microsoft.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04hw/arm/virt: Assume EL3 boot rom will handle PSCI if one is providedPeter Maydell
If the user passes us an EL3 boot rom, then it is going to want to implement the PSCI interface itself. In this case, disable QEMU's internal PSCI implementation so it does not get in the way, and instead start all CPUs in an SMP configuration at once (the boot rom will catch them all and pen up the secondaries until needed). The boot rom code is also responsible for editing the device tree to include any necessary information about its own PSCI implementation before eventually passing it to a NonSecure guest. (This "start all CPUs at once" approach is what both ARM Trusted Firmware and UEFI expect, since it is what the ARM Foundation Model does; the other approach would be to provide some emulated hardware for "start the secondaries" but this is simplest.) This is a compatibility break, but I don't believe that anybody was using a secure boot ROM with an SMP configuration. Such a setup would be somewhat broken since there was nothing preventing nonsecure guest code from calling the QEMU PSCI function to start up a secondary core in a way that completely bypassed the secure world. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-id: 1456853976-7592-1-git-send-email-peter.maydell@linaro.org
2016-03-04hw/arm/virt: Make first flash device Secure-only if booting securePeter Maydell
If the virt board is started with the 'secure' property set to request a Secure setup, then make the first flash device be visible only to the Secure world. This is a breaking change, but I don't expect it to be noticed by anybody, because running TZ-aware guests isn't common and those guests are generally going to be booting from the flash and implicitly expecting their Non-secure guests to not touch it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-5-git-send-email-peter.maydell@linaro.org
2016-03-04hw/arm/virt: Load bios image to MemoryRegion, not physaddrPeter Maydell
If we're loading a BIOS image into the first flash device, load it into the flash's memory region specifically, not into the physical address where the flash resides. This will make a difference when the flash might be in the Secure address space rather than the Nonsecure one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-4-git-send-email-peter.maydell@linaro.org
2016-03-04loader: Add load_image_mr() to load ROM image to a MemoryRegionPeter Maydell
Add a new function load_image_mr(), which behaves like load_image_targphys() except that it loads the ROM image to a specified MemoryRegion rather than to a specified physical address. This is useful when a ROM blob needs to be loaded to a particular flash or ROM device but the address of that device in the machine's address space is not known. (For instance, ROMs in devices, or ROMs which might exist in a different address space to the system address space.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2016-03-04hw/arm/virt: Provide a secure-only RAM if booting in Secure modePeter Maydell
If we're booting in Secure mode, provide a secure-only RAM (just 16MB) so that secure firmware has somewhere to run from that won't be accessible to the Non-secure guest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-2-git-send-email-peter.maydell@linaro.org
2016-03-04sdhci: Implement DeviceClass resetPeter Maydell
The sdhci device was missing a DeviceClass reset method; implement it. Poweron reset looks the same as reset commanded by the guest via the device registers, apart from modelling of the rpi 'pending insert interrupt on powerup' quirk. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456493044-10025-3-git-send-email-peter.maydell@linaro.org
2016-03-04sd.c: Handle NULL block backend in sd_get_inserted()Peter Maydell
The sd.c SD card emulation code can be in a state where the SDState BlockBackend pointer is NULL; this is treated as "card not present". Add a missing check to sd_get_inserted() so that we don't segfault in this situation. (This could be provoked by the guest writing to the SDHCI register to do a reset on a xilinx-zynq-a9 board; it will also happen at startup when sdhci implements its DeviceClass reset method.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1456493044-10025-2-git-send-email-peter.maydell@linaro.org
2016-03-04virt: Lift the maximum RAM limit from 30GB to 255GBPeter Maydell
The virt board restricts guests to only 30GB of RAM. This is a hangover from the vexpress-a15 board, and there's no inherent reason for it. 30GB is smaller than you might reasonably want to provision a VM for on a beefy server machine. Raise the limit to 255GB. We choose 255GB because the available space we currently have below the 1TB boundary is up to the 512GB mark, but we don't want to paint ourselves into a corner by assigning it all to RAM. So we make half of it available for RAM, with the 256GB..512GB range available for future non-RAM expansion purposes. If we need to provide more RAM to VMs in the future then we need to: * allocate a second bank of RAM starting at 2TB and working up * fix the DT and ACPI table generation code in QEMU to correctly report two split lumps of RAM to the guest * fix KVM in the host kernel to allow guests with >40 bit address spaces The last of these is obviously the trickiest, but it seems reasonable to assume that anybody configuring a VM with a quarter of a terabyte of RAM will be doing it on a host with more than a terabyte of physical address space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1456402182-11651-1-git-send-email-peter.maydell@linaro.org
2016-03-04target-arm: Correct handling of writes to CPSR mode bits from gdb in usermodePeter Maydell
In helper.c the expression (env->uncached_cpsr & CPSR_M) != CPSR_USER is always true; the right hand side was supposed to be ARM_CPU_MODE_USR (an error in commit cb01d391). Since the incorrect expression was always true, this just meant that commit cb01d391 had no effect. However simply changing the RHS here would reveal a logic error: if the mode is USR we wish to completely ignore the attempt to set the mode bits, which means that we must clear the CPSR_M bits from mask to avoid the uncached_cpsr bits being updated at the end of the function. Move the condition into the correct place in the code, fix its RHS constant, and add a comment about the fact that we must be doing a gdbstub write if we're in user mode. Fixes: https://bugs.launchpad.net/qemu/+bug/1550503 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1456764438-30015-1-git-send-email-peter.maydell@linaro.org
2016-03-03Merge remote-tracking branch 'remotes/amit-virtio-rng/tags/rng-for-2.6-1' ↵Peter Maydell
into staging rng: - implement a request queue for rng-random so multiple guest requests don't result in vq buffers getting forgotten - remove unused request cancellation code - a VM with multiple vq buffers, when migrated, could get in a situation where not all buffers are handed back to the guest. This is now fixed. # gpg: Signature made Thu 03 Mar 2016 12:18:54 GMT using RSA key ID 854083B6 # gpg: Good signature from "Amit Shah <amit@amitshah.net>" # gpg: aka "Amit Shah <amit@kernel.org>" # gpg: aka "Amit Shah <amitshah@gmx.net>" * remotes/amit-virtio-rng/tags/rng-for-2.6-1: virtio-rng: ask for more data if queue is not fully drained rng: add request queue support to rng-random rng: move request queue cleanup from RngEgd to RngBackend rng: move request queue from RngEgd to RngBackend rng: remove the unused request cancellation code MAINTAINERS: Add an entry for the include/sysemu/rng*.h files Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-03virtio-rng: ask for more data if queue is not fully drainedLadi Prosek
This commit effectively reverts: commit 4621c1768ef5d12171cca2aa1473595ecb9f1c9e Author: Amit Shah <amit.shah@redhat.com> Date: Wed Nov 21 11:21:19 2012 +0530 virtio-rng: remove extra request for entropy but instead of calling virtio_rng_process unconditionally, it first checks to see if the queue is empty as a little bit of optimization. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456998514-19271-1-git-send-email-lprosek@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-03rng: add request queue support to rng-randomLadi Prosek
Requests are now created in the RngBackend parent class and the code path is shared by both rng-egd and rng-random. This commit fixes the rng-random implementation which processed only one request at a time and simply discarded all but the most recent one. In the guest this manifested as delayed completion of reads from virtio-rng, i.e. a read was completed only after another read was issued. By switching rng-random to use the same request queue as rng-egd, the unsafe stack-based allocation of the entropy buffer is eliminated and replaced with g_malloc. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456994238-9585-5-git-send-email-lprosek@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-03rng: move request queue cleanup from RngEgd to RngBackendLadi Prosek
RngBackend is now in charge of cleaning up the linked list on instance finalization. It also exposes a function to finalize individual RngRequest instances, called by its child classes. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456994238-9585-4-git-send-email-lprosek@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-03rng: move request queue from RngEgd to RngBackendLadi Prosek
The 'requests' field now lives in the RngBackend parent class. There are no functional changes in this commit. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456994238-9585-3-git-send-email-lprosek@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-03rng: remove the unused request cancellation codeLadi Prosek
rng_backend_cancel_requests had no callers and none of the code deleted in this commit ever ran. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456994238-9585-2-git-send-email-lprosek@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-03MAINTAINERS: Add an entry for the include/sysemu/rng*.h filesThomas Huth
These headers are used by the virtio-rng and rng backends code, so they should be listed in the same section in MAINTAINERS, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456404260-26928-1-git-send-email-thuth@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-01Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell
into staging # gpg: Signature made Tue 01 Mar 2016 15:48:04 GMT using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/tracing-pull-request: trace: Add a proper API to manage auto-generated events from the 'tcg' property trace: Add 'vcpu' event property to trace guest vCPU typedefs: Add CPUState trace: Add helper function to cast event arguments tcg: Move definition of type TCGv tcg: Add type for vCPU pointers trace: Remove unnecessary intermediate event copies trace: Extend API to manage event arguments vl: fix tracing initialization trace: use addresses instead of offsets in memory tracepoints trace: split subpage MMIOs into their own trace events. trace: docs: "simple" backend does support strings trace: drop trailing empty strings Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-22 09:51:55 +0000