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2021-09-01softfloat: Remove assertion preventing silencing of NaN in default-NaN modePeter Maydell
In commit a777d6033447a we added an assertion to parts_silence_nan() that prohibits calling float*_silence_nan() when in default-NaN mode. This ties together a property of the output ("do we generate a default NaN when the result is a NaN?") with an operation on an input ("silence this input NaN"). It's true that most of the time when in default-NaN mode you won't need to silence an input NaN, because you can just produce the default NaN as the result instead. But some functions like float*_maxnum() are defined to be able to work with quiet NaNs, so silencing an input SNaN is still reasonable. In particular, the upcoming implementation of MVE VMAXNMV would fall over this assertion if we didn't delete it. Delete the assertion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-01target/arm: Implement MVE fp-with-scalar VFMA, VFMASPeter Maydell
Implement the MVE fp-with-scalar VFMA and VFMAS insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-01target/arm: Implement MVE scalar fp insnsPeter Maydell
Implement the MVE scalar floating point insns VADD, VSUB and VMUL. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-01target/arm: Implement MVE VMAXNMA and VMINNMAPeter Maydell
Implement the MVE VMAXNMA and VMINNMA insns; these are 2-operand, but the destination register must be the same as one of the source registers. We defer the decode of the size in bit 28 to the individual insn patterns rather than doing it in the format, because otherwise we would have a single insn pattern that overlapped with two groups (eg VMAXNMA with the VMULH_S and VMULH_U groups). Having two insn patterns per insn seems clearer than a complex multilevel nesting of overlapping and non-overlapping groups. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/arm: Implement MVE VCMUL and VCMLAPeter Maydell
Implement the MVE VCMUL and VCMLA insns. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/arm: Implement MVE VFMA and VFMSPeter Maydell
Implement the MVE VFMA and VFMS insns. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/arm: Implement MVE VCADDPeter Maydell
Implement the MVE VCADD insn. Note that here the size bit is the opposite sense to the other 2-operand fp insns. We don't check for the sz == 1 && Qd == Qm UNPREDICTABLE case, because that would mean we can't use the DO_2OP_FP macro in translate-mve.c. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNMPeter Maydell
Implement more simple 2-operand floating point MVE insns. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/arm: Implement MVE VADD (floating-point)Peter Maydell
Implement the MVE VADD (floating-point) insn. Handling of this is similar to the 2-operand integer insns, except that we must take care to only update the floating point exception status if the least significant bit of the predicate mask for each element is active. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01hw: Add compat machines for 6.2Yanan Wang
Add 6.2 machine types for arm/i440fx/q35/s390x/spapr. Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleansPhilippe Mathieu-Daudé
Quoting Peter Maydell: These MEMTX_* aren't from the memory transaction API functions; they're just being used by gicd_readl() and friends as a way to indicate a success/failure so that the actual MemoryRegionOps read/write fns like gicv3_dist_read() can log a guest error. Arguably this is a bit of a misuse of the MEMTX_* constants and perhaps we should have gicd_readl etc return a bool instead. Follow his suggestion and replace the MEMTX_* constants by boolean values, simplifying a bit the gicv3_dist_read() / gicv3_dist_write() handlers. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20210826180704.2131949-3-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffixPhilippe Mathieu-Daudé
QEMU load/store API (docs/devel/loads-stores.rst) uses the 'q' suffix for 64-bit accesses. Rename the current 'll' suffix to have the GIC dist accessors better match the rest of the codebase. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20210826180704.2131949-2-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01hw/arm/raspi: Remove deprecated raspi2/raspi3 aliasesPhilippe Mathieu-Daudé
Remove the raspi2/raspi3 machine aliases, deprecated since commit 155e1c82ed0. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210827060815.2384760-3-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01tests: Remove uses of deprecated raspi2/raspi3 machine namesPhilippe Mathieu-Daudé
Commit 155e1c82ed0 deprecated the raspi2/raspi3 machine names. Use the recommended new names: raspi2b and raspi3b. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-id: 20210827060815.2384760-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20210901-2' into staging First RISC-V PR for QEMU 6.2 - Add a config for Shakti UART - Fixup virt flash node - Don't override users supplied ISA version - Fixup some CSR accesses - Use g_strjoinv() for virt machine PLIC string config - Fix an overflow in the SiFive CLINT - Add 64-bit register access helpers - Replace tcg_const_* with direct constant usage # gpg: Signature made Wed 01 Sep 2021 03:08:48 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210901-2: (33 commits) target/riscv: Use {get,dest}_gpr for RVV target/riscv: Tidy trans_rvh.c.inc target/riscv: Use {get,dest}_gpr for RVD target/riscv: Use {get,dest}_gpr for RVF target/riscv: Use gen_shift_imm_fn for slli_uw target/riscv: Use {get,dest}_gpr for RVA target/riscv: Reorg csr instructions target/riscv: Fix hgeie, hgeip target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation target/riscv: Use {get, dest}_gpr for integer load/store target/riscv: Use get_gpr in branches target/riscv: Use extracts for sraiw and srliw target/riscv: Use DisasExtend in shift operations target/riscv: Add DisasExtend to gen_unary target/riscv: Move gen_* helpers for RVB target/riscv: Move gen_* helpers for RVM target/riscv: Use gen_arith for mulh and mulhu target/riscv: Remove gen_arith_div* target/riscv: Add DisasExtend to gen_arith* target/riscv: Introduce DisasExtend and new helpers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson
Remove gen_get_gpr, as the function becomes unused. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-25-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Tidy trans_rvh.c.incRichard Henderson
Exit early if check_access fails. Split out do_hlv, do_hsv, do_hlvx subroutines. Use dest_gpr, get_gpr in the new subroutines. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-24-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use {get,dest}_gpr for RVDRichard Henderson
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-23-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use {get,dest}_gpr for RVFRichard Henderson
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-22-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson
Always use tcg_gen_deposit_z_tl; the special case for shamt >= 32 is handled there. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-21-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use {get,dest}_gpr for RVARichard Henderson
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-20-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson
Introduce csrr and csrw helpers, for read-only and write-only insns. Note that we do not properly implement this in riscv_csrrw, in that we cannot distinguish true read-only (rs1 == 0) from any other zero write_mask another source register -- this should still raise an exception for read-only registers. Only issue gen_io_start for CF_USE_ICOUNT. Use ctx->zero for csrrc. Use get_gpr and dest_gpr. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-19-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Fix hgeie, hgeipRichard Henderson
We failed to write into *val for these read functions; replace them with read_zero. Only warn about unsupported non-zero value when writing a non-zero value. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-18-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson
We distinguish write-only by passing ret_value as NULL. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-17-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-16-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use get_gpr in branchesRichard Henderson
Narrow the scope of t0 in trans_jalr. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-15-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use extracts for sraiw and srliwRichard Henderson
These operations can be done in one instruction on some hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-14-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson
These operations are greatly simplified by ctx->w, which allows us to fold gen_shiftw into gen_shift. Split gen_shifti into gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-13-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson
Use ctx->w for ctpopw, which is the only one that can re-use the generic algorithm for the narrow operation. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-12-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson
Move these helpers near their use by the trans_* functions within insn_trans/trans_rvb.c.inc. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-11-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson
Move these helpers near their use by the trans_* functions within insn_trans/trans_rvm.c.inc. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-10-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use gen_arith for mulh and mulhuRichard Henderson
Split out gen_mulh and gen_mulhu and use the common helper. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-9-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson
Use ctx->w and the enhanced gen_arith function. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-8-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson
Most arithmetic does not require extending the inputs. Exceptions include division, comparison and minmax. Begin using ctx->w, which allows elimination of gen_addw, gen_subw, gen_mulw. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-7-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Introduce DisasExtend and new helpersRichard Henderson
Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force tcg globals into temps, returning a constant 0 for $zero as source and a new temp for $zero as destination. Introduce ctx->w for simplifying word operations, such as addw. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-6-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson
We will require the context to handle RV64 word operations. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Clean up division helpersRichard Henderson
Utilize the condition in the movcond more; this allows some of the setcond that were feeding into movcond to be removed. Do not write into source1 and source2. Re-name "condN" to "tempN" and use the temporaries for more than holding conditions. Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-4-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01tests/tcg/riscv64: Add test for divisionRichard Henderson
Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-3-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson
Replace uses of tcg_const_* with the allocate and free close together. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-2-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01hw/registerfields: Use 64-bit bitfield for FIELD_DP64Joe Komlodi
If we have a field that's wider than 32-bits, we need a data type wide enough to be able to create the bitfield used to deposit the value. Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1626805903-162860-3-git-send-email-joe.komlodi@xilinx.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01hw/core/register: Add more 64-bit utilitiesJoe Komlodi
We already have some utilities to handle 64-bit wide registers, so this just adds some more for: - Initializing 64-bit registers - Extracting and depositing to an array of 64-bit registers Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1626805903-162860-2-git-send-email-joe.komlodi@xilinx.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp()David Hoppenbrouwers
`muldiv64` would overflow in cases where the final 96-bit value does not fit in a `uint64_t`. This would result in small values that cause an interrupt to be triggered much sooner than intended. The overflow can be detected in most cases by checking if the new value is smaller than the previous value. If the final result is larger than `diff` it is either correct or it doesn't matter as it is effectively infinite anyways. `next` is an `uint64_t` value, but `timer_mod` takes an `int64_t`. This resulted in high values such as `UINT64_MAX` being converted to `-1`, which caused an immediate timer interrupt. By limiting `next` to `INT64_MAX` no overflow will happen while the timer will still be effectively set to "infinitely" far in the future. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/493 Signed-off-by: David Hoppenbrouwers <david@salt-inc.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210827152324.5201-1-david@salt-inc.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell
In the riscv virt machine init function, We assemble a string plic_hart_config which is a comma-separated list of N copies of the VIRT_PLIC_HART_CONFIG string. The code that does this has a misunderstanding of the strncat() length argument. If the source string is too large strncat() will write a maximum of length+1 bytes (length bytes from the source string plus a trailing NUL), but the code here assumes that it will write only length bytes at most. This isn't an actual bug because the code has correctly precalculated the amount of memory it needs to allocate so that it will never be too small (i.e. we could have used plain old strcat()), but it does mean that the code looks like it has a guard against accidental overrun when it doesn't. Rewrite the string handling here to use the glib g_strjoinv() function, which means we don't need to do careful accountancy of string lengths, and makes it clearer that what we're doing is "create a comma-separated string". Fixes: Coverity 1460752 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210812144647.10516-1-peter.maydell@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Add User CSRs read-only checkLIU Zhiwei
For U-mode CSRs, read-only check is also needed. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210810014552.4884-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Don't wrongly override isa versionLIU Zhiwei
For some cpu, the isa version has already been set in cpu init function. Thus only override the isa version when isa version is not set, or users set different isa version explicitly by cpu parameters. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Correct a comment in riscv_csrrw()Bin Meng
When privilege check fails, RISCV_EXCP_ILLEGAL_INST is returned, not -1 (RISCV_EXCP_NONE). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210807141025.31808-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01hw/riscv: virt: Move flash node to rootBin Meng
The flash is not inside the SoC, so it's inappropriate to put it under the /soc node. Move it to root instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210807035641.22449-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01hw/char: Add config for shakti uartVijai Kumar K
Use a dedicated UART config(CONFIG_SHAKTI_UART) to select shakti uart. Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210731190229.137483-1-vijai@behindbytes.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-08-31Merge remote-tracking branch 'remotes/marcandre/tags/clip-pull-request' into ↵Peter Maydell
staging # gpg: Signature made Tue 31 Aug 2021 14:29:27 BST # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * remotes/marcandre/tags/clip-pull-request: ui/vdagent: add a migration blocker ui/gtk-clipboard: emit release clipboard events ui/vdagent: send release when no clipboard owner ui/gtk-clipboard: use qemu_clipboard_info helper ui/vdagent: send empty clipboard when unhandled ui/vdagent: use qemu_clipboard_info helper ui/vdagent: use qemu_clipboard_peer_release helper ui/vdagent: split clipboard recv message handling ui/vdagent: reset outbuf on disconnect ui/vdagent: disconnect handlers and reset state on finalize ui/clipboard: release owned grabs on unregister ui/clipboard: add qemu_clipboard_peer_release() helper ui/clipboard: add qemu_clipboard_peer_owns() helper ui/clipboard: add helper to retrieve current clipboard ui/gtk-clipboard: fix clipboard enum typo ui/gtk-clipboard: use existing macros ui/vdagent: remove copy-pasta comment ui/vdagent: fix leak on error path Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-31ui/vdagent: add a migration blockerMarc-André Lureau
The current implementation lacks migration support. After migration, vdagent support will be broken (even after a restart of the daemons). Let's try to fix it in 6.2. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210805135715.857938-19-marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-23 12:50:42 +0000