slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2019-05-28	MAINTAINERS: update for semihostings new home	Alex Bennée
2019-05-28	target/mips: convert UHI_plog to use common semihosting code	Alex Bennée
2019-05-28	target/mips: only build mips-semi for softmmu	Alex Bennée
2019-05-28	target/arm: correct return values for WRITE/READ in arm-semi	Alex Bennée
2019-05-28	target/arm: add LOG_UNIMP messages to arm-semi	Alex Bennée
2019-05-28	target/arm: use the common interface for WRITE0/WRITEC in arm-semi	Alex Bennée
2019-05-28	target/arm: fixup some of the commentary for arm-semi	Alex Bennée
2019-05-28	semihosting: enable chardev backed output for console	Alex Bennée
2019-05-28	semihosting: implement a semihosting console	Alex Bennée
2019-05-28	semihosting: introduce CONFIG_SEMIHOSTING	Alex Bennée
2019-05-28	semihosting: move semihosting configuration into its own directory	Alex Bennée
2019-05-26	BootLinuxSshTest: Test some userspace commands on Malta	Philippe Mathieu-Daudé
2019-05-26	target/mips: realign comments to fix checkpatch warnings	Jules Irenge
2019-05-26	target/mips: add or remove space to fix checkpatch errors	Jules Irenge
2019-05-26	linux-user: fix __NR_semtimedop undeclared error	Laurent Vivier
2019-05-26	mips: Decide to map PAGE_EXEC in map_address	Jakub Jermář
2019-05-26	target/mips: Refactor and fix INSERT.<B\|H\|W\|D> instructions	Mateja Marjanovic
2019-05-26	target/mips: Refactor and fix COPY_U.<B\|H\|W> instructions	Mateja Marjanovic
2019-05-26	target/mips: Refactor and fix COPY_S.<B\|H\|W\|D> instructions	Mateja Marjanovic
2019-05-26	target/mips: Fix MSA instructions ST.<B\|H\|W\|D> on big endian host	Mateja Marjanovic
2019-05-26	target/mips: Fix MSA instructions LD.<B\|H\|W\|D> on big endian host	Mateja Marjanovic
2019-05-26	target/mips: Make the results of MOD_<U\|S>.<B\|H\|W\|D> the same as on hardware	Mateja Marjanovic
2019-05-26	target/mips: Make the results of DIV_<U\|S>.<B\|H\|W\|D> the same as on hardware	Mateja Marjanovic
2019-05-24	target/riscv: Only flush TLB if SATP.ASID changes	Jonathan Behrens
2019-05-24	target/riscv: More accurate handling of `sip` CSR	Jonathan Behrens
2019-05-24	target/riscv: Add checks for several RVC reserved operands	Richard Henderson
2019-05-24	target/riscv: Add the HGATP register masks	Alistair Francis
2019-05-24	target/riscv: Add the HSTATUS register masks	Alistair Francis
2019-05-24	target/riscv: Add Hypervisor CSR macros	Alistair Francis
2019-05-24	target/riscv: Allow setting mstatus virtulisation bits	Alistair Francis
2019-05-24	target/riscv: Add the MPV and MTL mstatus bits	Alistair Francis
2019-05-24	target/riscv: Improve the scause logic	Alistair Francis
2019-05-24	target/riscv: Trigger interrupt on MIP update asynchronously	Alistair Francis
2019-05-24	target/riscv: Mark privilege level 2 as reserved	Alistair Francis
2019-05-24	riscv: spike: Add a generic spike machine	Alistair Francis
2019-05-24	target/riscv: Deprecate the generic no MMU CPUs	Alistair Francis
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis
2019-05-24	target/riscv: Create settable CPU properties	Alistair Francis
2019-05-24	riscv: virt: Allow specifying a CPU via commandline	Alistair Francis
2019-05-24	linux-user/riscv: Add the CPU type as a comment	Alistair Francis
2019-05-24	target/riscv: Remove unused include of riscv_htif.h for virt board riscv	Jonathan Behrens
2019-05-24	target/riscv: Remove spaces from register names	Richard Henderson
2019-05-24	target/riscv: Split gen_arith_imm into functional and temp	Richard Henderson
2019-05-24	target/riscv: Split RVC32 and RVC64 insns into separate files	Richard Henderson
2019-05-24	target/riscv: Use pattern groups in insn16.decode	Richard Henderson
2019-05-24	target/riscv: Merge argument decode for RVC shifti	Richard Henderson
2019-05-24	target/riscv: Merge argument sets for insn32 and insn16	Richard Henderson
2019-05-24	target/riscv: Use --static-decode for decodetree	Richard Henderson
2019-05-24	target/riscv: Name the argument sets for all of insn32 formats	Richard Henderson
2019-05-24	RISC-V: fix single stepping over ret and other branching instructions	Fabien Chouteau