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2018-10-29linux-user: Read and set FP ABI value from MIPS abiflagsStefan Markovic
Set fp_abi and interp_fp_abi values to current fp_abi value read from MIPS.abiflags. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-10-29linux-user: Extract MIPS abiflags from ELF fileStefan Markovic
Read MIPS.abiflags section from ELF file into Mips_elf_abiflags_v0 struct. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-10-29linux-user: Extend image_info struct with MIPS fp_abi and interp_fp_abi fieldsStefan Markovic
Add MIPS specific image_info struct fields fp_abi and interp_fp_abi to store executable and interpreter fp_abi values (based on kernel struct arch_elf_state in mips/include/asm/elf.h). Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-10-29elf: Define MIPS_ABI_FP_UNKNOWN macroStefan Markovic
Add MIPS_ABI_FP_UNKNOWN as QEMU internal value to represent unknown fp_abi (based on kernel mips/include/asm/elf.h definition) Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-10-29target/mips: Amend MXU ASE overview noteAleksandar Markovic
Add prefix, suffix, operation descriptions, and other corrections and amendments to the comment that describes MXU ASE. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Move MXU_EN check one level higherAleksandar Markovic
Move MXU_EN check to the main MXU decoding function, to avoid code repetition. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instructions S32LDD and S32LDDRCraig Janeczek
Add support for emulating the S32LDD and S32LDDR MXU instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSUCraig Janeczek
Adds support for emulating the Q8MUL and Q8MULSU MXU instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instruction D16MACCraig Janeczek
Add support for emulating the D16MAC MXU instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instruction D16MULCraig Janeczek
Add support for emulating the D16MUL MXU instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instruction S8LDDCraig Janeczek
Add support for emulating the S8LDD MXU instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switchAleksandar Markovic
Move MUL, S32M2I, S32I2M handling out of switch. These are all instructions that do not depend on MXU_EN flag of MXU_CR. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instructions S32I2M and S32M2ICraig Janeczek
Add support for emulating the S32I2M and S32M2I MXU instructions. This commit also contains utility functions for reading/writing to MXU registers. This is required for overall MXU instruction support. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of non-MXU MULL within MXU decoding engineCraig Janeczek
Add emulation of non-MXU MULL within MXU decoding engine. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add bit encoding for MXU operand getting pattern 'optn3'Craig Janeczek
Add bit encoding for MXU operand getting pattern 'optn3'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add bit encoding for MXU operand getting pattern 'optn2'Craig Janeczek
Add bit encoding for MXU operand getting pattern 'optn2'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'Aleksandar Markovic
Add bit encoding for MXU execute 2-bit add/subtract pattern 'eptn2'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'Craig Janeczek
Add bit encoding for MXU accumulate add/subtract 2-bit pattern 'aptn2'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'Aleksandar Markovic
Add bit encoding for MXU accumulate add/subtract 1-bit pattern 'aptn1'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add MXU decoding engineAleksandar Markovic
Add MXU decoding engine: add handlers for all instruction pools, and main decode handler. The handlers, for now, for the purpose of this patch, contain only sceleton in the form of a single switch statement. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add and integrate MXU decoding engine placeholderAleksandar Markovic
Provide the placeholder and add the invocation logic for MXU decoding engine. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Amend MXU instruction opcodesAleksandar Markovic
Amend MXU instruction opcodes. Pool04 is actually only instruction OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit subfield 'aptn1'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Define a bit for MXU in insn_flagsCraig Janeczek
Define a bit for MXU in insn_flags. This is the first non-MIPS (third party) ASE supported in QEMU for MIPS, so it is placed in the section "bits 56-63: vendor-specific ASEs". Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Introduce MXU registersCraig Janeczek
Define and initialize the 16 MXU registers - 15 general computational register, and 1 control register). There is also a zero register, but it does not have any corresponding variable. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder casesAleksandar Markovic
Coverity found two fallthroughs that miss break statement. Fix them. Revieved-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-27Merge remote-tracking branch 'remotes/famz/tags/testing-pull-request' into ↵Peter Maydell
staging Testing patches One fix for mingw build and some improvements in VM based testing, many thanks to Paolo and Phil. # gpg: Signature made Fri 26 Oct 2018 15:15:13 BST # gpg: using RSA key CA35624C6A9171C6 # gpg: Good signature from "Fam Zheng <famz@redhat.com>" # Primary key fingerprint: 5003 7CB7 9706 0F76 F021 AD56 CA35 624C 6A91 71C6 * remotes/famz/tags/testing-pull-request: tests/vm: Do not abuse parallelism when HOST != TARGET architecture tests/vm: Do not use -enable-kvm if HOST != TARGET architecture tests/vm: Let kvm_available() work in cross environments tests/vm: Add a BaseVM::arch property tests/vm: Display remaining seconds to wait for a VM to start tests/vm: Do not use the -smp option with a single cpu tests/vm: Do not abuse parallelism when KVM is not available tests/vm: Extract the kvm_available() handy function tests: docker: update test-mingw for GTK+ 2.0 removal Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-26Merge remote-tracking branch ↵Peter Maydell
'remotes/amarkovic/tags/mips-queue-oct-2018-part-3' into staging MIPS queue for October 2018 - part 3 # gpg: Signature made Thu 25 Oct 2018 21:14:02 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-oct-2018-part-3: target/mips: Add disassembler support for nanoMIPS target/mips: Implement emulation of nanoMIPS EVA instructions target/mips: Add nanoMIPS CRC32 instruction pool Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-26tests/vm: Do not abuse parallelism when HOST != TARGET architecturePhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-9-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests/vm: Do not use -enable-kvm if HOST != TARGET architecturePhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-8-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests/vm: Let kvm_available() work in cross environmentsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-7-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests/vm: Add a BaseVM::arch propertyPhilippe Mathieu-Daudé
The 'arch' property gives a hint on which architecture the guest image runs. This can be use to select the correct QEMU binary path. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-6-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests/vm: Display remaining seconds to wait for a VM to startPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-5-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests/vm: Do not use the -smp option with a single cpuPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-4-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests/vm: Do not abuse parallelism when KVM is not availablePhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-3-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests/vm: Extract the kvm_available() handy functionPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-2-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests: docker: update test-mingw for GTK+ 2.0 removalPaolo Bonzini
--with-gtkabi does not exist anymore; remove it from the configure invocation. Fixes: 89d85cde75143325205e332dd97bf1bb8402d7c1 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1539886203-33670-1-git-send-email-pbonzini@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-25target/mips: Add disassembler support for nanoMIPSAleksandar Markovic
Add disassembler support for nanoMIPS. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Matthew Fortune <matthew.fortune@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-25target/mips: Implement emulation of nanoMIPS EVA instructionsDimitrije Nikolic
Implement emulation of nanoMIPS EVA instructions. They are all part of P.LS.E0 instruction pool, or one of its subpools. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-25target/mips: Add nanoMIPS CRC32 instruction poolAleksandar Markovic
Add nanoMIPS CRC32 instruction pool. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-25Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine queue, 2018-10-25 * sysbus init/realize cleanups (Cédric Le Goater, Philippe Mathieu-Daudé) * memory-device refactoring (David Hildenbrand) * -smp: deprecate incorrect CPUs topology (Igor Mammedov) * -numa parsing cleanups (Markus Armbruster) * Fix hostmem-file memory leak (Zhang Yi) * Typo fix (Li Qiang) # gpg: Signature made Thu 25 Oct 2018 14:31:46 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: (43 commits) net: xgmac: convert SysBus init method to a realize method net: stellaris_enet: add a reset method net: stellaris_enet: convert SysBus init method to a realize method net: smc91c111: convert SysBus init method to a realize method net: opencores_eth: convert SysBus init method to a realize method net: mipsnet: convert SysBus init method to a realize method net: milkymist_minimac2: convert SysBus init method to a realize method net: lance: convert SysBus init method to a realize method net: lan9118: convert SysBus init method to a realize method net: etraxfs_eth: add a reset method net: etraxfs_eth: convert SysBus init method to a realize method memory-device: trace when pre_plugging/plugging/unplugging memory-device: complete factoring out unplug handling memory-device: complete factoring out plug handling memory-device: complete factoring out pre_plug handling memory-device: add device class function set_addr() memory-device: drop get_region_size() memory-device: factor out get_memory_region() from pc-dimm memory-device: add and use memory_device_get_region_size() memory-device: document MemoryDeviceClass ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-25Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' ↵Peter Maydell
into staging First RISC-V Patch Set for the 3.1 Soft Freeze This pull request contains a handful of patches that have been floating around various trees for a while but haven't made it upstream. These patches all appear quite safe. They're all somewhat independent from each other: * One refactors our IRQ management function to allow multiple interrupts to be raised an once. This patch has no functional difference. * Cleaning up the op_helper/cpu_helper split. This patch has no functional difference. * Updates to various constants to keep them in sync with the latest ISA specification and to remove some non-standard bits that snuck in. * A fix for a memory leak in the PLIC driver. * A fix to our device tree handling to avoid provinging a NULL string. I've given this my standard test: building the port, booting a Fedora root filesytem on the latest Linux tag, and then shutting down that image. Essentially I'm just following the QEMU RISC-V wiki page's instructions. Everything looks fine here. We have a lot more outstanding patches so I'll definately be submitting another PR for the soft freeze. # gpg: Signature made Wed 17 Oct 2018 21:17:52 BST # gpg: using RSA key EF4CA1502CCBAB41 # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/riscv/tags/riscv-for-master-3.1-sf0: RISC-V: Don't add NULL bootargs to device-tree RISC-V: Add missing free for plic_hart_config RISC-V: Update CSR and interrupt definitions RISC-V: Move non-ops from op_helper to cpu_helper RISC-V: Allow setting and clearing multiple irqs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24Merge remote-tracking branch ↵Peter Maydell
'remotes/berrange/tags/qcrypto-next-pull-request' into staging Improve performance of XTS cipher mode impl The XTS cipher mode performance is approximately doubled and test coverage is improved. # gpg: Signature made Wed 24 Oct 2018 19:05:08 BST # gpg: using RSA key BE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/qcrypto-next-pull-request: crypto: add testing for unaligned buffers with XTS cipher mode crypto: refactor XTS cipher mode test suite crypto: annotate xts_tweak_encdec as inlineable crypto: convert xts_mult_x to use xts_uint128 type crypto: convert xts_tweak_encdec to use xts_uint128 type crypto: introduce a xts_uint128 data type crypto: remove code duplication in tweak encrypt/decrypt crypto: expand algorithm coverage for cipher benchmark Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24crypto: add testing for unaligned buffers with XTS cipher modeDaniel P. Berrangé
Validate that the XTS cipher mode will correctly operate with plain text, cipher text and IV buffers that are not 64-bit aligned. Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: refactor XTS cipher mode test suiteDaniel P. Berrangé
The current XTS test overloads two different tests in a single function making the code a little hard to follow. Split it into distinct test cases. Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: annotate xts_tweak_encdec as inlineableDaniel P. Berrangé
Encouraging the compiler to inline xts_tweak_encdec increases the performance for xts-aes-128 when built with gcrypt: Encrypt: 545 MB/s -> 580 MB/s Decrypt: 568 MB/s -> 602 MB/s Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: convert xts_mult_x to use xts_uint128 typeDaniel P. Berrangé
Using 64-bit arithmetic increases the performance for xts-aes-128 when built with gcrypt: Encrypt: 355 MB/s -> 545 MB/s Decrypt: 362 MB/s -> 568 MB/s Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: convert xts_tweak_encdec to use xts_uint128 typeDaniel P. Berrangé
Using 64-bit arithmetic increases the performance for xts-aes-128 when built with gcrypt: Encrypt: 272 MB/s -> 355 MB/s Decrypt: 275 MB/s -> 362 MB/s Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: introduce a xts_uint128 data typeDaniel P. Berrangé
The new type is designed to allow use of 64-bit arithmetic instead of operating 1-byte at a time. The following patches will use this to improve performance. Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: remove code duplication in tweak encrypt/decryptDaniel P. Berrangé
The tweak encrypt/decrypt functions are identical except for the comments, so can be merged. Profiling data shows that the compiler is in fact already merging the two merges in the object files. Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: expand algorithm coverage for cipher benchmarkDaniel P. Berrangé
Add testing coverage for AES with XTS, ECB and CTR modes Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
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