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QEMU is a generic and open source machine & userspace emulator and virtualizer
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2022-01-10
python: update type hints for mypy 0.930
John Snow
2022-01-10
Python/aqmp: fix type definitions for mypy 0.920
John Snow
2022-01-10
python/aqmp: use absolute import statement
John Snow
2022-01-10
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-7.0-pull-request' ...
Peter Maydell
2022-01-09
target/m68k: don't word align SP in stack frame if M68K_FEATURE_UNALIGNED_DAT...
Mark Cave-Ayland
2022-01-09
macfb: fix VRAM dirty memory region logging
Mark Cave-Ayland
2022-01-09
q800: fix segfault with invalid MacROM
Laurent Vivier
2022-01-09
hw: m68k: Add virt compat machine type for 7.0
Laurent Vivier
2022-01-08
Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu into staging
Richard Henderson
2022-01-07
Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into s...
Richard Henderson
2022-01-07
bsd-user: add arm target build
Warner Losh
2022-01-07
bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE
Warner Losh
2022-01-07
bsd-user/arm/signal.c: arm get_ucontext_sigreturn
Warner Losh
2022-01-07
bsd-user/arm/signal.c: arm set_mcontext
Warner Losh
2022-01-07
bsd-user/arm/signal.c: arm get_mcontext
Warner Losh
2022-01-07
bsd-user/arm/signal.c: arm set_sigtramp_args
Warner Losh
2022-01-07
bsd-user/arm/target_arch_signal.h: Define size of *context_t
Warner Losh
2022-01-07
bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signals
Warner Losh
2022-01-07
bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack
Warner Losh
2022-01-07
bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl
Warner Losh
2022-01-07
bsd-user/arm/target_arch_elf.h: arm get hwcap
Warner Losh
2022-01-07
bsd-user/arm/target_arch_elf.h: arm defines for ELF
Warner Losh
2022-01-07
bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread
Warner Losh
2022-01-07
bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm
Warner Losh
2022-01-07
bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space
Warner Losh
2022-01-07
bsd-user/arm/target_arch_reg.h: Implement core dump register copying
Warner Losh
2022-01-07
bsd-user/arm/target_arch_cpu.h: Implement system call dispatch
Warner Losh
2022-01-07
bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions
Warner Losh
2022-01-07
bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions
Warner Losh
2022-01-07
bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation
Warner Losh
2022-01-07
bsd-user/arm/target_arch_cpu.h: Implement target_cpu_clone_regs
Warner Losh
2022-01-07
bsd-user/arm/target_arch_cpu.h: CPU Loop definitions
Warner Losh
2022-01-07
bsd-user/arm/target_arch_cpu.c: Target specific TLS routines
Warner Losh
2022-01-07
bsd-user/arm/target_syscall.h: Add copyright and update name
Warner Losh
2022-01-07
bsd-user/arm/target_arch_sysarch.h: Use consistent include guards
Warner Losh
2022-01-07
bsd-user/target_os_signal.h: Move signal prototypes to target_os_ucontext.h
Warner Losh
2022-01-07
bsd-user/x86_64: Move functions into signal.c
Warner Losh
2022-01-07
bsd-user/x86_64/target_arch_signal.h: Fill in mcontext_t
Warner Losh
2022-01-07
bsd-user/x86_64/target_arch_signal.h: use new target_os_ucontext.h
Warner Losh
2022-01-07
bsd-user/x86_64/target_arch_signal.h: Remove target_sigcontext
Warner Losh
2022-01-07
bsd-user/i386: Move the inlines into signal.c
Warner Losh
2022-01-07
bsd-user/i386/target_arch_signal.h: Update mcontext_t to match FreeBSD
Warner Losh
2022-01-07
bsd-user/i386/target_arch_signal.h: use new target_os_ucontext.h
Warner Losh
2022-01-07
bsd-user/i386/target_arch_signal.h: Remove target_sigcontext
Warner Losh
2022-01-07
bsd-user: create a per-arch signal.c file
Warner Losh
2022-01-07
bsd-user/freebsd: Create common target_os_ucontext.h file
Warner Losh
2022-01-07
bsd-user/mips*: Remove mips support
Warner Losh
2022-01-08
target/riscv: Implement the stval/mtval illegal instruction
Alistair Francis
2022-01-08
target/riscv: Fixup setting GVA
Alistair Francis
2022-01-08
target/riscv: Set the opcode in DisasContext
Alistair Francis
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