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2021-02-12migration: dirty-bitmap: Use struct for alias map inner membersPeter Krempa
Currently the alias mapping hash stores just strings of the target objects internally. In further patches we'll be adding another member which will need to be stored in the map so pass a copy of the whole BitmapMigrationBitmapAlias QAPI struct into the map. Signed-off-by: Peter Krempa <pkrempa@redhat.com> Message-Id: <fc5f27e1fe16cb75e08a248c2d938de3997b9bfb.1613150869.git.pkrempa@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: adjust long lines] Signed-off-by: Eric Blake <eblake@redhat.com>
2021-02-11Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20210211-1' into staging target-arm queue: * Correctly initialize MDCR_EL2.HPMN * versal: Use nr_apu_cpus in favor of hard coding 2 * accel/tcg: Add URL of clang bug to comment about our workaround * Add support for FEAT_DIT, Data Independent Timing * Remove GPIO from unimplemented NPCM7XX * Fix SCR RES1 handling * Don't migrate CPUARMState.features # gpg: Signature made Thu 11 Feb 2021 19:56:40 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210211-1: target/arm: Correctly initialize MDCR_EL2.HPMN hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 accel/tcg: Add URL of clang bug to comment about our workaround arm: Update infocenter.arm.com URLs target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate target/arm: Add support for FEAT_DIT, Data Independent Timing hw/arm: Remove GPIO from unimplemented NPCM7XX target/arm: Fix SCR RES1 handling target/arm: Don't migrate CPUARMState.features Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-11target/arm: Correctly initialize MDCR_EL2.HPMNDaniel Müller
When working with performance monitoring counters, we look at MDCR_EL2.HPMN as part of the check whether a counter is enabled. This check fails, because MDCR_EL2.HPMN is reset to 0, meaning that no counters are "enabled" for < EL2. That's in violation of the Arm specification, which states that > On a Warm reset, this field [MDCR_EL2.HPMN] resets to the value in > PMCR_EL0.N That's also what a comment in the code acknowledges, but the necessary adjustment seems to have been forgotten when support for more counters was added. This change fixes the issue by setting the reset value to PMCR.N, which is four. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-11hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2Edgar E. Iglesias
Use nr_apu_cpus in favor of hard coding 2. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210210142048.3125878-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-11Merge remote-tracking branch 'remotes/nvme/tags/nvme-fixes-pull-request' ↵Peter Maydell
into staging Two small fixes for regressions reported by Alexander Graf and Bin Meng. v2: spotted one bug in the error handling. # gpg: Signature made Thu 11 Feb 2021 15:19:30 GMT # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * remotes/nvme/tags/nvme-fixes-pull-request: hw/block/nvme: fix error handling in nvme_ns_realize hw/block/nvme: Fix a build error in nvme_get_feature() hw/block/nvme: fix legacy namespace registration Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-11hw/block/nvme: fix error handling in nvme_ns_realizeKlaus Jensen
nvme_ns_realize passes errp to nvme_register_namespaces, but then try to prepend errp with local_err. Just remove the local_err and use errp directly. Fixes: 15d024d4aa9b ("hw/block/nvme: split setup and register for namespace") Cc: Minwoo Im <minwoo.im.dev@gmail.com> Reviewed-by: Minwoo Im <minwoo.im.dev@gmail.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2021-02-11hw/block/nvme: Fix a build error in nvme_get_feature()Bin Meng
Current QEMU HEAD nvme.c does not compile with the default GCC 5.4 on a Ubuntu 16.04 host: hw/block/nvme.c:3242:9: error: ‘result’ may be used uninitialized in this function [-Werror=maybe-uninitialized] trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); ^ hw/block/nvme.c:3150:14: note: ‘result’ was declared here uint32_t result; ^ Explicitly initialize the result to fix it. Fixes: aa5e55e3b07e ("hw/block/nvme: open code for volatile write cache") Fixes: Coverity CID 1446371 Signed-off-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2021-02-11hw/block/nvme: fix legacy namespace registrationKlaus Jensen
Moving namespace registration to the nvme-ns realization function had the unintended side-effect of breaking legacy namespace registration. Fix this. Fixes: 15d024d4aa9b ("hw/block/nvme: split setup and register for namespace") Reported-by: Alexander Graf <agraf@csgraf.de> Cc: Minwoo Im <minwoo.im.dev@gmail.com> Tested-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Minwoo Im <minwoo.im.dev@gmail.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2021-02-11accel/tcg: Add URL of clang bug to comment about our workaroundPeter Maydell
In cpu_exec() we have a longstanding workaround for compilers which do not correctly implement the part of the sigsetjmp()/siglongjmp() spec which requires that local variables which are not changed between the setjmp and the longjmp retain their value. I recently ran across the upstream clang bug report for this; add a link to it to the comment describing the workaround, and generally expand the comment, so that we have a reasonable chance in future of understanding why it's there and determining when we can remove it, assuming clang eventually fixes the bug. Remove the /* buggy compiler */ comments on the #else and #endif: they don't add anything to understanding and are somewhat misleading since they're sandwiching the code path for *non*-buggy compilers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20210129130330.30820-1-peter.maydell@linaro.org
2021-02-11arm: Update infocenter.arm.com URLsPeter Maydell
Update infocenter.arm.com URLs for various pieces of Arm documentation to the new developer.arm.com equivalents. (There is a redirection in place from the old URLs, but we might as well update our comments in case the redirect ever disappears in future.) This patch covers all the URLs which are not MPS2/SSE-200/IoTKit related (those are dealt with in a different patch). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210205171456.19939-1-peter.maydell@linaro.org
2021-02-11target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPURebecca Cran
Enable FEAT_DIT for the "max" 32-bit CPU. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210208065700.19454-5-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-11target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPURebecca Cran
Enable FEAT_DIT for the "max" AARCH64 CPU. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210208065700.19454-4-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-11target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstateRebecca Cran
cpsr has been treated as being the same as spsr, but it isn't. Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate. This allows us to add support for CPSR_DIT, adding helper functions to merge SPSR_ELx to and from CPSR. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210208065700.19454-3-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-11target/arm: Add support for FEAT_DIT, Data Independent TimingRebecca Cran
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required feature for ARMv8.4. Since virtual machine execution is largely nondeterministic and TCG is outside of the security domain, it's implemented as a NOP. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210208065700.19454-2-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-11hw/arm: Remove GPIO from unimplemented NPCM7XXHao Wu
NPCM7XX GPIO devices have been implemented in hw/gpio/npcm7xx-gpio.c. So we removed them from the unimplemented devices list. Reviewed-by: Doug Evans<dje@google.com> Reviewed-by: Tyrong Ting<kfting@nuvoton.com> Signed-off-by: Hao Wu<wuhaotsh@google.com> Message-id: 20210129005845.416272-2-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-11target/arm: Fix SCR RES1 handlingMike Nawrocki
The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them to 1 only when there is no support for AArch32 at EL1 or above. The reset value will be 0x30 only if the CPU is AArch64-only; if there is support for AArch32 at EL1 or above, it will be reset to 0. Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32 is supported at EL1 or above. Signed-off-by: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210203165552.16306-2-michael.nawrocki@gtri.gatech.edu Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-11target/arm: Don't migrate CPUARMState.featuresAaron Lindsay
As feature flags are added or removed, the meanings of bits in the `features` field can change between QEMU versions, causing migration failures. Additionally, migrating the field is not useful because it is a constant function of the CPU being used. Fixes: LP:1914696 Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Tested-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-10Merge remote-tracking branch ↵Peter Maydell
'remotes/stefanha-gitlab/tags/block-pull-request' into staging Pull request v4: * Add PCI_EXPRESS Kconfig dependency to fix s390x in "multi-process: setup PCI host bridge for remote device" [Philippe and Thomas] # gpg: Signature made Wed 10 Feb 2021 09:26:14 GMT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha-gitlab/tags/block-pull-request: (27 commits) docs: fix Parallels Image "dirty bitmap" section multi-process: perform device reset in the remote process multi-process: Retrieve PCI info from remote process multi-process: create IOHUB object to handle irq multi-process: Synchronize remote memory multi-process: PCI BAR read/write handling for proxy & remote endpoints multi-process: Forward PCI config space acceses to the remote process multi-process: add proxy communication functions multi-process: introduce proxy object multi-process: setup memory manager for remote device multi-process: Associate fd of a PCIDevice with its object multi-process: Initialize message handler in remote device multi-process: define MPQemuMsg format and transmission functions io: add qio_channel_readv_full_all_eof & qio_channel_readv_full_all helpers io: add qio_channel_writev_full_all helper multi-process: setup a machine object for remote device process multi-process: setup PCI host bridge for remote device multi-process: Add config option for multi-process QEMU memory: alloc RAM from file at offset multi-process: add configure and usage information ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-10Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-20210210' ↵Peter Maydell
into staging ppc patch queue for 20201-02-10 Here's the latest batch of patches for the ppc target and machine types. Highlights are: * Several fixes for E500 from Bin Meng * Fixes and cleanups for PowerNV from Cédric Le Goater * Assorted other fixes and cleanups # gpg: Signature made Wed 10 Feb 2021 06:16:53 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.0-20210210: target/ppc: Add E500 L2CSR0 write helper hw/net: fsl_etsec: Reverse the RCTRL.RSF logic hw/ppc: e500: Fill in correct <clock-frequency> for the serial nodes hw/ppc: e500: Use a macro for the platform clock frequency ppc/pnv: Set default RAM size to 1 GB spapr_numa.c: fix ibm,max-associativity-domains calculation spapr_numa.c: create spapr_numa_initial_nvgpu_numa_id() helper spapr: move spapr_machine_using_legacy_numa() to spapr_numa.c ppc/pnv: Introduce a LPC FW memory region attribute to map the PNOR ppc/pnv: Remove default disablement of the PNOR contents ppc/pnv: Discard internal BMC initialization when BMC is external ppc/pnv: Simplify pnv_bmc_create() ppc/pnv: Use skiboot addresses to load kernel and ramfs ppc/xive: Add firmware bit when dumping the ENDs ppc/pnv: Add trace events for PCI event notification target/ppc: Remove unused MMU definitions spapr: Adjust firmware path of PCI devices spapr.c: add 'name' property for hotplugged CPUs nodes spapr.c: use g_auto* with 'nodename' in CPU DT functions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-10docs: fix Parallels Image "dirty bitmap" sectionDenis V. Lunev
Original specification says that l1 table size if 64 * l1_size, which is obviously wrong. The size of the l1 entry is 64 _bits_, not bytes. Thus 64 is to be replaces with 8 as specification says about bytes. There is also minor tweak, field name is renamed from l1 to l1_table, which matches with the later text. Signed-off-by: Denis V. Lunev <den@openvz.org> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-id: 20210128171313.2210947-1-den@openvz.org CC: Stefan Hajnoczi <stefanha@redhat.com> CC: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> [Replace the original commit message "docs: fix mistake in dirty bitmap feature description" as suggested by Eric Blake. --Stefan] Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: perform device reset in the remote processElena Ufimtseva
Perform device reset in the remote process when QEMU performs device reset. This is required to reset the internal state (like registers, etc...) of emulated devices Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 7cb220a51f565dc0817bd76e2f540e89c2d2b850.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: Retrieve PCI info from remote processJagannathan Raman
Retrieve PCI configuration info about the remote device and configure the Proxy PCI object based on the returned information Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 85ee367bbb993aa23699b44cfedd83b4ea6d5221.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: create IOHUB object to handle irqJagannathan Raman
IOHUB object is added to manage PCI IRQs. It uses KVM_IRQFD ioctl to create irqfd to injecting PCI interrupts to the guest. IOHUB object forwards the irqfd to the remote process. Remote process uses this fd to directly send interrupts to the guest, bypassing QEMU. Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 51d5c3d54e28a68b002e3875c59599c9f5a424a1.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: Synchronize remote memoryJagannathan Raman
Add ProxyMemoryListener object which is used to keep the view of the RAM in sync between QEMU and remote process. A MemoryListener is registered for system-memory AddressSpace. The listener sends SYNC_SYSMEM message to the remote process when memory listener commits the changes to memory, the remote process receives the message and processes it in the handler for SYNC_SYSMEM message. Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 04fe4e6a9ca90d4f11ab6f59be7652f5b086a071.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: PCI BAR read/write handling for proxy & remote endpointsJagannathan Raman
Proxy device object implements handler for PCI BAR writes and reads. The handler uses BAR_WRITE/BAR_READ message to communicate to the remote process with the BAR address and value to be written/read. The remote process implements handler for BAR_WRITE/BAR_READ message. Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: a8b76714a9688be5552c4c92d089bc9e8a4707ff.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: Forward PCI config space acceses to the remote processElena Ufimtseva
The Proxy Object sends the PCI config space accesses as messages to the remote process over the communication channel Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: d3c94f4618813234655356c60e6f0d0362ff42d6.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: add proxy communication functionsElena Ufimtseva
Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: d54edb4176361eed86b903e8f27058363b6c83b3.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: introduce proxy objectElena Ufimtseva
Defines a PCI Device proxy object as a child of TYPE_PCI_DEVICE. Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: b5186ebfedf8e557044d09a768846c59230ad3a7.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: setup memory manager for remote deviceJagannathan Raman
SyncSysMemMsg message format is defined. It is used to send file descriptors of the RAM regions to remote device. RAM on the remote device is configured with a set of file descriptors. Old RAM regions are deleted and new regions, each with an fd, is added to the RAM. Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 7d2d1831d812e85f681e7a8ab99e032cf4704689.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: Associate fd of a PCIDevice with its objectJagannathan Raman
Associate the file descriptor for a PCIDevice in remote process with DeviceState object. Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: f405a2ed5d7518b87bea7c59cfdf334d67e5ee51.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: Initialize message handler in remote deviceJagannathan Raman
Initializes the message handler function in the remote process. It is called whenever there's an event pending on QIOChannel that registers this function. Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 99d38d8b93753a6409ac2340e858858cda59ab1b.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: define MPQemuMsg format and transmission functionsElena Ufimtseva
Defines MPQemuMsg, which is the message that is sent to the remote process. This message is sent over QIOChannel and is used to command the remote process to perform various tasks. Define transmission functions used by proxy and by remote. Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 56ca8bcf95195b2b195b08f6b9565b6d7410bce5.1611938319.git.jag.raman@oracle.com [Replace struct iovec send[2] = {0} with {} to make clang happy as suggested by Peter Maydell <peter.maydell@linaro.org>. --Stefan] Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10io: add qio_channel_readv_full_all_eof & qio_channel_readv_full_all helpersElena Ufimtseva
Adds qio_channel_readv_full_all_eof() and qio_channel_readv_full_all() to read both data and FDs. Refactors existing code to use these helpers. Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Acked-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: b059c4cc0fb741e794d644c144cc21372cad877d.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10io: add qio_channel_writev_full_all helperElena Ufimtseva
Adds qio_channel_writev_full_all() to transmit both data and FDs. Refactors existing code to use this helper. Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 480fbf1fe4152495d60596c9b665124549b426a5.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: setup a machine object for remote device processJagannathan Raman
x-remote-machine object sets up various subsystems of the remote device process. Instantiate PCI host bridge object and initialize RAM, IO & PCI memory regions. Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: c537f38d17f90453ca610c6b70cf3480274e0ba1.1611938319.git.jag.raman@oracle.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10multi-process: setup PCI host bridge for remote deviceJagannathan Raman
PCI host bridge is setup for the remote device process. It is implemented using remote-pcihost object. It is an extension of the PCI host bridge setup by QEMU. Remote-pcihost configures a PCI bus which could be used by the remote PCI device to latch on to. Signed-off-by: Jagannathan Raman <jag.raman@oracle.com> Signed-off-by: John G Johnson <john.g.johnson@oracle.com> Signed-off-by: Elena Ufimtseva <elena.ufimtseva@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 0871ba857abb2eafacde07e7fe66a3f12415bfb2.1611938319.git.jag.raman@oracle.com [Added PCI_EXPRESS condition in hw/remote/Kconfig since remote-pcihost needs PCIe. This solves "make check" failure on s390x. Fix suggested by Philippe Mathieu-Daudé <philmd@redhat.com> and Thomas Huth <thuth@redhat.com>. --Stefan] Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2021-02-10target/ppc: Add E500 L2CSR0 write helperBin Meng
Per EREF 2.0 [1] chapter 3.11.2: The following bits in L2CSR0 (exists in the e500mc/e5500/e6500 core): - L2FI (L2 cache flash invalidate) - L2FL (L2 cache flush) - L2LFC (L2 cache lock flash clear) when set, a cache operation is initiated by hardware, and these bits will be cleared when the operation is complete. Since we don't model cache in QEMU, let's add a write helper to emulate the cache operations completing instantly. [1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREFRM.pdf Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <1612925152-20913-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10hw/net: fsl_etsec: Reverse the RCTRL.RSF logicBin Meng
Per MPC8548ERM [1] chapter 14.5.3.4.1: When RCTRL.RSF is 1, frames less than 64 bytes are accepted upon a DA match. But currently QEMU does the opposite. This commit reverses the RCTRL.RSF testing logic to match the manual. Due to the reverse of the logic, certain guests may potentially break if they don't program eTSEC to have RCTRL.RSF bit set. When RCTRL.RSF is 0, short frames are silently dropped, however as of today both slirp and tap networking do not pad short frames (e.g.: an ARP packet) to the minimum frame size of 60 bytes. So ARP requests will be dropped, preventing the guest from becoming visible on the network. The same issue was reported on e1000 and vmxenet3 before, see: commit 78aeb23eded2 ("e1000: Pad short frames to minimum size (60 bytes)") commit 40a87c6c9b11 ("vmxnet3: Pad short frames to minimum size (60 bytes)") [1] https://www.nxp.com/docs/en/reference-manual/MPC8548ERM.pdf Fixes: eb1e7c3e5146 ("Add Enhanced Three-Speed Ethernet Controller (eTSEC)") Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <1612923021-19746-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10hw/ppc: e500: Fill in correct <clock-frequency> for the serial nodesBin Meng
At present the <clock-frequency> property of the serial node is populated with value zero. U-Boot's ns16550 driver is not happy about this, so let's fill in a meaningful value. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612362288-22216-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10hw/ppc: e500: Use a macro for the platform clock frequencyBin Meng
At present the platform clock frequency is using a magic number. Convert it to a macro and use it everywhere. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612362288-22216-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10ppc/pnv: Set default RAM size to 1 GBCédric Le Goater
The memory layout of the PowerNV machine is defined as : #define KERNEL_LOAD_BASE ((void *)0x20000000) #define KERNEL_LOAD_SIZE 0x08000000 #define INITRAMFS_LOAD_BASE KERNEL_LOAD_BASE + KERNEL_LOAD_SIZE #define INITRAMFS_LOAD_SIZE 0x08000000 #define SKIBOOT_BASE 0x30000000 #define SKIBOOT_SIZE 0x01c10000 #define CPU_STACKS_BASE (SKIBOOT_BASE + SKIBOOT_SIZE) #define STACK_SHIFT 15 #define STACK_SIZE (1 << STACK_SHIFT) The overall size of the CPU stacks is (max PIR + 1) * 32K and the machine easily reaches 800MB of minimum required RAM. Any value below will result in a skiboot crash : [ 0.034949905,3] MEM: Partial overlap detected between regions: [ 0.034959039,3] MEM: ibm,firmware-stacks [0x31c10000-0x3a450000] (new) [ 0.034968576,3] MEM: ibm,firmware-allocs-memory@0 [0x31c10000-0x38400000] [ 0.034980367,3] Out of memory adding skiboot reserved areas [ 0.035074945,3] *********************************************** [ 0.035093627,3] < assert failed at core/mem_region.c:1129 > [ 0.035104247,3] . [ 0.035108025,3] . [ 0.035111651,3] . [ 0.035115231,3] OO__) [ 0.035119198,3] <"__/ [ 0.035122980,3] ^ ^ Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210129111719.790692-1-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10spapr_numa.c: fix ibm,max-associativity-domains calculationDaniel Henrique Barboza
The current logic for calculating 'maxdomain' making it a sum of numa_state->num_nodes with spapr->gpu_numa_id. spapr->gpu_numa_id is used as a index to determine the next available NUMA id that a given NVGPU can use. The problem is that the initial value of gpu_numa_id, for any topology that has more than one NUMA node, is equal to numa_state->num_nodes. This means that our maxdomain will always be, at least, twice the amount of existing NUMA nodes. This means that a guest with 4 NUMA nodes will end up with the following max-associativity-domains: rtas/ibm,max-associativity-domains 00000004 00000008 00000008 00000008 00000008 This overtuning of maxdomains doesn't go unnoticed in the guest, being detected in SLUB during boot: dmesg | grep SLUB [ 0.000000] SLUB: HWalign=128, Order=0-3, MinObjects=0, CPUs=4, Nodes=8 SLUB is detecting 8 total nodes, with 4 nodes being online. This patch fixes ibm,max-associativity-domains by considering the amount of NVGPUs NUMA nodes presented in the guest, instead of just spapr->gpu_numa_id. Reported-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210128174213.1349181-4-danielhb413@gmail.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10spapr_numa.c: create spapr_numa_initial_nvgpu_numa_id() helperDaniel Henrique Barboza
We'll need to check the initial value given to spapr->gpu_numa_id when building the rtas DT, so put it in a helper for easier access and to avoid repetition. Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210128174213.1349181-3-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10spapr: move spapr_machine_using_legacy_numa() to spapr_numa.cDaniel Henrique Barboza
This function is used only in spapr_numa.c. Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210128174213.1349181-2-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10ppc/pnv: Introduce a LPC FW memory region attribute to map the PNORCédric Le Goater
This to map the PNOR from the machine init handler directly and finish the cleanup of the LPC model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210126171059.307867-8-clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10ppc/pnv: Remove default disablement of the PNOR contentsCédric Le Goater
On PowerNV systems, the BMC is in charge of mapping the PNOR contents on the LPC FW address space using the HIOMAP protocol. Under QEMU, we emulate this behavior and we also add an extra control on the flash accesses by letting the HIOMAP command handler decide whether the memory region is accessible or not depending on the firmware requests. However, this behavior is not compatible with hostboot like firmwares which need this mapping to be always available. For this reason, the PNOR memory region is initially disabled for skiboot mode only. This is badly placed under the LPC model and requires the use of the machine. Since it doesn't add much, simply remove the initial setting. The extra control in the HIOMAP command handler will still be performed. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210126171059.307867-7-clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10ppc/pnv: Discard internal BMC initialization when BMC is externalCédric Le Goater
The PowerNV machine can be run with an external IPMI BMC device connected to a remote QEMU machine acting as BMC, using these options : -chardev socket,id=ipmi0,host=localhost,port=9002,reconnect=10 \ -device ipmi-bmc-extern,id=bmc0,chardev=ipmi0 \ -device isa-ipmi-bt,bmc=bmc0,irq=10 \ -nodefaults In that case, some aspects of the BMC initialization should be skipped, since they rely on the simulator interface. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210126171059.307867-6-clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10ppc/pnv: Simplify pnv_bmc_create()Cédric Le Goater
and reuse pnv_bmc_set_pnor() to share the setting of the PNOR. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210126171059.307867-5-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10ppc/pnv: Use skiboot addresses to load kernel and ramfsCédric Le Goater
The current settings are useful to load large kernels (with debug) but it moves the initrd image in a memory region not protected by skiboot. If skiboot is compiled with DEBUG=1, memory poisoning will corrupt the initrd. Cc: Murilo Opsfelder Araujo <muriloo@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210126171059.307867-4-clg@kaod.org> Reviewed-by: Murilo Opsfelder Araujo <muriloo@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10ppc/xive: Add firmware bit when dumping the ENDsCédric Le Goater
ENDs allocated by OPAL for the HW thread VPs are tagged as owned by FW. Dump the state in 'info pic'. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210126171059.307867-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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