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2017-09-21nvic: Handle banked exceptions in nvic_recompute_state()Peter Maydell
Update the nvic_recompute_state() code to handle the security extension and its associated banked registers. Code that uses the resulting cached state (ie the irq acknowledge and complete code) will be updated in a later commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-9-git-send-email-peter.maydell@linaro.org
2017-09-21nvic: Implement NVIC_ITNS<n> registersPeter Maydell
For v8M, the NVIC has a new set of registers per interrupt, NVIC_ITNS<n>. These determine whether the interrupt targets Secure or Non-secure state. Implement the register read/write code for these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER, NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure accesses to fields corresponding to interrupts which are configured to target secure state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org
2017-09-21nvic: Make ICSR.RETTOBASE handle banked exceptionsPeter Maydell
Update the code in nvic_rettobase() so that it checks the sec_vectors[] array as well as the vectors[] array if needed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-7-git-send-email-peter.maydell@linaro.org
2017-09-21nvic: Implement AIRCR changes for v8MPeter Maydell
The Application Interrupt and Reset Control Register has some changes for v8M: * new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have real state if the security extension is implemented and otherwise are constant * the PRIGROUP field is banked between security states * non-secure code can be blocked from using the SYSRESET bit to reset the system if SYSRESETREQS is set Implement the new state and the changes to register read and write. For the moment we ignore the effects of the secure PRIGROUP. We will implement the effects of PRIS and BFHFNMIS later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-6-git-send-email-peter.maydell@linaro.org
2017-09-21nvic: Add cached vectpending_prio statePeter Maydell
Instead of looking up the pending priority in nvic_pending_prio(), cache it in a new state struct field. The calculation of the pending priority given the interrupt number is more complicated in v8M with the security extension, so the caching will be worthwhile. This changes nvic_pending_prio() from returning a full (group + subpriority) priority value to returning a group priority. This doesn't require changes to its callsites because we use it only in comparisons of the form execution_prio > nvic_pending_prio() and execution priority is always a group priority, so a test (exec prio > full prio) is true if and only if (execprio > group_prio). (Architecturally the expected comparison is with the group priority for this sort of "would we preempt" test; we were only doing a test with a full priority as an optimisation to avoid the mask, which is possible precisely because the two comparisons always give the same answer.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-5-git-send-email-peter.maydell@linaro.org
2017-09-21nvic: Add cached vectpending_is_s_banked statePeter Maydell
With banked exceptions, just the exception number in s->vectpending is no longer sufficient to uniquely identify the pending exception. Add a vectpending_is_s_banked bool which is true if the exception is using the sec_vectors[] array. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1505240046-11454-4-git-send-email-peter.maydell@linaro.org
2017-09-21nvic: Add banked exception statesPeter Maydell
For the v8M security extension, some exceptions must be banked between security states. Add the new vecinfo array which holds the state for the banked exceptions and migrate it if the CPU the NVIC is attached to implements the security extension. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-21target/arm: Implement MSR/MRS access to NS banked registersPeter Maydell
In v8M the MSR and MRS instructions have extra register value encodings to allow secure code to access the non-secure banked version of various special registers. (We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because we don't currently implement the stack limit registers at all.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-2-git-send-email-peter.maydell@linaro.org
2017-09-21Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into stagingPeter Maydell
MIPS patches 2017-09-21 Changes: QOMify MIPS cpu Improve macro parenthesization # gpg: Signature made Thu 21 Sep 2017 13:50:37 BST # gpg: using RSA key 0x2238EB86D5F797C2 # gpg: Good signature from "Yongbok Kim <yongbok.kim@imgtec.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA 2B5C 2238 EB86 D5F7 97C2 * remotes/yongbok/tags/mips-20170921: mips: Improve macro parenthesization mips: replace cpu_mips_init() with cpu_generic_init() mips: MIPSCPU model subclasses mips: call cpu_mips_realize_env() from mips_cpu_realizefn() mips: split cpu_mips_realize_env() out of cpu_mips_init() mips: introduce internal.h and cleanup cpu.h mips: move hw/mips/cputimer.c to target/mips/ Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-21mips: Improve macro parenthesizationEric Blake
Although none of the existing macro call-sites were broken, it's always better to write macros that properly parenthesize arguments that can be complex expressions, so that the intended order of operations is not broken. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: replace cpu_mips_init() with cpu_generic_init()Igor Mammedov
now cpu_mips_init() reimplements subset of cpu_generic_init() tasks, so just drop it and use cpu_generic_init() directly. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: use internal.h instead of cpu.h] Tested-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: MIPSCPU model subclassesIgor Mammedov
Register separate QOM types for each mips cpu model, so it would be possible to reuse generic CPU creation routines. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: use internal.h, use void* to hold cpu_def in MIPSCPUClass, mark MIPSCPU abstract, address Eduardo Habkost review] Tested-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: call cpu_mips_realize_env() from mips_cpu_realizefn()Philippe Mathieu-Daudé
This changes the order between cpu_mips_realize_env() and cpu_exec_initfn(), but cpu_exec_initfn() don't have anything that depends on cpu_mips_realize_env() being called first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: split cpu_mips_realize_env() out of cpu_mips_init()Philippe Mathieu-Daudé
so it can be used in mips_cpu_realizefn() in the next commit Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: introduce internal.h and cleanup cpu.hPhilippe Mathieu-Daudé
no logical change, only code movement (and fix a comment typo). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: James Hogan <james.hogan@imgtec.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: move hw/mips/cputimer.c to target/mips/Philippe Mathieu-Daudé
This timer is a required part of the MIPS32/MIPS64 System Control coprocessor (CP0). Moving it with the other architecture related files will allow an opaque use of CPUMIPSState* in the next commit (introduce "internal.h"). also remove it from 'user' targets, remove an unnecessary include. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: James Hogan <james.hogan@imgtec.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into ↵Peter Maydell
staging qemu-sparc update # gpg: Signature made Thu 21 Sep 2017 08:42:30 BST # gpg: using RSA key 0x5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-signed: sun4u: use sunhme as default on-board NIC net: add Sun HME (Happy Meal Ethernet) on-board NIC Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-21Merge remote-tracking branch 'remotes/sstabellini/tags/xen-20170920-tag' ↵Peter Maydell
into staging Xen 2017/09/20 # gpg: Signature made Thu 21 Sep 2017 03:20:02 BST # gpg: using RSA key 0x894F8F4870E1AE90 # gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" # gpg: aka "Stefano Stabellini <sstabellini@kernel.org>" # Primary key fingerprint: D04E 33AB A51F 67BA 07D3 0AEA 894F 8F48 70E1 AE90 * remotes/sstabellini/tags/xen-20170920-tag: xen/pt: allow QEMU to request MSI unmasking at bind time xen-disk: use g_new0 to fix build Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-21sun4u: use sunhme as default on-board NICMark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-09-21net: add Sun HME (Happy Meal Ethernet) on-board NICMark Cave-Ayland
Enable it by default for the sparc64-softmmu configuration. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-09-20xen/pt: allow QEMU to request MSI unmasking at bind timeRoger Pau Monne
When a MSI interrupt is bound to a guest using xc_domain_update_msi_irq (XEN_DOMCTL_bind_pt_irq) the interrupt is left masked by default. This causes problems with guests that first configure interrupts and clean the per-entry MSIX table mask bit and afterwards enable MSIX globally. In such scenario the Xen internal msixtbl handlers would not detect the unmasking of MSIX entries because vectors are not yet registered since MSIX is not enabled, and vectors would be left masked. Introduce a new flag in the gflags field to signal Xen whether a MSI interrupt should be unmasked after being bound. This also requires to track the mask register for MSI interrupts, so QEMU can also notify to Xen whether the MSI interrupt should be bound masked or unmasked Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> Reported-by: Andreas Kinzler <hfp@posteo.de> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-09-20xen-disk: use g_new0 to fix buildOlaf Hering
g_malloc0_n is available since glib-2.24. To allow build with older glib versions use the generic g_new0, which is already used in many other places in the code. Fixes commit 3284fad728 ("xen-disk: add support for multi-page shared rings") Signed-off-by: Olaf Hering <olaf@aepfle.de> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-09-20Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into stagingPeter Maydell
These patches fix regressions in 2.10 # gpg: Signature made Wed 20 Sep 2017 07:51:07 BST # gpg: using DSA key 0x02FC3AEB0101DBC2 # gpg: Good signature from "Greg Kurz <groug@kaod.org>" # gpg: aka "Greg Kurz <groug@free.fr>" # gpg: aka "Greg Kurz <gkurz@linux.vnet.ibm.com>" # gpg: aka "Gregory Kurz (Groug) <groug@free.fr>" # gpg: aka "[jpeg image of size 3330]" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2BD4 3B44 535E C0A7 9894 DBA2 02FC 3AEB 0101 DBC2 * remotes/gkurz/tags/for-upstream: 9pfs: check the size of transport buffer before marshaling 9pfs: fix name_to_path assertion in v9fs_complete_rename() 9pfs: fix readdir() for 9p2000.u Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-20Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine/CPU/NUMA queue, 2017-09-19 # gpg: Signature made Tue 19 Sep 2017 21:17:01 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: MAINTAINERS: Update git URLs for my trees hw/acpi-build: Fix SRAT memory building in case of node 0 without RAM NUMA: Replace MAX_NODES with nb_numa_nodes in for loop numa: cpu: calculate/set default node-ids after all -numa CLI options are parsed arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly pc: use generic cpu_model parsing vl.c: convert cpu_model to cpu type and set of global properties before machine_init() cpu: make cpu_generic_init() abort QEMU on error qom: cpus: split cpu_generic_init() on feature parsing and cpu creation parts hostmem-file: Add "discard-data" option osdep: Define QEMU_MADV_REMOVE vl: Clean up user-creatable objects when exiting Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-209pfs: check the size of transport buffer before marshalingJan Dakinevich
v9fs_do_readdir_with_stat() should check for a maximum buffer size before an attempt to marshal gathered data. Otherwise, buffers assumed as misconfigured and the transport would be broken. The patch brings v9fs_do_readdir_with_stat() in conformity with v9fs_do_readdir() behavior. Signed-off-by: Jan Dakinevich <jan.dakinevich@gmail.com> [groug, regression caused my commit 8d37de41cab1 # 2.10] Signed-off-by: Greg Kurz <groug@kaod.org>
2017-09-209pfs: fix name_to_path assertion in v9fs_complete_rename()Jan Dakinevich
The third parameter of v9fs_co_name_to_path() must not contain `/' character. The issue is most likely related to 9p2000.u protocol only. Signed-off-by: Jan Dakinevich <jan.dakinevich@gmail.com> [groug, regression caused by commit f57f5878578a # 2.10] Signed-off-by: Greg Kurz <groug@kaod.org>
2017-09-209pfs: fix readdir() for 9p2000.uJan Dakinevich
If the client is using 9p2000.u, the following occurs: $ cd ${virtfs_shared_dir} $ mkdir -p a/b/c $ ls a/b ls: cannot access 'a/b/a': No such file or directory ls: cannot access 'a/b/b': No such file or directory a b c instead of the expected: $ ls a/b c This is a regression introduced by commit f57f5878578a; local_name_to_path() now resolves ".." and "." in paths, and v9fs_do_readdir_with_stat()->stat_to_v9stat() then copies the basename of the resulting path to the response. With the example above, this means that "." and ".." are turned into "b" and "a" respectively... stat_to_v9stat() currently assumes it is passed a full canonicalized path and uses it to do two different things: 1) to pass it to v9fs_co_readlink() in case the file is a symbolic link 2) to set the name field of the V9fsStat structure to the basename part of the given path It only has two users: v9fs_stat() and v9fs_do_readdir_with_stat(). v9fs_stat() really needs 1) and 2) to be performed since it starts with the full canonicalized path stored in the fid. It is different for v9fs_do_readdir_with_stat() though because the name we want to put into the V9fsStat structure is the d_name field of the dirent actually (ie, we want to keep the "." and ".." special names). So, we only need 1) in this case. This patch hence adds a basename argument to stat_to_v9stat(), to be used to set the name field of the V9fsStat structure, and moves the basename logic to v9fs_stat(). Signed-off-by: Jan Dakinevich <jan.dakinevich@gmail.com> (groug, renamed old name argument to path and updated changelog) Signed-off-by: Greg Kurz <groug@kaod.org>
2017-09-19MAINTAINERS: Update git URLs for my treesEduardo Habkost
List the branches where I queue patches for Machine Core, NUMA, Memory Backends, and X86. Update the NUMA section to list the "machine-next" branch instead of "numa". Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20170901153928.17058-1-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-09-19hw/acpi-build: Fix SRAT memory building in case of node 0 without RAMEduardo Habkost
Currently, Using the fisrt node without memory on the machine makes QEMU unhappy. With this example command line: ... \ -m 1024M,slots=4,maxmem=32G \ -numa node,nodeid=0 \ -numa node,mem=1024M,nodeid=1 \ -numa node,nodeid=2 \ -numa node,nodeid=3 \ Guest reports "No NUMA configuration found" and the NUMA topology is wrong. This is because when QEMU builds ACPI SRAT, it regards node 0 as the default node to deal with the memory hole(640K-1M). this means the node0 must have some memory(>1M), but, actually it can have no memory. Fix this problem by cut out the 640K hole in the same way the PCI 4G hole does. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com> Message-Id: <1504231805-30957-2-git-send-email-douly.fnst@cn.fujitsu.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-09-19NUMA: Replace MAX_NODES with nb_numa_nodes in for loopDou Liyang
In QEMU, the number of the NUMA nodes is determined by parse_numa_opts(). Then, QEMU uses it for iteration, for example: for (i = 0; i < nb_numa_nodes; i++) However, in memory_region_allocate_system_memory(), it uses MAX_NODES not nb_numa_nodes. So, replace MAX_NODES with nb_numa_nodes to keep code consistency and reduce the loop times. Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com> Message-Id: <1503387936-3483-1-git-send-email-douly.fnst@cn.fujitsu.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-09-19numa: cpu: calculate/set default node-ids after all -numa CLI options are parsedIgor Mammedov
Calculating default node-ids for CPUs in possible_cpu_arch_ids() is rather fragile since defaults calculation uses nb_numa_nodes but callback might be potentially called early before all -numa CLI options are parsed, which would lead to cpus assigned only upto nb_numa_nodes at the time possible_cpu_arch_ids() is called. Issue was introduced by (7c88e65 numa: mirror cpu to node mapping in MachineState::possible_cpus) and for example CLI: -smp 4 -numa node,cpus=0 -numa node would set props.node-id in possible_cpus array for every non explicitly mapped CPU to the first node. Issue is not visible to guest nor to mgmt interface due to 1) implictly mapped cpus are forced to the first node in case of partial mapping 2) in case of default mapping possible_cpu_arch_ids() is called after all -numa options are parsed (resulting in correct mapping). However it's fragile to rely on late execution of possible_cpu_arch_ids(), therefore add machine specific callback that returns node-id for CPU and use it to calculate/ set defaults at machine_numa_finish_init() time when all -numa options are parsed. Reported-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <1496314408-163972-1-git-send-email-imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-09-19Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170919-v2' into ↵Peter Maydell
staging Assorted s390x patches: - introduce virtio-gpu-ccw, with virtio-gpu endian fixes - lots of cleanup in the s390x code - make device_add work for s390x cpus - enable seccomp on s390x - an ivshmem endian fix - set the reserved DHCP client architecture id for netboot - fixes in the css and pci support # gpg: Signature made Tue 19 Sep 2017 17:39:45 BST # gpg: using RSA key 0xDECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # gpg: aka "Cornelia Huck <cohuck@kernel.org>" # gpg: aka "Cornelia Huck <cohuck@redhat.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20170919-v2: (38 commits) MAINTAINERS/s390x: add terminal3270.c virtio-ccw: Create a virtio gpu device for the ccw bus virtio-gpu: Handle endian conversion s390x/ccw: create s390 phb for compat reasons as well configure: Allow --enable-seccomp on s390x, too virtio-ccw: remove stale comments on endianness s390x: allow CPU hotplug in random core-id order s390x: generate sclp cpu information from possible_cpus s390x: get rid of cpu_s390x_create() s390x: get rid of cpu_states and use possible_cpus instead s390x: implement query-hotpluggable-cpus s390x: CPU hot unplug via device_del cannot work for now s390x: allow cpu hotplug via device_add s390x: print CPU definitions in sorted order target/s390x: rename next_cpu_id to next_core_id target/s390x: use "core-id" for cpu number/address/id handling target/s390x: set cpu->id for linux user when realizing s390x: allow only 1 CPU with TCG target/s390x: use program_interrupt() in per_check_exception() target/s390x: use trigger_pgm_exception() in s390_cpu_handle_mmu_fault() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-19MAINTAINERS/s390x: add terminal3270.cChristian Borntraeger
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20170918130455.144262-1-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19virtio-ccw: Create a virtio gpu device for the ccw busFarhan Ali
Wire up the virtio-gpu device for the CCW bus. The virtio-gpu is a virtio-1 device, so disable revision 0. Signed-off-by: Farhan Ali <alifm@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Halil Pasic <pasic@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <6c53f939cf2d64b66d2a6878b29c9bf3820f3d5b.1505485574.git.alifm@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19virtio-gpu: Handle endian conversionFarhan Ali
Virtio GPU code currently only supports litte endian format, and so using the Virtio GPU device on a big endian machine does not work. Let's fix it by supporting the correct host cpu byte order. Signed-off-by: Farhan Ali <alifm@linux.vnet.ibm.com> Message-Id: <dc748e15f36db808f90b4f2393bc29ba7556a9f6.1505485574.git.alifm@linux.vnet.ibm.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x/ccw: create s390 phb for compat reasons as wellCornelia Huck
d32bd032d8 ("s390x/ccw: create s390 phb conditionally") made registering the s390 pci host bridge conditional on presense of the zpci facility bit. Sadly, that breaks migration from machines that did not use the cpu model (2.7 and previous). Create the s390 phb for pre-cpu model machines as well: We can tweak s390_has_feat() to always indicate the zpci facility bit when no cpu model is available (on 2.7 and previous compat machines). Fixes: d32bd032d8 ("s390x/ccw: create s390 phb conditionally") Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19configure: Allow --enable-seccomp on s390x, tooThomas Huth
libseccomp supports s390x since version 2.3.0, and I was able to start a VM with "-sandbox on" without any obvious problems by using this patch, so it should be safe to allow --enable-seccomp on s390x nowadays, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1505385363-27717-1-git-send-email-thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Eduardo Otubo <otubo@redhat.com> Acked-by: Halil Pasic <pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19virtio-ccw: remove stale comments on endiannessHalil Pasic
We have two stale comments suggesting one should think about virtio config space endianness a bit longer. We have just done that, and came to the conclusion we are fine as is: it's the responsibility of the virtio device and not of the transport (and that is how it works now). Putting the responsibility into the transport isn't even possible, because the transport would have to know about the config space layout of each device. Let us remove the stale comments. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Suggested-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20170914105535.47941-1-pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: allow CPU hotplug in random core-id orderDavid Hildenbrand
SCLP correctly indicates the core-id aka. CPU address for each available CPU. As the core-id corresponds to cpu_index, also a newly created kvm vcpu gets assigned this core-id as vcpu id. So SIGP in the kernel works correctly (it uses the vcpu id to lookup the correct CPU). So there should be nothing hindering us from hotplugging CPUs in random core-id order. This now makes sure that the output from "query-hotpluggable-cpus" is completely true. Until now, a specific order is implicit. Performance vice, hotplugging CPUs in non-sequential order might not be the best thing to do, as VCPU lookup inside KVM might be a little slower. But that doesn't hinder us from supporting it. next_core_id is now used by linux user only. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-23-david@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: generate sclp cpu information from possible_cpusDavid Hildenbrand
This is the first step to allow hot plugging of CPUs in a non-sequential order. If a cpu is available ("plugged") can directly be decided by looking at the cpu state pointer. This makes sure, that really only cpus attached to the machine are reported. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-22-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: get rid of cpu_s390x_create()David Hildenbrand
Now that there is only one user of cpu_s390x_create() left, make cpu creation look like on x86. - Perform the model/properties split and checks in s390_init_cpus() - Parse features only once without having to remember if already parsed - Pass only the typename to s390x_new_cpu() - Use the typename of an existing CPU for hotplug via cpu-add Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-21-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: get rid of cpu_states and use possible_cpus insteadDavid Hildenbrand
Now that we have possible_cpus, we can get rid of the global variable and rewrite s390_cpu_addr2state() to use it. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-20-david@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: implement query-hotpluggable-cpusDavid Hildenbrand
CPU hotplug is only possible on a per core basis on s390x. So let's add possible_cpus and wire everything up properly. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-19-david@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: CPU hot unplug via device_del cannot work for nowDavid Hildenbrand
device_del on a CPU will currently do nothing. Let's emit an error telling that this is will currently not work (there is no architecture support on s390x). Error message copied from ppc. (qemu) device_del cpu1 device_del cpu1 CPU hot unplug not supported on this machine Reviewed-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: allow cpu hotplug via device_addDavid Hildenbrand
E.g. the following now works: device_add host-s390-cpu,id=cpu1,core-id=1 The system will perform the same checks as when using cpu_add: - If the core_id is already in use - If the next sequential core_id isn't used - If core-id >= max_cpu is specified In addition, mixed CPU models are checked. E.g. if starting with -cpu host and trying to hotplug "qemu-s390-cpu": "Mixed CPU models are not supported on s390x." Reviewed-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: print CPU definitions in sorted orderDavid Hildenbrand
Other architectures provide nicely sorted lists, let's do it similarly on s390x. While at it, clean up the code we have to touch either way. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19target/s390x: rename next_cpu_id to next_core_idDavid Hildenbrand
Adapt to the new term "core_id". While at it, fix the type and drop the initialization to 0 (which is superfluous). Reviewed-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19target/s390x: use "core-id" for cpu number/address/id handlingDavid Hildenbrand
Some time ago we discussed that using "id" as property name is not the right thing to do, as it is a reserved property for other devices and will not work with device_add. Switch to the term "core-id" instead, and use it as an equivalent to "CPU address" mentioned in the PoP. There is no such thing as cpu number, so rename env.cpu_num to env.core_id. We use "core-id" as this is the common term to use for device_add later on (x86 and ppc). We can get rid of cpu->id now. Keep cpu_index and env->core_id in sync. cpu_index was already implicitly used by e.g. cpu_exists(), so keeping both in sync seems to be the right thing to do. cpu_index will now no longer automatically get set via cpu_exec_realizefn(). For now, we were lucky that both implicitly stayed in sync. Our new cpu property "core-id" can be a static property. Range checks can be avoided by using the correct type and the "setting after realized" check is done implicitly. device_add will later need the reserved "id" property. Hotplugging a CPU on s390x will then be: "device_add host-s390-cpu,id=cpu2,core-id=2". Reviewed-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19target/s390x: set cpu->id for linux user when realizingDavid Hildenbrand
scc->next_cpu_id is updated when realizing. Setting it just before that point looks cleaner. Reviewed-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: allow only 1 CPU with TCGDavid Hildenbrand
Specifying more than 1 CPU (e.g. -smp 5) leads to SIGP errors (the guest tries to bring these CPUs up but fails), because we don't support multiple CPUs on s390x under TCG. Let's bail out if more than 1 is specified, so we don't raise people's hope. Tested-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-12-david@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-24 17:35:17 +0000