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2022-03-02target/ppc: vmulh* instructions without helpersLucas Mateus Castro (alqotel)
Changed vmulhuw, vmulhud, vmulhsw, vmulhsd to not use helpers. Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225210936.1749575-5-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Moved vector multiply high and low to decodetreeLucas Mateus Castro (alqotel)
Moved instructions vmulld, vmulhuw, vmulhsw, vmulhud and vmulhsd to decodetree Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-4-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: moved vector even and odd multiplication to decodetreeLucas Mateus Castro (alqotel)
Moved the instructions vmulesb, vmulosb, vmuleub, vmuloub, vmulesh, vmulosh, vmuleuh, vmulouh, vmulesw, vmulosw, muleuw and vmulouw from legacy to decodetree. Implemented the instructions vmulesd, vmulosd, vmuleud, vmuloud. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-3-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Introduce TRANS*FLAGS macrosLuis Pires
New macros that add FLAGS and FLAGS2 checking were added for both TRANS and TRANS64. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> [ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E - Use the new macros in load/store vector insns ] Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-2-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: trigger PERFM EBBs from power8-pmu.cDaniel Henrique Barboza
This patch adds the EBB exception support that are triggered by Performance Monitor alerts. This happens when a Performance Monitor alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set. fire_PMC_interrupt() will execute the raise_ebb_perfm_exception() helper which will check for MMCR0_EBE, BESCR_PME and BESCR_GE bits. If all bits are set, do_ebb() will attempt to trigger a PERFM EBB event. If the EBB facility is enabled in both FSCR and HFSCR we consider that the EBB is valid and set BESCR_PMEO. After that, if we're running in problem state, fire a POWERPC_EXCP_PERM_EBB immediately. Otherwise we'll queue a PPC_INTERRUPT_EBB. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225101140.1054160-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: add PPC_INTERRUPT_EBB and EBB exceptionsDaniel Henrique Barboza
PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB exceptions that had to be postponed because the thread wasn't in problem state at the time the event-based branch was supposed to occur. ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB exception and External EBB exception. They are being added as POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB. PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that occurred and trigger the appropriate exception. Both exceptions are doing the same thing in this first implementation: clear BESCR_GE and enter the branch with env->nip retrieved from SPR_EBBHR. The checks being done by the interrupt code are msr_pr and BESCR_GE states. All other checks (EBB facility check, BESCR_PME bit, specific bits related to the event type) must be done beforehand. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220225101140.1054160-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: finalize pre-EBB PMU logicDaniel Henrique Barboza
There are still PMU exclusive bits to handle in fire_PMC_interrupt() before implementing the EBB support. Let's finalize it now to avoid dealing with PMU and EBB logic at the same time in the next patches. fire_PMC_interrupt() will fire an Performance Monitor alert depending on MMCR0_PMAE. If we are required to freeze the timers (MMCR0_FCECE) we'll also need to update summaries and delete the existing overflow timers. In all cases we're going to update the cycle counters. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220225101140.1054160-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: make power8-pmu.c CONFIG_TCG onlyDaniel Henrique Barboza
This is an exclusive TCG helper. Gating it with CONFIG_TCG and changing meson.build accordingly will prevent problems --disable-tcg and --disable-linux-user later on. We're also changing the uses of !kvm_enabled() to tcg_enabled() to avoid adding "defined(CONFIG_TCG)" ifdefs, since tcg_enabled() will be defaulted to false with --disable-tcg and the block will always be skipped. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220225101140.1054160-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: fix default PHB4 QOM hierarchyDaniel Henrique Barboza
Commit 3f4c369ea63e ("ppc/pnv: make PECs create and realize PHB4s") changed phb4_pec code to create the default PHB4 objects in pnv_pec_default_phb_realize(). In this process the stacks[] PEC array was removed and each PHB4 object is tied together with its PEC via the phb->pec pointer. This change also broke the previous QOM hierarchy - the PHB4 objects are being created and not being parented to their respective chips. This can be verified by 'info pic' in a powernv9 domain with default settings. pnv_chip_power9_pic_print_info() will fail to find the PHBs because object_child_foreach_recursive() won't find any. The solution is to set the parent chip and the parent bus, in the same way done for user created PHB4 devices, for all PHB4 devices. Fixes: 3f4c369ea63e ("ppc/pnv: make PECs create and realize PHB4s") Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220218202804.413157-1-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/pnv: Determine ns16550's IRQ number from QOM propertyBernhard Beschow
Determine the IRQ number in the same way as for pnv_dt_ipmi_bt(). This resolves one usage of ISADevice::isairq[] which allows it to be removed eventually. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220301220037.76555-6-shentey@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-01Merge remote-tracking branch ↵Peter Maydell
'remotes/bsdimp/tags/bsd-user-preen-2022q1-pull-request' into staging bsd-user: Prepare for future upstream of system calls. This series of patches does three things. First, it starts to give up on the idea that you can run FooBSD binaries on BarBSD. They are too different to make that happen any time soon, though I've kept the support for Net/OpenBSD, even though they haven't built. We'll need a lot of work to make that happen, though, and I need to simplify to get things upstream. Second, it starts to move some of the ifdef trees into target.h. Third, it starts to upstream bsd-file.h, but the remainder of the file in the bsd-user fork had some issues that will be resolved before next quarter's update. # gpg: Signature made Mon 28 Feb 2022 18:11:47 GMT # gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100 # gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown] # gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown] # gpg: aka "Warner Losh <imp@freebsd.org>" [unknown] # gpg: aka "Warner Losh <imp@village.org>" [unknown] # gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100 * remotes/bsdimp/tags/bsd-user-preen-2022q1-pull-request: bsd-user: Add safe system call macros bsd-user: Define target_arg64 bsd-user: introduce target.h bsd-user/bsd-file.h: Implementation details for the filesystem calls bsd-user/freebsd/os-syscall.c: Add get_errno and host_to_target_errno bsd-user/sycall.c: Now obsolete, remove bsd-user: Move system call building to os-syscall.c bsd-user/freebsd/os-syscall.c: Move syscall processing here bsd-user: Remove bsd_type bsd-user/x86_64/target_arch_thread.h: Assume a FreeBSD target bsd-user/arm/target_arch_thread.h: Assume a FreeBSD target bsd-user/arm/target_arch_cpu.h: Only support FreeBSD sys calls bsd-user/i386/target_arch_cpu.h: Remove openbsd syscall bsd-user/x86_64/target_arch_cpu.h: Remove openbsd syscall bsd-user/x86_64/target_arch_cpu.h: int $80 never was a BSD system call on amd64 bsd-user/main.c: Drop syscall flavor arg -bsd Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-01Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220228' ↵Peter Maydell
into staging Fix typecode generation for tcg helpers Fix single stepping into interrupt handlers Fix out-of-range offsets for stores in TCI # gpg: Signature made Mon 28 Feb 2022 18:07:13 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20220228: tcg/tci: Use tcg_out_ldst in tcg_out_st accel/tcg/cpu-exec: Fix precise single-stepping after interrupt tcg: Remove dh_alias indirection for dh_typecode Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-01Merge remote-tracking branch ↵Peter Maydell
'remotes/thuth-gitlab/tags/pull-request-2022-02-28' into staging * Fix emulation of the SET CLOCK instruction * Fix the s390x avocado test with Fedora * Update the s390x Travis jobs to Focal (instead of Bionic) * Implement the z15 Misc Instruction Extension 3 Facility # gpg: Signature made Mon 28 Feb 2022 10:34:47 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/pull-request-2022-02-28: tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3 s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1 s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x travis.yml: Update the s390x jobs to Ubuntu Focal tests/avocado/machine_s390_ccw_virtio: Adapt test to new default resolution s390x: sck: load into a temporary not into in1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-01Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2022-02-28' into ↵Peter Maydell
staging QAPI patches patches for 2022-02-28 # gpg: Signature made Mon 28 Feb 2022 10:40:22 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2022-02-28: qapi: Belatedly adjust limitations documentation rtc: Have event RTC_CHANGE identify the RTC by QOM path hw/rtc: Compile pl031 once-only qapi: Document some missing details of RTC_CHANGE event qapi: Move RTC_CHANGE back out of target schema qapi/migration: Fix examples document wrong field name for arguments qapi: Fix stale reference to scripts/qapi.py in a comment keyval: Fix grammar comment to cover downstream prefix scripts/qapi: minor delinting Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-28tcg/tci: Use tcg_out_ldst in tcg_out_stRichard Henderson
The tcg_out_ldst helper will handle out-of-range offsets. We haven't actually encountered any, since we haven't run across the assert within tcg_out_op_rrs, but an out-of-range offset would not be impossible in future. Fixes: 65089889183 ("tcg/tci: Change encoding to uint32_t units") Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-28accel/tcg/cpu-exec: Fix precise single-stepping after interruptLuc Michel
In some cases, cpu->exit_request can be false after handling the interrupt, leading to another TB being executed instead of returning to the main loop. Fix this by returning true unconditionally when in single-step mode. Fixes: ba3c35d9c402 ("tcg/cpu-exec: precise single-stepping after an interrupt") Signed-off-by: Luc Michel <lmichel@kalray.eu> Message-Id: <20220214132656.11397-1-lmichel@kalray.eu> [rth: Unlock iothread mutex; simplify indentation] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-28tcg: Remove dh_alias indirection for dh_typecodeRichard Henderson
The dh_alias redirect is intended to handle TCG types as distinguished from C types. TCG does not distinguish signed int from unsigned int, because they are the same size. However, we need to retain this distinction for dh_typecode, lest we fail to extend abi types properly for the host call parameters. This bug was detected when running the 'arm' emulator on an s390 system. The s390 uses TCG_TARGET_EXTEND_ARGS which triggers code in tcg_gen_callN to extend 32 bit values to 64 bits; the incorrect sign data in the typemask for each argument caused the values to be extended as unsigned values. This simple program exhibits the problem: static volatile int num = -9; static volatile int den = -5; int main(void) { int quo = num / den; printf("num %d den %d quo %d\n", num, den, quo); exit(0); } When run on the broken qemu, this results in: num -9 den -5 quo 0 The correct result is: num -9 den -5 quo 1 Fixes: 7319d83a735 ("tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/876 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reported-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> Tested-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> Tested-by: Keith Packard <keithp@keithp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-28Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220227' ↵Peter Maydell
into staging aspeed queue: * Removal of the swift-bmc machine * New Secure Boot Controller model * Improvements on the rainier machine * Various small cleanups # gpg: Signature made Sun 27 Feb 2022 08:45:45 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20220227: aspeed/sdmc: Add trace events aspeed/smc: Add an address mask on segment registers aspeed: Introduce a create_pca9552() helper aspeed: rainier: Add strap values taken from hardware aspeed: rainier: Add i2c LED devices ast2600: Add Secure Boot Controller model arm: Remove swift-bmc machine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-28tests/tcg: port SYS_HEAPINFO to a system testAlex Bennée
This allows us to check our new SYS_HEAPINFO implementation generates sane values. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220225172021.3493923-19-alex.bennee@linaro.org>
2022-02-28semihosting/arm-compat: replace heuristic for softmmu SYS_HEAPINFOAlex Bennée
The previous numbers were a guess at best and rather arbitrary without taking into account anything that might be loaded. Instead of using guesses based on the state of registers implement a new function that: a) scans the MemoryRegions for the largest RAM block b) iterates through all "ROM" blobs looking for the biggest gap The "ROM" blobs include all code loaded via -kernel and the various -device loader techniques. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Andrew Strauss <astrauss11@gmail.com> Cc: Keith Packard <keithp@keithp.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220225172021.3493923-18-alex.bennee@linaro.org>
2022-02-28tests/tcg: completely disable threadcount for sh4Alex Bennée
The previous disabling of threadcount 3bdc19af00 ("tests/tcg/sh4: disable another unreliable test") just for plugins was being too conservative. It's all broken so skip it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-17-alex.bennee@linaro.org>
2022-02-28gitlab: upgrade the job definition for s390x to 20.04Alex Bennée
The new s390x machine has more of everything including the OS. As 18.04 will soon be going we might as well get onto something moderately modern. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-16-alex.bennee@linaro.org>
2022-02-28travis.yml: Update the s390x jobs to Ubuntu FocalThomas Huth
QEMU will soon drop the support for Ubuntu 18.04, so let's update the Travis jobs that were still using this version to 20.04 instead. While we're at it, also remove an obsolete comment about Ubuntu Xenial being the default for our Travis jobs. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220221153423.1028465-1-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-15-alex.bennee@linaro.org>
2022-02-28tests/tcg: add vectorised sha512 versionsAlex Bennée
This builds vectorised versions of sha512 to exercise the vector code: - aarch64 (AdvSimd) - i386 (SSE) - s390x (MVX) - ppc64/ppc64le (power10 vectors) Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-14-alex.bennee@linaro.org>
2022-02-28tests/tcg: add sha512 testAlex Bennée
This imports the sha512 algorithm and related tests from ccan which offers a cleaner hash implementation with its own validation tests with which we can exercise TCG code generations. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-13-alex.bennee@linaro.org>
2022-02-28tests/tcg: build sha1-vector with O3 and compareAlex Bennée
The aim of this is to test code generation for vectorised operations. Unfortunately gcc struggles to do much with the messy sha1 code (try -fopt-info-vec-missed to see why). However it's better than nothing. We assume the non-vectorised output is gold and baring compiler bugs the outputs should match. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-12-alex.bennee@linaro.org>
2022-02-28tests/tcg/ppc64: clean-up handling of byte-reverseAlex Bennée
Rather than having an else leg for the missing compiler case we can simply just not add the test - the same way as is done for ppc64le. Also while we are at it fix up the compiler invocation. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-11-alex.bennee@linaro.org>
2022-02-28gitlab: add a new aarch32 custom runner definitionAlex Bennée
Although running on aarch64 hardware we can still target 32bit builds with a cross compiler and run the resulting binaries. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220225172021.3493923-10-alex.bennee@linaro.org>
2022-02-28scripts/ci: allow for a secondary runnerAlex Bennée
Some HW can run multiple architecture profiles so we can install a secondary runner to build and run tests for those profiles. This allows setting up secondary service. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-9-alex.bennee@linaro.org>
2022-02-28scripts/ci: add build env rules for aarch32 on aarch64Alex Bennée
At least the current crop of Aarch64 HW can support running 32 bit EL0 code. Before we can build and test we need a minimal set of packages installed. We can't use "apt build-dep" because it currently gets confused trying to keep two sets of build-deps installed at once. Instead we install a minimal set of libraries that will allow us to continue. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-8-alex.bennee@linaro.org>
2022-02-28tests/docker: introduce debian-riscv64-test-crossAlex Bennée
Cross building QEMU for riscv64 still involves messing about with sid and ports. However for building tests we can have a slimmer compiler only container which should be more stable. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-7-alex.bennee@linaro.org>
2022-02-28tests/docker: update debian-s390x-cross with lcitoolAlex Bennée
A later compiler is needed for some upcomming tests so we might as well migrate to an lcitool generated docker file. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-6-alex.bennee@linaro.org>
2022-02-28tests/docker: update debian-arm64-cross with lcitoolAlex Bennée
Using lcitool update debian-arm64-cross to a Debian 11 based system. As a result we can drop debian-arm64-test-cross just for building tests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-5-alex.bennee@linaro.org>
2022-02-28tests/lcitool: update to latest versionAlex Bennée
We will need an update shortly for some new images. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220225172021.3493923-4-alex.bennee@linaro.org>
2022-02-28tests/docker: add NOUSER for alpine imageAlex Bennée
The alpine image doesn't have a standard useradd binary so disable this convenience feature for it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-3-alex.bennee@linaro.org>
2022-02-28tests/docker: restore TESTS/IMAGES filteringAlex Bennée
This was broken in the re-factor: e86c9a64f4 ("tests/docker/Makefile.include: add a generic docker-run target") Rather than unwind the changes just apply the filters to the total set of available images and tests. That way we don't inadvertently build images only not to use them later. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reported-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-2-alex.bennee@linaro.org>
2022-02-28Merge remote-tracking branch 'remotes/shorne/tags/or1k-pull-request' into ↵Peter Maydell
staging OpenRISC patches - Add automatic DTS generation to openrisc_sim # gpg: Signature made Sat 26 Feb 2022 01:39:55 GMT # gpg: using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4 # gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4 * remotes/shorne/tags/or1k-pull-request: hw/openrisc/openrisc_sim: Add support for initrd loading hw/openrisc/openrisc_sim: Add automatic device tree generation hw/openrisc/openrisc_sim: Increase max_cpus to 4 hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART hw/openrisc/openrisc_sim: Parameterize initialization hw/openrisc/openrisc_sim: Create machine state for or1ksim Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-28qapi: Belatedly adjust limitations documentationMarkus Armbruster
Commit 57df0dff1a "qapi: Extend -compat to set policy for unstable interfaces" (v6.2.0) took care of covering experimental features, but neglected to adjust a comment suggesting to cover it. Adjust it now. Fixes: 57df0dff1a1f4c846aa74a082bfd595a8a990015 Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220225084538.218876-1-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-02-28rtc: Have event RTC_CHANGE identify the RTC by QOM pathMarkus Armbruster
Event RTC_CHANGE is "emitted when the guest changes the RTC time" (and the RTC supports the event). What if there's more than one RTC? Which one changed? New @qom-path identifies it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <87a6ejnm80.fsf@pond.sub.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-02-28hw/rtc: Compile pl031 once-onlyPeter Maydell
Now that the RTC_CHANGE event is no longer target-specific, we can move the pl031 back to a compile-once source file rather than a compile-per-target one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220221192123.749970-4-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-02-28qapi: Document some missing details of RTC_CHANGE eventPeter Maydell
The RTC_CHANGE event's documentation is missing some details: * the offset argument is in units of seconds * it isn't guaranteed that the RTC will implement the event Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220221192123.749970-3-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-02-28qapi: Move RTC_CHANGE back out of target schemaPeter Maydell
This commit effectively reverts commit 183e4281a30962, which moved the RTC_CHANGE event to the target schema. That change was an attempt to make the event target-specific to improve introspection, but the event isn't really target-specific: it's machine or device specific. Putting RTC_CHANGE in the target schema with an ifdef list reduces maintainability (by adding an if: list with a long list of targets that needs to be manually updated as architectures are added or removed or as new devices gain the RTC_CHANGE functionality) and increases compile time (by preventing RTC devices which emit the event from being "compile once" rather than "compile once per target", because qapi-events-misc-target.h uses TARGET_* ifdefs, which are poisoned in "compile once" files.) Move RTC_CHANGE back to misc.json. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Acked-by: Greg Kurz <groug@kaod.org> Message-Id: <20220221192123.749970-2-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-02-28qapi/migration: Fix examples document wrong field name for argumentsFabian Holler
The examples for the snapshot-* and calc-dirty-rate commands document that arguments for the commands are passed in a 'data' field. This is wrong, passing them in a "data" field results in the error: {"error": {"class": "GenericError", "desc": "QMP input member 'data' is unexpected"}} Arguments are expected to be passed in an field called "arguments". Replace "data" with "arguments" in the snapshot-* and calc-dirty-rate command examples. Signed-off-by: Fabian Holler <fabian.holler@simplesurance.de> Message-Id: <20220222170116.63105-1-fabian.holler@simplesurance.de> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-02-28qapi: Fix stale reference to scripts/qapi.py in a commentMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220218145551.892787-3-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-02-28keyval: Fix grammar comment to cover downstream prefixMarkus Armbruster
According to the grammar, a key __com.redhat_foo would be parsed as two key fragments __com and redhat_foo. It's actually parsed as a single fragment. Fix the grammar. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220218145551.892787-2-armbru@redhat.com>
2022-02-28scripts/qapi: minor delintingJohn Snow
Get isort and pylint tools passing again. Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20220211183650.2946895-1-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Comment explaining good-names-rgxs tweaked] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-02-28tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3David Miller
tests/tcg/s390x/mie3-compl.c: [N]*K instructions tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction tests/tcg/s390x/mie3-sel.c: SELECT instruction Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-4-dmiller423@gmail.com> [thuth: Squash mnemonic -> .insn patch, white space cleanup, improve asm usage] Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-28s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1David Miller
TCG implements everything we need to run basic z15 OS+software Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-3-dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-28s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the ↵David Miller
s390x implements: AND WITH COMPLEMENT (NCRK, NCGRK) NAND (NNRK, NNGRK) NOT EXCLUSIVE OR (NXRK, NXGRK) NOR (NORK, NOGRK) OR WITH COMPLEMENT (OCRK, OCGRK) SELECT (SELR, SELGR) SELECT HIGH (SELFHR) MOVE RIGHT TO LEFT (MVCRL) POPULATION COUNT (POPCNT) Resolves: https://gitlab.com/qemu-project/qemu/-/issues/737 Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-2-dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-28travis.yml: Update the s390x jobs to Ubuntu FocalThomas Huth
QEMU will soon drop the support for Ubuntu 18.04, so let's update the Travis jobs that were still using this version to 20.04 instead. While we're at it, also remove an obsolete comment about Ubuntu Xenial being the default for our Travis jobs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220221153423.1028465-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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