slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2021-05-11	target/riscv: fix a typo with interrupt names	Emmanuel Blot
2021-05-11	fpu/softfloat: set invalid excp flag for RISC-V muladd instructions	Frank Chang
2021-05-11	hw/riscv: Fix OT IBEX reset vector	Alexander Wagner
2021-05-11	target/riscv: fix exception index on instruction access fault	Emmanuel Blot
2021-05-11	target/riscv: fix vrgather macro index variable type bug	Frank Chang
2021-05-11	target/riscv: Add ePMP support for the Ibex CPU	Alistair Francis
2021-05-11	target/riscv/pmp: Remove outdated comment	Alistair Francis
2021-05-11	target/riscv: Add a config option for ePMP	Hou Weiying
2021-05-11	target/riscv: Implementation of enhanced PMP (ePMP)	Hou Weiying
2021-05-11	target/riscv: Add ePMP CSR access functions	Hou Weiying
2021-05-11	target/riscv: Add the ePMP feature	Alistair Francis
2021-05-11	target/riscv: Define ePMP mseccfg	Hou Weiying
2021-05-11	target/riscv: Fix the PMP is locked check when using TOR	Alistair Francis
2021-05-11	docs: Add documentation for shakti_c machine	Vijai Kumar K
2021-05-11	target/riscv: Fixup saturate subtract function	LIU Zhiwei
2021-05-11	riscv: don't look at SUM when accessing memory from a debugger context	Jade Fink
2021-05-11	hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine	Alistair Francis
2021-05-11	hw/opentitan: Update the interrupt layout	Alistair Francis
2021-05-11	MAINTAINERS: Update the RISC-V CPU Maintainers	Alistair Francis
2021-05-11	target/riscv: Use RISCVException enum for CSR access	Alistair Francis
2021-05-11	target/riscv: Use the RISCVException enum for CSR operations	Alistair Francis
2021-05-11	target/riscv: Fix 32-bit HS mode access permissions	Alistair Francis
2021-05-11	target/riscv: Use the RISCVException enum for CSR predicates	Alistair Francis
2021-05-11	target/riscv: Convert the RISC-V exceptions to an enum	Alistair Francis
2021-05-11	hw/riscv: Connect Shakti UART to Shakti platform	Vijai Kumar K
2021-05-11	hw/char: Add Shakti UART emulation	Vijai Kumar K
2021-05-11	riscv: Add initial support for Shakti C machine	Vijai Kumar K
2021-05-11	target/riscv: Add Shakti C class CPU	Vijai Kumar K
2021-05-11	hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]	Bin Meng
2021-05-11	target/riscv: Align the data type of reset vector address	Dylan Jhong
2021-05-11	docs/system/generic-loader.rst: Fix style	Axel Heider
2021-05-11	target/riscv: Remove privilege v1.9 specific CSR related code	Atish Patra
2021-05-11	main-loop: remove dead code	Paolo Bonzini
2021-05-11	target/i386: use mmu_translate for NPT walk	Paolo Bonzini
2021-05-11	target/i386: allow customizing the next phase of the translation	Paolo Bonzini
2021-05-11	target/i386: extend pg_mode to more CR0 and CR4 bits	Paolo Bonzini
2021-05-11	target/i386: pass cr3 to mmu_translate	Paolo Bonzini
2021-05-11	target/i386: extract mmu_translate	Paolo Bonzini
2021-05-11	target/i386: move paging mode constants from SVM to cpu.h	Paolo Bonzini
2021-05-11	target/i386: merge SVM_NPTEXIT_* with PF_ERROR_* constants	Paolo Bonzini
2021-05-10	accel: add init_accel_cpu for adapting accel behavior to CPU type	Claudio Fontana
2021-05-10	accel: move call to accel_init_interfaces	Claudio Fontana
2021-05-10	i386: make cpu_load_efer sysemu-only	Claudio Fontana
2021-05-10	target/i386: gdbstub: only write CR0/CR2/CR3/EFER for sysemu	Claudio Fontana
2021-05-10	target/i386: gdbstub: introduce aux functions to read/write CS64 regs	Claudio Fontana
2021-05-10	i386: split off sysemu part of cpu.c	Claudio Fontana
2021-05-10	i386: split seg_helper into user-only and sysemu parts	Claudio Fontana
2021-05-10	i386: split svm_helper into sysemu and stub-only user	Claudio Fontana
2021-05-10	i386: separate fpu_helper sysemu-only parts	Claudio Fontana
2021-05-10	i386: split misc helper user stubs and sysemu part	Claudio Fontana