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2021-11-04tests/tcg: remove duplicate EXTRA_RUNSAlex Bennée
We set it bellow outside the #if leg. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211026102234.3961636-28-alex.bennee@linaro.org>
2021-11-04plugins: try and make plugin_insn_append more ergonomicAlex Bennée
Currently we make the assumption that the guest frontend loads all op code bytes sequentially. This mostly holds up for regular fixed encodings but some architectures like s390x like to re-read the instruction which causes weirdness to occur. Rather than changing the frontends make the plugin API a little more ergonomic and able to handle the re-read case. Stuff will still get strange if we read ahead of the opcode but so far no front ends have done that and this patch asserts the case so we can catch it early if they do. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211026102234.3961636-21-alex.bennee@linaro.org>
2021-11-04tests/plugins: extend the insn plugin to track opcode sizesAlex Bennée
This is mostly a convenience feature for identifying frontends that do multiple repeat loads so I can test changes to the instruction tracking interface. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211026102234.3961636-20-alex.bennee@linaro.org>
2021-11-04chardev: don't exit() straight away on C-a xAlex Bennée
While there are a number of uses in the code-base of the exit(0) pattern it gets in the way of clean exit which can do all of it's house-keeping. In particular it was reported that you can crash plugins this way because TCG can still be running on other threads when the atexit callback is called. Use qmp_quit() instead which takes care of some housekeeping before triggering the shutdown. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reported-by: Lukas Jünger <lukas.junger@greensocs.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20211026102234.3961636-19-alex.bennee@linaro.org>
2021-11-04docs/tcg-plugins: add L2 arguments to cache docsMahmoud Mandour
cache plugin now allows optional L2 per-core cache emulation that can be configured through plugin arguments, this commit adds this functionality to the docs. While I'm at it, I editted the bullet point for cache plugin to say: contrib/plugins/cache.c instead of contrib/plugins/cache to match other plugins. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210810134844.166490-6-ma.mandourr@gmail.com> Message-Id: <20211026102234.3961636-18-alex.bennee@linaro.org>
2021-11-04plugins/cache: make L2 emulation optional through argsMahmoud Mandour
By default L2 is not enabled and is enabled by either using the newly-introduced "l2" boolean argument, or by setting any of the L2 cache parameters using args. On specifying "l2=on", the default cache configuration is used. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210810134844.166490-5-ma.mandourr@gmail.com> Message-Id: <20211026102234.3961636-17-alex.bennee@linaro.org>
2021-11-04plugins/cache: split command line arguments into name and valueMahmoud Mandour
This way of handling args is more lenient and sets a better framework to parse boolean command line arguments. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210810134844.166490-4-ma.mandourr@gmail.com> Message-Id: <20211026102234.3961636-16-alex.bennee@linaro.org>
2021-11-04plugins/cache: implement unified L2 cache emulationMahmoud Mandour
This adds an implementation of a simple L2 configuration, in which a unified L2 cache (stores both blocks of instructions and data) is maintained for each core separately, with no inter-core interaction taken in account. The L2 cache is used as a backup for L1 and is only accessed if the wanted block does not exist in L1. In terms of multi-threaded user-space emulation, the same approximation of L1 is done, a static number of caches is maintained, and each and every memory access initiated by a thread will have to go through one of the available caches. An atomic increment is used to maintain the number of L2 misses per instruction. The default cache parameters of L2 caches is: 2MB cache size 16-way associativity 64-byte blocks Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210810134844.166490-3-ma.mandourr@gmail.com> Message-Id: <20211026102234.3961636-15-alex.bennee@linaro.org>
2021-11-04plugins/cache: freed heap-allocated mutexesMahmoud Mandour
Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210810134844.166490-2-ma.mandourr@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211026102234.3961636-14-alex.bennee@linaro.org>
2021-11-04ebpf: really include it only in system emulatorsPaolo Bonzini
eBPF libraries are being included in user emulators, which is useless and also breaks --static compilation if a shared library for libbpf is present in the system. Reported-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211012162252.263933-1-pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-bt: Warner Losh <imp@bsdimp.com> Message-Id: <20211026102234.3961636-13-alex.bennee@linaro.org>
2021-11-04tests/tcg: enable debian-nios2-cross for test buildingAlex Bennée
Now we have a nios2 test image we can start using it to build tests. However signal handling in nios2 is still broken so we disable the signals and linux-test tests that trigger the bug. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211026102234.3961636-12-alex.bennee@linaro.org>
2021-11-04tests/docker: split PARTIAL into PARTIAL and VIRTUAL imagesAlex Bennée
This is mostly to ensure we don't include the toolchain and bootstrap builds in DOCKER_IMAGES which is useful when verifying all images still build. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211026102234.3961636-10-alex.bennee@linaro.org>
2021-11-04tests/tcg: Fix some targets default cross compiler pathPhilippe Mathieu-Daudé
We do not want a shell command substitution, but a parameter substitution (with assignment). Replace $() -> ${}, otherwise the expanded command return an empty string and the $cross_cc variable is not set. Fixes: 634ef789f8e ("tests/tcg: add more default compilers to configure.sh") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [AJB: disable sh4 linux-test] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211023164329.328137-1-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211026102234.3961636-9-alex.bennee@linaro.org>
2021-11-04tests/tcg: Enable container_cross_cc for microblazeRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211014224435.2539547-8-richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211026102234.3961636-8-alex.bennee@linaro.org>
2021-11-04tests/docker: Add debian-microblaze-cross imageRichard Henderson
Build the entire cross tool chain from source. For this reason, default to caching. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [AJB: Update MAINTAINERS] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211014224435.2539547-7-richard.henderson@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211026102234.3961636-7-alex.bennee@linaro.org>
2021-11-04tests/docker: Add debian-nios2-cross imageRichard Henderson
Build the entire cross tool chain from source. For this reason, default to caching. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [AJB: honour NOUSER in cached fetch and build, update MAINTAINERS] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211014224435.2539547-6-richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20211026102234.3961636-6-alex.bennee@linaro.org>
2021-11-04Merge remote-tracking branch ↵Richard Henderson
'remotes/juanquintela/tags/migration-20211102-pull-request' into staging Migration Pull request Hi This are the pending migration patches on the list: - Provide an error message for migration_cancel by Laurent - Don't dump colo cache when a guest core is requested by Lukas - Initialise Compression_conters for new migration by Yuxiating On top of that I added another missing initialization - Colo optimizations and crash improvements by Rao. Please, apply. # gpg: Signature made Wed 03 Nov 2021 04:45:35 AM EDT # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] * remotes/juanquintela/tags/migration-20211102-pull-request: Optimized the function of fill_connection_key. colo: Don't dump colo cache if dump-guest-core=off Changed the last-mode to none of first start COLO Removed the qemu_fclose() in colo_process_incoming_thread colo: fixed 'Segmentation fault' when the simplex mode PVM poweroff Fixed SVM hang when do failover before PVM crash Fixed qemu crash when guest power off in COLO mode Some minor optimizations for COLO migration: Zero migration compression counters migration: initialise compression_counters for a new migration migration: provide an error message to migration_cancel() Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-03Hexagon HVX (tests/tcg/hexagon) histogram testTaylor Simpson
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (tests/tcg/hexagon) scatter_gather testTaylor Simpson
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (tests/tcg/hexagon) hvx_misc testTaylor Simpson
Tests for packet semantics vector loads (aligned and unaligned) vector stores (aligned and unaligned) vector masked stores vector new value store maximum HVX temps in a packet vector operations Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (tests/tcg/hexagon) vector_add_int testTaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) import instruction encodingsTaylor Simpson
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) instruction decodingTaylor Simpson
Add new file to target/hexagon/meson.build Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) import semanticsTaylor Simpson
Imported from the Hexagon architecture library imported/allext.idef Top level file for all extensions imported/mmvec/ext.idef HVX instruction definitions Support functions added to target/hexagon/genptr.c Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector storesTaylor Simpson
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector loadsTaylor Simpson
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector splat and absTaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector comparesTaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector logical opsTaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector max/minTaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector shiftsTaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector add & subTaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper overrides - vector assign & cmovTaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper overrides for histogram instructionsTaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper overrides infrastructureTaylor Simpson
Build the infrastructure to create overrides for HVX instructions. We create a new empty file (gen_tcg_hvx.h) that will be populated in subsequent patches. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) TCG generationTaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) helper functionsTaylor Simpson
Probe and commit vector stores (masked and scatter/gather) Log vector register writes Add the execution counters to the debug log Histogram instructions Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) instruction utility functionsTaylor Simpson
Functions to support scatter/gather Add new file to target/hexagon/meson.build Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) C preprocessor for decode treeTaylor Simpson
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) semantics generator - part 2Taylor Simpson
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) semantics generatorTaylor Simpson
Add HVX support to the semantics generator Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) import macro definitionsTaylor Simpson
Imported from the Hexagon architecture library imported/allext_macros.def Top level macro include for all extensions imported/macros.def Scalar core macros (some HVX here) imported/mmvec/macros.def HVX macro definitions The macro definition files specify instruction attributes that are applied to each instruction that reverences the macro. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) macrosTaylor Simpson
macros to interface with the generator macros referenced in instruction semantics Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) instruction attributesTaylor Simpson
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) register namesTaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to coreTaylor Simpson
HVX is a set of wide vector instructions. Machine state includes vector registers (VRegs) vector predicate registers (QRegs) temporary registers for intermediate values store buffer (masked stores and scatter/gather) Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) READMETaylor Simpson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingRichard Henderson
* Build system fixes and cleanups * DMA support in the multiboot option ROM * Rename default-bus-bypass-iommu * Deprecate -watchdog and cleanup -watchdog-action * HVF fix for <PAGE_SIZE regions * Support TSC scaling for AMD nested virtualization * Fix for ESP fuzzing bug # gpg: Signature made Tue 02 Nov 2021 10:57:37 AM EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] * remotes/bonzini/tags/for-upstream: (27 commits) configure: fix --audio-drv-list help message configure: Remove the check for the __thread keyword Move the l2tpv3 test from configure to meson.build meson: remove unnecessary coreaudio test program meson: remove pointless warnings meson.build: Allow to disable OSS again meson: bump submodule to 0.59.3 qtest/am53c974-test: add test for cancelling in-flight requests esp: ensure in-flight SCSI requests are always cancelled KVM: SVM: add migration support for nested TSC scaling hw/i386: fix vmmouse registration watchdog: remove select_watchdog_action vl: deprecate -watchdog watchdog: add information from -watchdog help to -device help hw/i386: Rename default_bus_bypass_iommu hvf: Avoid mapping regions < PAGE_SIZE as ram configure: do not duplicate CPU_CFLAGS into QEMU_LDFLAGS configure: remove useless NPTL probe target/i386: use DMA-enabled multiboot ROM for new-enough QEMU machine types optionrom: add a DMA-enabled multiboot ROM ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-03Merge remote-tracking branch ↵Richard Henderson
'remotes/vivier/tags/trivial-branch-for-6.2-pull-request' into staging Trivial patches branch pull request 20211101 v2 # gpg: Signature made Tue 02 Nov 2021 07:21:44 PM EDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] * remotes/vivier/tags/trivial-branch-for-6.2-pull-request: hw/input/lasips2: Fix typos in function names MAINTAINERS: Split HPPA TCG vs HPPA machines/hardware hw/core/machine: Add the missing delimiter in cpu_slot_to_string() monitor: Trim some trailing space from human-readable output Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-03Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211102-2' into stagingRichard Henderson
Add nuvoton sd module for NPCM7XX Add gdb-xml for MVE More uses of tcg_constant_* in target/arm Fix parameter naming for default-bus-bypass-iommu Ignore cache operations to mmio in HVF # gpg: Signature made Tue 02 Nov 2021 02:23:53 PM EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * remotes/rth/tags/pull-arm-20211102-2: hvf: arm: Ignore cache operations on MMIO hw/arm/virt: Rename default_bus_bypass_iommu target/arm: Use tcg_constant_i32() in gen_rev16() target/arm: Use tcg_constant_i64() in do_sat_addsub_64() target/arm: Use the constant variant of store_cpu_field() when possible target/arm: Introduce store_cpu_field_constant() helper target/arm: Use tcg_constant_i32() in op_smlad() target/arm: Advertise MVE to gdb when present tests/qtest/libqos: add SDHCI commands hw/arm: Attach MMC to quanta-gbs-bmc hw/arm: Add Nuvoton SD module to board hw/sd: add nuvoton MMC Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 20:23:37 +0000