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2019-12-16tests/acceptance: Makes linux_initrd and empty_cpu_model use QEMUMachineWainer dos Santos Moschetta
On linux_initrd and empty_cpu_model tests the same effect of calling QEMU through run() to inspect the terminated process is achieved with a sequence of set_qmp_monitor() / launch() / wait() commands on an QEMUMachine object. This patch changes those tests to use QEMUMachine instead, so they follow the same pattern to launch QEMU found on other acceptance tests. Signed-off-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Reviewed-by: Cleber Rosa <crosa@redhat.com> Tested-by: Cleber Rosa <crosa@redhat.com> Message-Id: <20191211185536.16962-3-wainersm@redhat.com> Signed-off-by: Cleber Rosa <crosa@redhat.com>
2019-12-16python/qemu: Add set_qmp_monitor() to QEMUMachineWainer dos Santos Moschetta
The QEMUMachine VM has a monitor setup on which an QMP connection is always attempted on _post_launch() (executed by launch()). In case the QEMU process immediatly exits then the qmp.accept() (used to establish the connection) stalls until it reaches timeout and consequently an exception raises. That behavior is undesirable when, for instance, it needs to gather information from the QEMU binary ($ qemu -cpu list) or a test which launches the VM expecting its failure. This patch adds the set_qmp_monitor() method to QEMUMachine that allows turn off the creation of the monitor machinery on VM launch. Signed-off-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Reviewed-by: Cleber Rosa <crosa@redhat.com> Message-Id: <20191211185536.16962-2-wainersm@redhat.com> [Cleber: trivial indentation fix] Signed-off-by: Cleber Rosa <crosa@redhat.com>
2019-12-16analyze-migration.py: replace numpy with python 3.2Marc-André Lureau
Use int.from_bytes() from python 3.2 instead. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20191127101038.327080-3-marcandre.lureau@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Cleber Rosa <crosa@redhat.com>
2019-12-16analyze-migration.py: fix find() type errorMarc-André Lureau
Traceback (most recent call last): File "../scripts/analyze-migration.py", line 611, in <module> dump.read(desc_only = True) File "../scripts/analyze-migration.py", line 513, in read self.load_vmsd_json(file) File "../scripts/analyze-migration.py", line 556, in load_vmsd_json vmsd_json = file.read_migration_debug_json() File "../scripts/analyze-migration.py", line 89, in read_migration_debug_json nulpos = data.rfind("\0") TypeError: argument should be integer or bytes-like object, not 'str' Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20191127101038.327080-2-marcandre.lureau@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Cleber Rosa <crosa@redhat.com>
2019-12-16Revert "Acceptance test: cancel test if m68k kernel packages goes missing"Philippe Mathieu-Daudé
Now than we use the stable snapshot archive, we can remove this check. This reverts commit d2499aca4bac613d837e2720e7bbe3378bc91245. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191126223810.20180-3-philmd@redhat.com> Tested-by: Willian Rampazzo <wrampazz@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Cleber Rosa <crosa@redhat.com>
2019-12-16tests/boot_linux_console: Fetch assets from Debian snapshot archivesPhilippe Mathieu-Daudé
The kernel packaged was fetched from an unstable repository. Use the stable snapshot archive instead. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191126223810.20180-2-philmd@redhat.com> Tested-by: Willian Rampazzo <wrampazz@redhat.com> Reviewed-by: Cleber Rosa <crosa@redhat.com> Tested-by: Cleber Rosa <crosa@redhat.com> Signed-off-by: Cleber Rosa <crosa@redhat.com>
2019-12-16Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20191216-1' into staging target-arm queue: * Add support for Cortex-M7 CPU * exynos4210_gic: Suppress gcc9 format-truncation warnings * aspeed: Various minor bug fixes and improvements * aspeed: Add support for the tacoma-bmc board * Honour HCR_EL32.TID1 and .TID2 trapping requirements * Handle trapping to EL2 of AArch32 VMRS instructions * Handle AArch32 CP15 trapping via HSTR_EL2 * Add support for missing Jazelle system registers * arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on * Add support for DC CVAP & DC CVADP instructions * Fix assertion when SCR.NS is changed in Secure-SVC &c * enable SHPC native hot plug in arm ACPI # gpg: Signature made Mon 16 Dec 2019 11:08:07 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20191216-1: (34 commits) target/arm: ensure we use current exception state after SCR update hw/arm/virt: Simplify by moving the gic in the machine state hw/arm/acpi: enable SHPC native hot plug hw/arm/acpi: simplify AML bit and/or statement hw/arm/sbsa-ref: Simplify by moving the gic in the machine state target/arm: Add support for DC CVAP & DC CVADP ins migration: ram: Switch to ram block writeback Memory: Enable writeback for given memory region tcg: cputlb: Add probe_read arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() target/arm: Add support for missing Jazelle system registers target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 target/arm: Handle trapping to EL2 of AArch32 VMRS instructions target/arm: Honor HCR_EL2.TID1 trapping requirements target/arm: Honor HCR_EL2.TID2 trapping requirements aspeed: Change the "nic" property definition aspeed: Change the "scu" property definition gpio: fix memory leak in aspeed_gpio_init() aspeed: Add support for the tacoma-bmc board aspeed: Remove AspeedBoardConfig array and use AspeedMachineClass ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16target/arm: ensure we use current exception state after SCR updateAlex Bennée
A write to the SCR can change the effective EL by droppping the system from secure to non-secure mode. However if we use a cached current_el from before the change we'll rebuild the flags incorrectly. To fix this we introduce the ARM_CP_NEWEL CP flag to indicate the new EL should be used when recomputing the flags. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191212114734.6962-1-alex.bennee@linaro.org Cc: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191209143723.6368-1-alex.bennee@linaro.org> Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16hw/arm/virt: Simplify by moving the gic in the machine statePhilippe Mathieu-Daudé
Make the gic a field in the machine state, and instead of filling an array of qemu_irq and passing it around, directly call qdev_get_gpio_in() on the gic field. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20191209090306.20433-1-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16hw/arm/acpi: enable SHPC native hot plugHeyi Guo
After the introduction of generic PCIe root port and PCIe-PCI bridge, we will also have SHPC controller on ARM, so just enable SHPC native hot plug. Also update tests/data/acpi/virt/DSDT* to pass "make check". Cc: Shannon Zhao <shannon.zhaosl@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Heyi Guo <guoheyi@huawei.com> Message-id: 20191209063719.23086-3-guoheyi@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16hw/arm/acpi: simplify AML bit and/or statementHeyi Guo
The last argument of AML bit and/or statement is the target variable, so we don't need to use a NULL target and then an additional store operation; using just aml_and() or aml_or() statement is enough. Also update tests/data/acpi/virt/DSDT* to pass "make check". Cc: Shannon Zhao <shannon.zhaosl@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Suggested-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Heyi Guo <guoheyi@huawei.com> Message-id: 20191209063719.23086-2-guoheyi@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16hw/arm/sbsa-ref: Simplify by moving the gic in the machine statePhilippe Mathieu-Daudé
Make the gic a field in the machine state, and instead of filling an array of qemu_irq and passing it around, directly call qdev_get_gpio_in() on the gic field. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20191206162303.30338-1-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16target/arm: Add support for DC CVAP & DC CVADP insBeata Michalska
ARMv8.2 introduced support for Data Cache Clean instructions to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence) - DV CVADP. Both specify conceptual points in a memory system where all writes that are to reach them are considered persistent. The support provided considers both to be actually the same so there is no distinction between the two. If none is available (there is no backing store for given memory) both will result in Data Cache Clean up to the point of coherency. Otherwise sync for the specified range shall be performed. Signed-off-by: Beata Michalska <beata.michalska@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191121000843.24844-5-beata.michalska@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16migration: ram: Switch to ram block writebackBeata Michalska
Switch to ram block writeback for pmem migration. Signed-off-by: Beata Michalska <beata.michalska@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 20191121000843.24844-4-beata.michalska@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16Memory: Enable writeback for given memory regionBeata Michalska
Add an option to trigger memory writeback to sync given memory region with the corresponding backing store, case one is available. This extends the support for persistent memory, allowing syncing on-demand. Signed-off-by: Beata Michalska <beata.michalska@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191121000843.24844-3-beata.michalska@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16tcg: cputlb: Add probe_readBeata Michalska
Add probe_read alongside the write probing equivalent. Signed-off-by: Beata Michalska <beata.michalska@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191121000843.24844-2-beata.michalska@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on()Niek Linnenbank
This change ensures that the FPU can be accessed in Non-Secure mode when the CPU core is reset using the arm_set_cpu_on() function call. The NSACR.{CP11,CP10} bits define the exception level required to access the FPU in Non-Secure mode. Without these bits set, the CPU will give an undefined exception trap on the first FPU access for the secondary cores under Linux. This is necessary because in this power-control codepath QEMU is effectively emulating a bit of EL3 firmware, and has to set the CPU up as the EL3 firmware would. Fixes: fc1120a7f5 Cc: qemu-stable@nongnu.org Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> [PMM: added clarifying para to commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16target/arm: Add support for missing Jazelle system registersMarc Zyngier
QEMU lacks the minimum Jazelle implementation that is required by the architecture (everything is RAZ or RAZ/WI). Add it together with the HCR_EL2.TID0 trapping that goes with it. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191201122018.25808-6-maz@kernel.org [PMM: moved ARMCPRegInfo array to file scope, marked it 'static global', moved new condition down in register_cp_regs_for_features() to go with other feature things rather than up with the v6/v7/v8 stuff] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16target/arm: Handle AArch32 CP15 trapping via HSTR_EL2Marc Zyngier
HSTR_EL2 offers a way to trap ranges of CP15 system register accesses to EL2, and it looks like this register is completely ignored by QEMU. To avoid adding extra .accessfn filters all over the place (which would have a direct performance impact), let's add a new TB flag that gets set whenever HSTR_EL2 is non-zero and that QEMU translates a context where this trap has a chance to apply, and only generate the extra access check if the hypervisor is actively using this feature. Tested with a hand-crafted KVM guest accessing CBAR. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191201122018.25808-5-maz@kernel.org [PMM: use is_a64(); fix comment syntax] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16target/arm: Handle trapping to EL2 of AArch32 VMRS instructionsMarc Zyngier
HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to EL2, and HCR_EL2.TID0 does the same for reads of FPSID. In order to handle this, introduce a new TCG helper function that checks for these control bits before executing the VMRC instruction. Tested with a hacked-up version of KVM/arm64 that sets the control bits for 32bit guests. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191201122018.25808-4-maz@kernel.org [PMM: move helper declaration to helper.h; make it TCG_CALL_NO_WG] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16target/arm: Honor HCR_EL2.TID1 trapping requirementsMarc Zyngier
HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1 (and their 32bit equivalents) as well as TCMTR, TLBTR are trapped to EL2. QEMU ignores it, making it harder for a hypervisor to virtualize the HW (though to be fair, no known hypervisor actually cares). Do the right thing by trapping to EL2 if HCR_EL2.TID1 is set. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191201122018.25808-3-maz@kernel.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16target/arm: Honor HCR_EL2.TID2 trapping requirementsMarc Zyngier
HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU completely ignores it, making it impossible for hypervisors to virtualize the cache hierarchy. Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191201122018.25808-2-maz@kernel.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed: Change the "nic" property definitionCédric Le Goater
The Aspeed MII model has a link pointing to its associated FTGMAC100 NIC in the machine. Change the "nic" property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-18-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed: Change the "scu" property definitionCédric Le Goater
The Aspeed Watchdog and Timer models have a link pointing to the SCU controller model of the machine. Change the "scu" property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-17-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16gpio: fix memory leak in aspeed_gpio_init()PanNengyuan
Address Sanitizer shows memory leak in hw/gpio/aspeed_gpio.c:875 Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: PanNengyuan <pannengyuan@huawei.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-16-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed: Add support for the tacoma-bmc boardCédric Le Goater
The Tacoma BMC board is replacement board for the BMC of the OpenPOWER Witherspoon system. It uses a AST2600 SoC instead of a AST2500 and the I2C layout is the same as it controls the same main board. Used for HW bringup. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-15-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed: Remove AspeedBoardConfig array and use AspeedMachineClassCédric Le Goater
AspeedBoardConfig is a redundant way to define class attributes and it complexifies the machine definition and initialization. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-14-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/smc: Add AST2600 timings registersCédric Le Goater
Each CS has its own Read Timing Compensation Register on newer SoCs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-13-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/smc: Do not map disabled segment on the AST2600Cédric Le Goater
The segments can be disabled on the AST2600 (zero register value). CS0 is open by default but not the other CS. This is closing the access to the flash device in user mode and forbids scanning. In the model, check the segment size and disable the associated region when the value is zero. Fixes: bcaa8ddd081c ("aspeed/smc: Add AST2600 support") Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-12-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/smc: Restore default AHB window mapping at resetCédric Le Goater
The current model only restores the Segment Register values but leaves the previous CS mapping behind. Introduce a helper setting the register value and mapping the region at the requested address. Use this helper when a Segment register is set and at reset. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-11-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16watchdog/aspeed: Fix AST2600 frequency behaviourJoel Stanley
The AST2600 control register sneakily changed the meaning of bit 4 without anyone noticing. It no longer controls the 1MHz vs APB clock select, and instead always runs at 1MHz. The AST2500 was always 1MHz too, but it retained bit 4, making it read only. We can model both using the same fixed 1MHz calculation. Fixes: 6b2b2a703cad ("hw: wdt_aspeed: Add AST2600 support") Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-10-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16watchdog/aspeed: Improve watchdog timeout messageJoel Stanley
Users benefit from knowing which watchdog timer has expired. The address of the watchdog's registers unambiguously indicates which has expired, so log that. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-9-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/scu: Fix W1C behaviorJoel Stanley
This models the clock write one to clear registers, and fixes up some incorrect behavior in all of the write to clear registers. There was also a typo in one of the register definitions. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-8-clg@kaod.org [clg: checkpatch.pl fixes ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/sdmc: Make ast2600 default 1GJoel Stanley
Most boards have this much. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-7-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/i2c: Add trace eventsCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-6-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/i2c: Add support for DMA transfersCédric Le Goater
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA transfers to and from DRAM. A pair of registers defines the buffer address and the length of the DMA transfer. The address should be aligned on 4 bytes and the maximum length should not exceed 4K. The receive or transmit DMA transfer can then be initiated with specific bits in the Command/Status register of the controller. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-5-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed: Add a DRAM memory region at the SoC levelCédric Le Goater
Currently, we link the DRAM memory region to the FMC model (for DMAs) through a property alias at the SoC level. The I2C model will need a similar region for DMA support, add a DRAM region property at the SoC level for both model to use. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/i2c: Check SRAM enablement on AST2500Cédric Le Goater
The SRAM must be enabled before using the Buffer Pool mode or the DMA mode. This is not required on other SoCs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16aspeed/i2c: Add support for pool buffer transfersCédric Le Goater
The Aspeed I2C controller can operate in different transfer modes : - Byte Buffer mode, using a dedicated register to transfer a byte. This is what the model supports today. - Pool Buffer mode, using an internal SRAM to transfer multiple bytes in the same command sequence. Each SoC has different SRAM characteristics. On the AST2400, 2048 bytes of SRAM are available at offset 0x800 of the controller AHB window. The pool buffer can be configured from 1 to 256 bytes per bus. On the AST2500, the SRAM is at offset 0x200 and the pool buffer is of 16 bytes per bus. On the AST2600, the SRAM is at offset 0xC00 and the pool buffer is of 32 bytes per bus. It can be splitted in two for TX and RX but the current model does not add support for it as it it unused by known drivers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-2-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16exynos4210_gic: Suppress gcc9 format-truncation warningsDavid Gibson
exynos4210_gic_realize() prints the number of cpus into some temporary buffers, but it only allows 3 bytes space for it. That's plenty: existing machines will only ever set this value to EXYNOS4210_NCPUS (2). But the compiler can't always figure that out, so some[*] gcc9 versions emit -Wformat-truncation warnings. We can fix that by hinting the constraint to the compiler with a suitably placed assert(). [*] The bizarre thing here, is that I've long gotten these warnings compiling in a 32-bit x86 container as host - Fedora 30 with gcc-9.2.1-1.fc30.i686 - but it compiles just fine on my normal x86_64 host - Fedora 30 with and gcc-9.2.1-1.fc30.x86_64. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: deleted stray blank line] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16target/arm: Add support for cortex-m7 CPUChristophe Lyon
This is derived from cortex-m4 description, adding DP support and FPv5 instructions with the corresponding flags in isar and mvfr2. Checked that it could successfully execute vrinta.f32 s15, s15 while cortex-m4 emulation rejects it with "illegal instruction". Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20191025090841.10299-1-christophe.lyon@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20191214-2' into stagingPeter Maydell
First s390x update for 5.0: - compat machines (also for other architectures) - cleanups and fixes in reset handling - fence off guest-set-time, as we have no hwclock - fix some misuses of the error API - further cleanups # gpg: Signature made Sat 14 Dec 2019 09:33:17 GMT # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20191214-2: qga: fence guest-set-time if hwclock not available s390x/tcg: clear local interrupts on reset normal s390x/cpumodel: Fix query-cpu-definitions error API violations s390x/cpumodel: Fix query-cpu-model-FOO error API violations s390x/cpumodel: Fix realize() error API violations s390x/cpumodel: Fix feature property error API violations s390x/event-facility: Fix realize() error API violations s390x: Fix cpu normal reset ri clearing s390x: kvm: Make kvm_sclp_service_call void s390x: Beautify diag308 handling s390x: Move clear reset s390x: Move initial reset s390x: Move reset normal to shared reset handler s390x: Don't do a normal reset on the initial cpu hw: add compat machines for 5.0 vfio-ccw: Fix error message Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-14qga: fence guest-set-time if hwclock not availableCornelia Huck
The Posix implementation of guest-set-time invokes hwclock to set/retrieve the time to/from the hardware clock. If hwclock is not available, the user is currently informed that "hwclock failed to set hardware clock to system time", which is quite misleading. This may happen e.g. on s390x, which has a different timekeeping concept anyway. Let's check for the availability of the hwclock command and return QERR_UNSUPPORTED for guest-set-time if it is not available. Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com> Message-Id: <20191205115350.18713-1-cohuck@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-14s390x/tcg: clear local interrupts on reset normalCornelia Huck
We neglected to clean up pending interrupts and emergency signals; fix that. Message-Id: <20191206135404.16051-1-cohuck@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com>
2019-12-14s390x/cpumodel: Fix query-cpu-definitions error API violationsMarkus Armbruster
qmp_query_cpu_definitions() passes @errp to get_max_cpu_model(), then frees any error it gets back. This effectively ignores errors. Dereferencing @errp is wrong; see the big comment in error.h. Passing @errp is also wrong, because it works only as long as @errp is neither @error_fatal nor @error_abort. Introduced in commit 38cba1f4d8 "s390x: return unavailable features via query-cpu-definitions". No caller actually passes such @errp values. Fix anyway: simply pass NULL to get_max_cpu_model(). Cc: David Hildenbrand <david@redhat.com> Cc: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20191204093625.14836-16-armbru@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-14s390x/cpumodel: Fix query-cpu-model-FOO error API violationsMarkus Armbruster
cpu_model_from_info() is a helper for qmp_query_cpu_model_expansion(), qmp_query_cpu_model_comparison(), qmp_query_cpu_model_baseline(). It dereferences @errp when the visitor or the QOM setter fails. That's wrong; see the big comment in error.h. Introduced in commit 137974cea3 's390x/cpumodel: implement QMP interface "query-cpu-model-expansion"'. Its three callers have the same issue. Introduced in commit 4e82ef0502 's390x/cpumodel: implement QMP interface "query-cpu-model-comparison"' and commit f1a47d08ef 's390x/cpumodel: implement QMP interface "query-cpu-model-baseline"'. No caller actually passes null. Fix anyway: splice in a local Error *err, and error_propagate(). Cc: David Hildenbrand <david@redhat.com> Cc: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20191204093625.14836-15-armbru@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-14s390x/cpumodel: Fix realize() error API violationsMarkus Armbruster
get_max_cpu_model() dereferences @errp when kvm_s390_get_host_cpu_model() fails, apply_cpu_model() dereferences it when kvm_s390_apply_cpu_model() fails, and s390_realize_cpu_model() dereferences it when get_max_cpu_model() or check_compatibility() fail. That's wrong; see the big comment in error.h. All three introduced in commit 80560137cf "s390x/cpumodel: check and apply the CPU model". No caller actually passes null. Fix anyway: splice in a local Error *err, and error_propagate(). Cc: David Hildenbrand <david@redhat.com> Cc: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20191204093625.14836-14-armbru@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-14s390x/cpumodel: Fix feature property error API violationsMarkus Armbruster
s390x-cpu property setters set_feature() and set_feature_group() dereference @errp when the visitor fails. That's wrong; see the big comment in error.h. Introduced in commit 0754f60429 "s390x/cpumodel: expose features and feature groups as properties". No caller actually passes null. Fix anyway: splice in a local Error *err, and error_propagate(). Cc: David Hildenbrand <david@redhat.com> Cc: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20191204093625.14836-13-armbru@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-14s390x/event-facility: Fix realize() error API violationsMarkus Armbruster
sclp_events_bus_realize() dereferences @errp when object_property_set_bool() fails. That's wrong; see the big comment in error.h. Introduced in commit f6102c329c "s390/sclp: rework sclp event facility initialization + device realization". No caller actually passes null. Fix anyway: splice in a local Error *err, and error_propagate(). Cc: David Hildenbrand <david@redhat.com> Cc: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20191204093625.14836-12-armbru@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-12-14s390x: Fix cpu normal reset ri clearingJanosch Frank
As it turns out we need to clear the ri controls and PSW enablement bit to be architecture compliant. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20191203132813.2734-4-frankja@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-18 01:30:56 +0000