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2021-10-18bsd-user/mmap.c: Don't mmap fd == -1 independently from MAP_ANON flagWarner Losh
Switch checks for !(flags & MAP_ANONYMOUS) with checks for fd != -1. MAP_STACK and MAP_GUARD both require fd == -1 and don't require mapping the fd either. Add analysis from Guy Yur detailing the different cases for MAP_GUARD and MAP_STACK. Signed-off-by: Guy Yur <guyyur@gmail.com> [ partially merged before, finishing the job and documenting origin] Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Kyle Evans <kevans@FreeBSD.org>
2021-10-18Merge remote-tracking branch 'remotes/philmd/tags/mips-20211018' into stagingRichard Henderson
MIPS patches queue Hardware emulation: - Generate FDT blob for Boston machine (Jiaxun) - VIA chipset cleanups (Zoltan) TCG: - Use tcg_constant() in Compact branch and MSA opcodes - Restrict nanoMIPS DSP MULT[U] opcode accumulator to Rel6 - Fix DEXTRV_S.H DSP opcode - Remove unused TCG temporary for some DSP opcodes # gpg: Signature made Sun 17 Oct 2021 03:50:57 PM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * remotes/philmd/tags/mips-20211018: via-ide: Avoid using isa_get_irq() vt82c686: Add a method to VIA_ISA to raise ISA interrupts vt82c686: Move common code to via_isa_realize via-ide: Set user_creatable to false target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn() target/mips: Fix DEXTRV_S.H DSP opcode target/mips: Use tcg_constant_tl() in gen_compute_compact_branch() target/mips: Use explicit extract32() calls in gen_msa_i5() target/mips: Use tcg_constant_i32() in gen_msa_3rf() target/mips: Use tcg_constant_i32() in gen_msa_2r() target/mips: Use tcg_constant_i32() in gen_msa_2rf() target/mips: Use tcg_constant_i32() in gen_msa_elm_df() target/mips: Remove unused register from MSA 2R/2RF instruction format hw/mips/boston: Add FDT generator hw/mips/boston: Allow loading elf kernel and dtb hw/mips/boston: Massage memory map information target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-18bsd-user/mmap.c: Convert to qemu_log logging for mmap debuggingWarner Losh
Convert DEBUG_MMAP to qemu_log CPU_LOG_PAGE. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Kyle Evans <kevans@FreeBSD.org>
2021-10-17bsd-user/mmap.c: mmap prefer MAP_ANON for BSDWarner Losh
MAP_ANON and MAP_ANONYMOUS are identical. Prefer MAP_ANON for BSD since the file is now a confusing mix of the two. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Kyle Evans <kevans@FreeBSD.org>
2021-10-17bsd-user/mmap.c: mmap return ENOMEM on overflowWarner Losh
mmap should return ENOMEM on len overflow rather than EINVAL. Return EINVAL when len == 0 and ENOMEM when the rounded to a page length is 0. Found by make check-tcg. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Kyle Evans <kevans@FreeBSD.org>
2021-10-17bsd-user/mmap.c: MAP_ symbols are defined, so no need for ifdefsWarner Losh
All these MAP_ symbols are always defined on supported FreeBSD versions (12.2 and newer), so remove the #ifdefs since they aren't needed. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Kyle Evans <kevans@FreeBSD.org>
2021-10-17bsd-user/mmap.c: check pread's return value to fix warnings with _FORTIFY_SOURCEMikaël Urankar
Simmilar to the equivalent linux-user: commit fb7e378cf9c, which added checking to pread's return value. Update to current qemu standards with {} around the if statement. Signed-off-by: Mikaël Urankar <mikael.urankar@gmail.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Kyle Evans <kevans@FreeBSD.org>
2021-10-17bsd-user/mmap.c: Always zero MAP_ANONYMOUS memory in mmap_frag()Mikaël Urankar
Similar to the equivalent linux-user commit e6deac9cf99 When mapping MAP_ANONYMOUS memory fragments, still need notice about to set it zero, or it will cause issues. Signed-off-by: Mikaël Urankar <mikael.urankar@gmail.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Kyle Evans <kevans@FreeBSD.org>
2021-10-18via-ide: Avoid using isa_get_irq()BALATON Zoltan
Use via_isa_set_irq() which better encapsulates irq handling in the vt82xx model and avoids using isa_get_irq() that has a comment saying it should not be used. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <26cb1848c9fc0360df7a57c2c9ba5e03c4a692b5.1634259980.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-10-18vt82c686: Add a method to VIA_ISA to raise ISA interruptsBALATON Zoltan
Other functions in the VT82xx chips need to raise ISA interrupts. Keep a reference to them in the device state and add via_isa_set_irq() to allow setting their state. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <778c04dc2c8affac060b8edf9e8d7dab3c3e04eb.1634259980.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-10-18vt82c686: Move common code to via_isa_realizeBALATON Zoltan
The vt82c686b_realize and vt8231_realize methods are almost identical, factor out the common parts to a via_isa_realize function to avoid code duplication. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <7cb7a16ff4daf8f48d576246255bea1fd355207c.1634259980.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-10-18via-ide: Set user_creatable to falseBALATON Zoltan
This model only works as a function of the via superio chip not as a standalone PCI device. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211015092159.3E863748F57@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-10-18target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()Philippe Mathieu-Daudé
Since gen_mipsdsp_accinsn() got added in commit b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions"), the 'v2_t' TCG temporary has never been used. Remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211014224551.2204949-1-f4bug@amsat.org>
2021-10-18target/mips: Fix DEXTRV_S.H DSP opcodePhilippe Mathieu-Daudé
While for the DEXTR_S.H opcode: "The shift argument is provided in the instruction." For the DEXTRV_S.H opcode we have: "The five least-significant bits of register rs provide the shift argument, interpreted as a five-bit unsigned integer; the remaining bits in rs are ignored." While 't1' contains the 'rs' register content (the shift value for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H. We can directly use the v1_t TCG register which already contains this shift value. Fixes: b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211013215652.1764551-1-f4bug@amsat.org>
2021-10-18target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()Philippe Mathieu-Daudé
The offset is constant and read-only: move it to the constant pool. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211003175743.3738710-9-f4bug@amsat.org>
2021-10-18target/mips: Use explicit extract32() calls in gen_msa_i5()Philippe Mathieu-Daudé
We already use sextract32(), use extract32() for completeness instead of open-coding it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211003175743.3738710-7-f4bug@amsat.org>
2021-10-18target/mips: Use tcg_constant_i32() in gen_msa_3rf()Philippe Mathieu-Daudé
Avoid using a TCG temporary by moving Data Format to the constant pool. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211003175743.3738710-6-f4bug@amsat.org>
2021-10-18target/mips: Use tcg_constant_i32() in gen_msa_2r()Philippe Mathieu-Daudé
Avoid using a TCG temporary by moving Data Format to the constant pool. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211003175743.3738710-5-f4bug@amsat.org>
2021-10-18target/mips: Use tcg_constant_i32() in gen_msa_2rf()Philippe Mathieu-Daudé
Avoid using a TCG temporary by moving Data Format to the constant pool. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211003175743.3738710-4-f4bug@amsat.org>
2021-10-18target/mips: Use tcg_constant_i32() in gen_msa_elm_df()Philippe Mathieu-Daudé
Data Format is a 2-bit constant value. Avoid using a TCG temporary by moving it to the constant pool. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211003175743.3738710-3-f4bug@amsat.org>
2021-10-18target/mips: Remove unused register from MSA 2R/2RF instruction formatPhilippe Mathieu-Daudé
Commits cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions") and 3bdeb68866e ("target-mips: add MSA 2RF format instructions") added the MSA 2R/2RF instructions. However these instructions don't use any target vector register, so remove the unused TCG temporaries. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211003175743.3738710-2-f4bug@amsat.org>
2021-10-18hw/mips/boston: Add FDT generatorJiaxun Yang
Generate FDT on our own if no dtb argument supplied. Avoid introducing unused device in FDT with user supplied dtb. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> [PMD: Fix coding style] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211002184539.169-4-jiaxun.yang@flygoat.com>
2021-10-18hw/mips/boston: Allow loading elf kernel and dtbJiaxun Yang
ELF kernel allows us debugging much easier with DWARF symbols. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Fix coding style] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211002184539.169-3-jiaxun.yang@flygoat.com>
2021-10-18hw/mips/boston: Massage memory map informationJiaxun Yang
Use memmap array to uinfy address of memory map. That would allow us reuse address information for FDT generation. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Use local 'regaddr' in gen_firmware(), fix coding style] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211002184539.169-2-jiaxun.yang@flygoat.com>
2021-10-17target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6Philippe Mathieu-Daudé
Per the "MIPS Architecture Extension: nanoMIPS32 DSP TRM" rev 0.04, MULT and MULTU opcodes: The value of ac selects an accumulator numbered from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS32 architecture. In Release 6 of the MIPS Architecture, accumulators are eliminated from MIPS32. Ensure pre-Release 6 is restricted to HI/LO registers pair. Fixes: 8b3698b2947 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part 4") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-10-16Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211016' into stagingRichard Henderson
Move gdb singlestep to generic code Fix cpu_common_props # gpg: Signature made Sat 16 Oct 2021 11:13:54 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * remotes/rth/tags/pull-tcg-20211016: (24 commits) Revert "cpu: Move cpu_common_props to hw/core/cpu.c" target/xtensa: Drop check for singlestep_enabled target/tricore: Drop check for singlestep_enabled target/sh4: Drop check for singlestep_enabled target/s390x: Drop check for singlestep_enabled target/rx: Drop checks for singlestep_enabled target/riscv: Remove exit_tb and lookup_and_goto_ptr target/riscv: Remove dead code after exception target/ppc: Drop exit checks for singlestep_enabled target/openrisc: Drop checks for singlestep_enabled target/mips: Drop exit checks for singlestep_enabled target/mips: Fix single stepping target/microblaze: Drop checks for singlestep_enabled target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP target/m68k: Drop checks for singlestep_enabled target/i386: Drop check for singlestep_enabled target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt target/hppa: Drop checks for singlestep_enabled target/arm: Drop checks for singlestep_enabled target/hexagon: Drop checks for singlestep_enabled ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15Revert "cpu: Move cpu_common_props to hw/core/cpu.c"Richard Henderson
This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f. Despite a comment saying why cpu_common_props cannot be placed in a file that is compiled once, it was moved anyway. Revert that. Since then, Property is not defined in hw/core/cpu.h, so it is now easier to declare a function to install the properties rather than the Property array itself. Cc: Eduardo Habkost <ehabkost@redhat.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/xtensa: Drop check for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/tricore: Drop check for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/sh4: Drop check for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/s390x: Drop check for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/rx: Drop checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson
GDB single-stepping is now handled generically, which means we don't need to do anything in the wrappers. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/riscv: Remove dead code after exceptionRichard Henderson
We have already set DISAS_NORETURN in generate_exception, which makes the exit_tb unreachable. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/ppc: Drop exit checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Reuse gen_debug_exception to handle architectural debug exceptions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/openrisc: Drop checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/mips: Drop exit checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/mips: Fix single steppingRichard Henderson
As per an ancient comment in mips_tr_translate_insn about the expectations of gdb, when restarting the insn in a delay slot we also re-execute the branch. Which means that we are expected to execute two insns in this case. This has been broken since 8b86d6d2580, where we forced max_insns to 1 while single-stepping. This resulted in an exit from the translator loop after the branch but before the delay slot is translated. Increase the max_insns to 2 for this case. In addition, bypass the end-of-page check, for when the branch itself ends the page. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/microblaze: Drop checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMPRichard Henderson
We were using singlestep_enabled as a proxy for whether translator_use_goto_tb would always return false. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/m68k: Drop checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Acked-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/i386: Drop check for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/i386: Check CF_NO_GOTO_TB for dc->jmp_optRichard Henderson
We were using singlestep_enabled as a proxy for whether translator_use_goto_tb would always return false. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/hppa: Drop checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/arm: Drop checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/hexagon: Drop checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/cris: Drop checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/avr: Drop checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Tested-by: Michael Rolnik <mrolnik@gmail.com> Reviewed-by: Michael Rolnik <mrolnik@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/alpha: Drop checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15accel/tcg: Handle gdb singlestep in cpu_tb_execRichard Henderson
Currently the change in cpu_tb_exec is masked by the debug exception being raised by the translators. But this allows us to remove that code. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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