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2018-04-26Change references to serial_hds[] to serial_hd()Peter Maydell
Change all the uses of serial_hds[] to go via the new serial_hd() function. Code change produced with: find hw -name '*.[ch]' | xargs sed -i -e 's/serial_hds\[\([^]]*\)\]/serial_hd(\1)/g' Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20180420145249.32435-8-peter.maydell@linaro.org
2018-04-26vl.c: Provide accessor function serial_hd() for serial_hds[] arrayPeter Maydell
Provide an accessor function serial_hd() to return the Chardev (if any) associated with the numbered serial port. This will be used to replace direct accesses to the serial_hds[] array, so that calling code doesn't need to care about the size of that array. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180420145249.32435-7-peter.maydell@linaro.org
2018-04-26hw/xtensa/xtfpga.c: Don't create "null" chardevs for serial devicesPeter Maydell
Following commit 12051d82f004024, UART devices should handle being passed a NULL pointer chardev, so we don't need to create "null" backends in board code. Remove the code that does this and updates serial_hds[]. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180420145249.32435-6-peter.maydell@linaro.org
2018-04-26hw/mips/mips_malta: Don't create "null" chardevs for serial devicesPeter Maydell
Following commit 12051d82f004024, UART devices should handle being passed a NULL pointer chardev, so we don't need to create "null" backends in board code. Remove the code that does this and updates serial_hds[]. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180420145249.32435-5-peter.maydell@linaro.org
2018-04-26hw/mips/boston.c: Don't create "null" chardevs for serial devicesPeter Maydell
Following commit 12051d82f004024, UART devices should handle being passed a NULL pointer chardev, so we don't need to create "null" backends in board code. Remove the code that does this and updates serial_hds[]. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180420145249.32435-4-peter.maydell@linaro.org
2018-04-26hw/arm/fsl-imx*: Don't create "null" chardevs for serial devicesPeter Maydell
Following commit 12051d82f004024, UART devices should handle being passed a NULL pointer chardev, so we don't need to create "null" backends in board code. Remove the code that does this and updates serial_hds[]. (fsl-imx7.c was already written this way.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20180420145249.32435-3-peter.maydell@linaro.org
2018-04-26hw/char/serial: Allow disconnected chardevsPeter Maydell
Currently the serial.c realize code has an explicit check that it is not connected to a disconnected backend (ie one with a NULL chardev). This isn't what we want -- you should be able to create a serial device even if it isn't attached to anything. Remove the check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-id: 20180420145249.32435-2-peter.maydell@linaro.org
2018-04-26Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20180426' into staging target-arm queue: * xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo * timer/aspeed: fix vmstate version id * hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM * hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate' * hw/arm/highbank: don't make sysram 'nomigrate' * hw/arm/raspi: Don't bother setting default_cpu_type * PMU emulation: some minor bugfixes and preparation for support of other events than just the cycle counter * target/arm: Use v7m_stack_read() for reading the frame signature * target/arm: Remove stale TODO comment * arm: always start from first_cpu when registering loader cpu reset callback * device_tree: Increase FDT_MAX_SIZE to 1 MiB # gpg: Signature made Thu 26 Apr 2018 11:46:31 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180426: xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo timer/aspeed: fix vmstate version id hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate' hw/arm/highbank: don't make sysram 'nomigrate' hw/arm/raspi: Don't bother setting default_cpu_type target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide target/arm: Fix bitmask for PMCCFILTR writes target/arm: Allow EL change hooks to do IO target/arm: Add pre-EL change hooks target/arm: Support multiple EL change hooks target/arm: Fetch GICv3 state directly from CPUARMState target/arm: Mask PMU register writes based on PMCR_EL0.N target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0 target/arm: Check PMCNTEN for whether PMCCNTR is enabled target/arm: Use v7m_stack_read() for reading the frame signature target/arm: Remove stale TODO comment arm: always start from first_cpu when registering loader cpu reset callback device_tree: Increase FDT_MAX_SIZE to 1 MiB Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26Open 2.13 development treePeter Maydell
Unfortunately I forgot to do this before applying the merge in commit 8e383d19b44863556, so that commit will incorrectly claim to be 2.12 even though it isn't in the official 2.12 release. Oops. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26xilinx_spips: Correct SNOOP_NONE state when flushing the txfifoSai Pavan Boddu
SNOOP_NONE state handle is moved above in the if ladder, as it's same as SNOOP_STRIPPING during data cycles. Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-id: 1524119244-1240-1-git-send-email-saipava@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26timer/aspeed: fix vmstate version idCédric Le Goater
commit 1d3e65aa7ac5 ("hw/timer: Add value matching support to aspeed_timer") increased the vmstate version of aspeed.timer because the state had changed, but it also bumped the version of the VMSTATE_STRUCT_ARRAY under the aspeed.timerctrl which did not need to. Change back this version to fix migration. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180423101433.17759-1-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAMPeter Maydell
Currently we use vmstate_register_ram_global() for the SRAM; this is not a good idea for devices, because it means that you can only ever create one instance of the device, as the second instance would get a RAM block name clash. Instead, use memory_region_init_ram(), which automatically registers the RAM block with a local-to-the-device name. Note that this would be a cross-version migration compatibility break for the "palmetto-bmc", "ast2500-evb" and "romulus-bmc" machines, but migration is currently broken for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180420124835.7268-4-peter.maydell@linaro.org
2018-04-26hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'Peter Maydell
Currently we use memory_region_init_ram_nomigrate() to create the "aspeed.boot_rom" memory region, and we don't manually register it with vmstate_register_ram(). This currently means that its contents are migrated but as a ram block whose name is the empty string; in future it may mean they are not migrated at all. Use memory_region_init_ram() instead. Note that would be a cross-version migration compatibility break for the "palmetto-bmc", "ast2500-evb" and "romulus-bmc" machines, but migration is currently broken for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180420124835.7268-3-peter.maydell@linaro.org
2018-04-26hw/arm/highbank: don't make sysram 'nomigrate'Peter Maydell
Currently we use memory_region_init_ram_nomigrate() to create the "highbank.sysram" memory region, and we don't manually register it with vmstate_register_ram(). This currently means that its contents are migrated but as a ram block whose name is the empty string; in future it may mean they are not migrated at all. Use memory_region_init_ram() instead. Note that this is a cross-version migration compatibility break for the "highbank" and "midway" machines. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180420124835.7268-2-peter.maydell@linaro.org
2018-04-26hw/arm/raspi: Don't bother setting default_cpu_typePeter Maydell
In commit 210f47840dd62, we changed the bcm2836 SoC object to always create a CPU of the correct type for that SoC model. This makes the default_cpu_type settings in the MachineClass structs for the raspi2 and raspi3 boards redundant. We didn't change those at the time because it would have meant a temporary regression in a corner case of error handling if the user requested a non-existing CPU type. The -cpu parse handling changes in 2278b93941d42c3 mean that it no longer implicitly depends on default_cpu_type for this to work, so we can now delete the redundant default_cpu_type fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180420155547.9497-1-peter.maydell@linaro.org
2018-04-26target/arm: Make PMOVSCLR and PMUSERENR 64 bits wideAaron Lindsay
This is a bug fix to ensure 64-bit reads of these registers don't read adjacent data. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Message-id: 1523997485-1905-13-git-send-email-alindsay@codeaurora.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26target/arm: Fix bitmask for PMCCFILTR writesAaron Lindsay
It was shifted to the left one bit too few. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1523997485-1905-10-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26target/arm: Allow EL change hooks to do IOAaron Lindsay
During code generation, surround CPSR writes and exception returns which call the EL change hooks with gen_io_start/end. The immediate need is for the PMU to access the clock and icount during EL change to support mode filtering. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Message-id: 1523997485-1905-9-git-send-email-alindsay@codeaurora.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26target/arm: Add pre-EL change hooksAaron Lindsay
Because the design of the PMU requires that the counter values be converted between their delta and guest-visible forms for mode filtering, an additional hook which occurs before the EL is changed is necessary. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Message-id: 1523997485-1905-8-git-send-email-alindsay@codeaurora.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26target/arm: Support multiple EL change hooksAaron Lindsay
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Message-id: 1523997485-1905-7-git-send-email-alindsay@codeaurora.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26target/arm: Fetch GICv3 state directly from CPUARMStateAaron Lindsay
This eliminates the need for fetching it from el_change_hook_opaque, and allows for supporting multiple el_change_hooks without having to hack something together to find the registered opaque belonging to GICv3. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1523997485-1905-6-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26target/arm: Mask PMU register writes based on PMCR_EL0.NAaron Lindsay
This is in preparation for enabling counters other than PMCCNTR Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1523997485-1905-5-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0Aaron Lindsay
They share the same underlying state Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1523997485-1905-3-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26target/arm: Check PMCNTEN for whether PMCCNTR is enabledAaron Lindsay
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1523997485-1905-2-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26target/arm: Use v7m_stack_read() for reading the frame signaturePeter Maydell
In commit 95695effe8caa552b8f2 we changed the v7M/v8M stack pop code to use a new v7m_stack_read() function that checks whether the read should fail due to an MPU or bus abort. We missed one call though, the one which reads the signature word for the callee-saved register part of the frame. Correct the omission. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180419142106.9694-1-peter.maydell@linaro.org
2018-04-26target/arm: Remove stale TODO commentPeter Maydell
Remove a stale TODO comment -- we have now made the arm_ldl_ptw() and arm_ldq_ptw() functions propagate physical memory read errors out to their callers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180419142151.9862-1-peter.maydell@linaro.org
2018-04-26arm: always start from first_cpu when registering loader cpu reset callbackIgor Mammedov
if arm_load_kernel() were passed non first_cpu, QEMU would end up with partially set do_cpu_reset() callback leaving some CPUs without it. Make sure that do_cpu_reset() is registered for all CPUs by enumerating CPUs from first_cpu. (In practice every board that we have was passing us the first CPU as the boot CPU, either directly or indirectly, so this wasn't causing incorrect behaviour.) Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added a note that this isn't a behaviour change] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26device_tree: Increase FDT_MAX_SIZE to 1 MiBGeert Uytterhoeven
It is not uncommon for a contemporary FDT to be larger than 64 KiB, leading to failures loading the device tree from sysfs: qemu-system-aarch64: qemu_fdt_setprop: Couldn't set ...: FDT_ERR_NOSPACE Hence increase the limit to 1 MiB, like on PPC. For reference, the largest arm64 DTB created from the Linux sources is ca. 75 KiB large (100 KiB when built with symbols/fixup support). Cc: qemu-stable@nongnu.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Message-id: 1523541337-23919-1-git-send-email-geert+renesas@glider.be Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-26Merge remote-tracking branch ↵Peter Maydell
'remotes/dgilbert/tags/pull-migration-20180425a' into staging Migration pull for 2.13 Alexey Perevalov postcopy blocktime statistics Xiao Guangrong's compression performance improvements # gpg: Signature made Wed 25 Apr 2018 20:21:13 BST # gpg: using RSA key 0516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert/tags/pull-migration-20180425a: migration: remove ram_save_compressed_page() migration: introduce save_normal_page() migration: move calling save_zero_page to the common place migration: move calling control_save_page to the common place migration: move some code to ram_save_host_page migration: introduce control_save_page() migration: detect compression and decompression errors migration: stop decompression to allocate and free memory frequently migration: stop compression to allocate and free memory frequently migration: stop compressing page in migration thread migration: add postcopy total blocktime into query-migrate migration: add blocktime calculation into migration-test migration: postcopy_blocktime documentation migration: calculate vCPU blocktime on dst side migration: add postcopy blocktime ctx into MigrationIncomingState migration: introduce postcopy-blocktime capability Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-25migration: remove ram_save_compressed_page()Xiao Guangrong
Now, we can reuse the path in ram_save_page() to post the page out as normal, then the only thing remained in ram_save_compressed_page() is compression that we can move it out to the caller Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Xiao Guangrong <xiaoguangrong@tencent.com> Message-Id: <20180330075128.26919-11-xiaoguangrong@tencent.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: introduce save_normal_page()Xiao Guangrong
It directly sends the page to the stream neither checking zero nor using xbzrle or compression Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Xiao Guangrong <xiaoguangrong@tencent.com> Message-Id: <20180330075128.26919-10-xiaoguangrong@tencent.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: move calling save_zero_page to the common placeXiao Guangrong
save_zero_page() is always our first approach to try, move it to the common place before calling ram_save_compressed_page and ram_save_page Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Xiao Guangrong <xiaoguangrong@tencent.com> Message-Id: <20180330075128.26919-9-xiaoguangrong@tencent.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: move calling control_save_page to the common placeXiao Guangrong
The function is called by both ram_save_page and ram_save_target_page, so move it to the common caller to cleanup the code Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Xiao Guangrong <xiaoguangrong@tencent.com> Message-Id: <20180330075128.26919-8-xiaoguangrong@tencent.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: move some code to ram_save_host_pageXiao Guangrong
Move some code from ram_save_target_page() to ram_save_host_page() to make it be more readable for latter patches that dramatically clean ram_save_target_page() up Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Xiao Guangrong <xiaoguangrong@tencent.com> Message-Id: <20180330075128.26919-7-xiaoguangrong@tencent.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: introduce control_save_page()Xiao Guangrong
Abstract the common function control_save_page() to cleanup the code, no logic is changed Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Xiao Guangrong <xiaoguangrong@tencent.com> Message-Id: <20180330075128.26919-6-xiaoguangrong@tencent.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: detect compression and decompression errorsXiao Guangrong
Currently the page being compressed is allowed to be updated by the VM on the source QEMU, correspondingly the destination QEMU just ignores the decompression error. However, we completely miss the chance to catch real errors, then the VM is corrupted silently To make the migration more robuster, we copy the page to a buffer first to avoid it being written by VM, then detect and handle the errors of both compression and decompression errors properly Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Xiao Guangrong <xiaoguangrong@tencent.com> Message-Id: <20180330075128.26919-5-xiaoguangrong@tencent.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: stop decompression to allocate and free memory frequentlyXiao Guangrong
Current code uses uncompress() to decompress memory which manages memory internally, that causes huge memory is allocated and freed very frequently, more worse, frequently returning memory to kernel will flush TLBs So, we maintain the memory by ourselves and reuse it for each decompression Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Jiang Biao <jiang.biao2@zte.com.cn> Signed-off-by: Xiao Guangrong <xiaoguangrong@tencent.com> Message-Id: <20180330075128.26919-4-xiaoguangrong@tencent.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: stop compression to allocate and free memory frequentlyXiao Guangrong
Current code uses compress2() to compress memory which manages memory internally, that causes huge memory is allocated and freed very frequently More worse, frequently returning memory to kernel will flush TLBs and trigger invalidation callbacks on mmu-notification which interacts with KVM MMU, that dramatically reduce the performance of VM So, we maintain the memory by ourselves and reuse it for each compression Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Jiang Biao <jiang.biao2@zte.com.cn> Signed-off-by: Xiao Guangrong <xiaoguangrong@tencent.com> Message-Id: <20180330075128.26919-3-xiaoguangrong@tencent.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: stop compressing page in migration threadXiao Guangrong
As compression is a heavy work, do not do it in migration thread, instead, we post it out as a normal page Reviewed-by: Wei Wang <wei.w.wang@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Xiao Guangrong <xiaoguangrong@tencent.com> Message-Id: <20180330075128.26919-2-xiaoguangrong@tencent.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: add postcopy total blocktime into query-migrateAlexey Perevalov
Postcopy total blocktime is available on destination side only. But query-migrate was possible only for source. This patch adds ability to call query-migrate on destination. To be able to see postcopy blocktime, need to request postcopy-blocktime capability. The query-migrate command will show following sample result: {"return": "postcopy-vcpu-blocktime": [115, 100], "status": "completed", "postcopy-blocktime": 100 }} postcopy_vcpu_blocktime contains list, where the first item is the first vCPU in QEMU. This patch has a drawback, it combines states of incoming and outgoing migration. Ongoing migration state will overwrite incoming state. Looks like better to separate query-migrate for incoming and outgoing migration or add parameter to indicate type of migration. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Alexey Perevalov <a.perevalov@samsung.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <1521742647-25550-7-git-send-email-a.perevalov@samsung.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: add blocktime calculation into migration-testAlexey Perevalov
This patch just requests blocktime calculation, and check it in case when UFFD_FEATURE_THREAD_ID feature is set on the host. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Alexey Perevalov <a.perevalov@samsung.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <1521742647-25550-6-git-send-email-a.perevalov@samsung.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: postcopy_blocktime documentationAlexey Perevalov
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Alexey Perevalov <a.perevalov@samsung.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <1521742647-25550-5-git-send-email-a.perevalov@samsung.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: calculate vCPU blocktime on dst sideAlexey Perevalov
This patch provides blocktime calculation per vCPU, as a summary and as a overlapped value for all vCPUs. This approach was suggested by Peter Xu, as an improvements of previous approch where QEMU kept tree with faulted page address and cpus bitmask in it. Now QEMU is keeping array with faulted page address as value and vCPU as index. It helps to find proper vCPU at UFFD_COPY time. Also it keeps list for blocktime per vCPU (could be traced with page_fault_addr) Blocktime will not calculated if postcopy_blocktime field of MigrationIncomingState wasn't initialized. Signed-off-by: Alexey Perevalov <a.perevalov@samsung.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <1521742647-25550-4-git-send-email-a.perevalov@samsung.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: add postcopy blocktime ctx into MigrationIncomingStateAlexey Perevalov
This patch adds request to kernel space for UFFD_FEATURE_THREAD_ID, in case this feature is provided by kernel. PostcopyBlocktimeContext is encapsulated inside postcopy-ram.c, due to it being a postcopy-only feature. Also it defines PostcopyBlocktimeContext's instance live time. Information from PostcopyBlocktimeContext instance will be provided much after postcopy migration end, instance of PostcopyBlocktimeContext will live till QEMU exit, but part of it (vcpu_addr, page_fault_vcpu_time) used only during calculation, will be released when postcopy ended or failed. To enable postcopy blocktime calculation on destination, need to request proper compatibility (Patch for documentation will be at the tail of the patch set). As an example following command enable that capability, assume QEMU was started with -chardev socket,id=charmonitor,path=/var/lib/migrate-vm-monitor.sock option to control it [root@host]#printf "{\"execute\" : \"qmp_capabilities\"}\r\n \ {\"execute\": \"migrate-set-capabilities\" , \"arguments\": { \"capabilities\": [ { \"capability\": \"postcopy-blocktime\", \"state\": true } ] } }" | nc -U /var/lib/migrate-vm-monitor.sock Or just with HMP (qemu) migrate_set_capability postcopy-blocktime on Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Alexey Perevalov <a.perevalov@samsung.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <1521742647-25550-3-git-send-email-a.perevalov@samsung.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-25migration: introduce postcopy-blocktime capabilityAlexey Perevalov
Right now it could be used on destination side to enable vCPU blocktime calculation for postcopy live migration. vCPU blocktime - it's time since vCPU thread was put into interruptible sleep, till memory page was copied and thread awake. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Alexey Perevalov <a.perevalov@samsung.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <1521742647-25550-2-git-send-email-a.perevalov@samsung.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-04-24Update version for v2.12.0 releasev2.12.0Peter Maydell
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-17Update version for v2.12.0-rc4 releasev2.12.0-rc4Peter Maydell
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-17Revert "mux: fix ctrl-a b again"Peter Maydell
This reverts commit 1b2503fcf7b5932c5a3779ca2ceb92bd403c4ee7. Unfortunately this fix regresses console handling on MIPS Malta; since the mux ctrl-a b bug is not a regression since 2.11, we take the conservative approach and just drop it from 2.12. Reported-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-17fpu: Bound increment for scalbnRichard Henderson
Without bounding the increment, we can overflow exp either here in scalbn_decomposed or when adding the bias in round_canonical. This can result in e.g. underflowing to 0 instead of overflowing to infinity. The old softfloat code did bound the increment. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-17mux: fix ctrl-a b againMarc-André Lureau
Commit fb5e19d2e1472e96d72d5e4d89c20033f8ab345c originally fixed the regression, but was inadvertently broken again in merge commit 2d6752d38d8acda. Fixes: https://bugs.launchpad.net/qemu/+bug/1654137 Cc: qemu-stable@nongnu.org Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 20180416181844.7851-1-marcandre.lureau@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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