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2020-05-14target/microblaze: gdb: Extend the number of registers presented to GDBJoe Komlodi
Increase the number of Microblaze registers QEMU will report when talking to GDB. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <1589393329-223076-2-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2020-05-14target/microblaze: Fix FPU2 instruction checkJoe Komlodi
The check to see if we can use FPU2 instructions would return 0 if cfg.use_fpu == 2, rather than returning the PVR2_USE_FPU2_MASK. This would cause all FPU2 instructions (fsqrt, flt, fint) to not be used. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <1589219346-106769-2-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2020-05-14target/microblaze: Add MFS Rd,EDR translationTong Ho
This is to fix cpu-abort with 'qemu: fatal: unknown mfs reg d' (in the default case) when microblaze guest issues 'MFS Rd,EDR' instruction. Since embeddedsw release 2019.2, XPlm_ExceptionHandler() issues the instruction on exception, and microblaze model aborts when PLM firmware guest encounters an exception. Signed-off-by: Tong Ho <tong.ho@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-Id: <20200512143649.21655-2-edgar.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2020-05-14MAINTAINERS: Add myself as streams maintainerEdgar E. Iglesias
Since we're missing a maintainer, add myself. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200506082513.18751-10-edgar.iglesias@gmail.com>
2020-05-14hw/dma/xilinx_axidma: s2mm: Support stream fragmentsEdgar E. Iglesias
Add support for stream fragments. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20200506082513.18751-9-edgar.iglesias@gmail.com>
2020-05-14hw/dma/xilinx_axidma: mm2s: Stream descriptor by descriptorEdgar E. Iglesias
Stream descriptor by descriptor from memory instead of buffering entire packets before pushing. This enables non-packet streaming clients to work and also lifts the limitation that our internal DMA buffer needs to be able to hold entire packets. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20200506082513.18751-8-edgar.iglesias@gmail.com>
2020-05-14hw/net/xilinx_axienet: Handle fragmented packets from DMAEdgar E. Iglesias
Add support for fragmented packets from the DMA. Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20200506082513.18751-7-edgar.iglesias@gmail.com>
2020-05-14hw/core: stream: Add an end-of-packet flagEdgar E. Iglesias
Some stream clients stream an endless stream of data while other clients stream data in packets. Stream interfaces usually have a way to signal the end of a packet or the last beat of a transfer. This adds an end-of-packet flag to the push interface. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20200506082513.18751-6-edgar.iglesias@gmail.com>
2020-05-14hw/dma/xilinx_axidma: Add DMA memory-region propertyEdgar E. Iglesias
Add DMA memory-region property to externally control what address-space this DMA operates on. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200506082513.18751-5-edgar.iglesias@gmail.com>
2020-05-14hw/net/xilinx_axienet: Remove unncessary castEdgar E. Iglesias
Remove unncessary cast, buf is already uint8_t *. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200506082513.18751-4-edgar.iglesias@gmail.com>
2020-05-14hw/net/xilinx_axienet: Cleanup stream->push assignmentEdgar E. Iglesias
Split the shared stream_class_init function to assign stream->push with better type-safety. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200506082513.18751-3-edgar.iglesias@gmail.com>
2020-05-14hw/net/xilinx_axienet: Auto-clear PHY AutonegEdgar E. Iglesias
Auto-clear PHY CR Autoneg bits. This makes this model work with recent Linux kernels. Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20200506082513.18751-2-edgar.iglesias@gmail.com>
2020-05-14Merge remote-tracking branch 'remotes/gkurz/tags/9p-next-2020-05-14' into ↵Peter Maydell
staging Changes: - Christian Schoenebeck is now co-maintainer for 9pfs - relax checks for O_NOATIME - minor documentation updates # gpg: Signature made Thu 14 May 2020 08:14:37 BST # gpg: using RSA key B4828BAF943140CEF2A3491071D4D5E5822F73D6 # gpg: Good signature from "Greg Kurz <groug@kaod.org>" [full] # gpg: aka "Gregory Kurz <gregory.kurz@free.fr>" [full] # gpg: aka "[jpeg image of size 3330]" [full] # Primary key fingerprint: B482 8BAF 9431 40CE F2A3 4910 71D4 D5E5 822F 73D6 * remotes/gkurz/tags/9p-next-2020-05-14: xen-9pfs: Fix log messages of reply errors 9pfs: local: ignore O_NOATIME if we don't have permissions qemu-options.hx: 9p: clarify -virtfs vs. -fsdev MAINTAINERS: Upgrade myself as 9pfs co-maintainer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-14xen-9pfs: Fix log messages of reply errorsChristian Schoenebeck
If delivery of some 9pfs response fails for some reason, log the error message by mentioning the 9P protocol reply type, not by client's request type. The latter could be misleading that the error occurred already when handling the request input. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> Message-Id: <ad0e5a9b6abde52502aa40b30661d29aebe1590a.1589132512.git.qemu_oss@crudebyte.com> Signed-off-by: Greg Kurz <groug@kaod.org>
2020-05-149pfs: local: ignore O_NOATIME if we don't have permissionsOmar Sandoval
QEMU's local 9pfs server passes through O_NOATIME from the client. If the QEMU process doesn't have permissions to use O_NOATIME (namely, it does not own the file nor have the CAP_FOWNER capability), the open will fail. This causes issues when from the client's point of view, it believes it has permissions to use O_NOATIME (e.g., a process running as root in the virtual machine). Additionally, overlayfs on Linux opens files on the lower layer using O_NOATIME, so in this case a 9pfs mount can't be used as a lower layer for overlayfs (cf. https://github.com/osandov/drgn/blob/dabfe1971951701da13863dbe6d8a1d172ad9650/vmtest/onoatimehack.c and https://github.com/NixOS/nixpkgs/issues/54509). Luckily, O_NOATIME is effectively a hint, and is often ignored by, e.g., network filesystems. open(2) notes that O_NOATIME "may not be effective on all filesystems. One example is NFS, where the server maintains the access time." This means that we can honor it when possible but fall back to ignoring it. Acked-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Signed-off-by: Omar Sandoval <osandov@fb.com> Message-Id: <e9bee604e8df528584693a4ec474ded6295ce8ad.1587149256.git.osandov@fb.com> Signed-off-by: Greg Kurz <groug@kaod.org>
2020-05-14qemu-options.hx: 9p: clarify -virtfs vs. -fsdevChristian Schoenebeck
The docs are ambiguous about the difference (or actually their equality) between options '-virtfs' vs. '-fsdev'. So clarify that '-virtfs' is actually just a convenience shortcut for its generalized form '-fsdev' in conjunction with '-device virtio-9p-pci'. And as we're at it, also be a bit more descriptive what 9pfs is actually used for. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <208f1fceffce2feaf7c900b29e326b967dce7762.1585661532.git.qemu_oss@crudebyte.com> Signed-off-by: Greg Kurz <groug@kaod.org>
2020-05-14MAINTAINERS: Upgrade myself as 9pfs co-maintainerChristian Schoenebeck
As suggested by Greg, let's upgrade myself as co-maintainer of 9pfs. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <E1jEYz4-0004pt-Cs@lizzy.crudebyte.com> Signed-off-by: Greg Kurz <groug@kaod.org>
2020-05-13Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-05-13' ↵Peter Maydell
into staging Block patches: - zstd compression for qcow2 - Fix use-after-free # gpg: Signature made Wed 13 May 2020 15:14:06 BST # gpg: using RSA key 91BEB60A30DB3E8857D11829F407DB0061D5CF40 # gpg: issuer "mreitz@redhat.com" # gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full] # Primary key fingerprint: 91BE B60A 30DB 3E88 57D1 1829 F407 DB00 61D5 CF40 * remotes/maxreitz/tags/pull-block-2020-05-13: block/block-copy: fix use-after-free of task pointer iotests: 287: add qcow2 compression type test qcow2: add zstd cluster compression qcow2: rework the cluster compression routine qcow2: introduce compression type feature Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-13block/block-copy: fix use-after-free of task pointerVladimir Sementsov-Ogievskiy
Obviously, we should g_free the task after trace point and offset update. Reported-by: Coverity (CID 1428756) Fixes: 4ce5dd3e9b5ee0fac18625860eb3727399ee965e Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20200507183800.22626-1-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-05-13iotests: 287: add qcow2 compression type testDenis Plotnikov
The test checks fulfilling qcow2 requirements for the compression type feature and zstd compression type operability. Signed-off-by: Denis Plotnikov <dplotnikov@virtuozzo.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Tested-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20200507082521.29210-5-dplotnikov@virtuozzo.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-05-13qcow2: add zstd cluster compressionDenis Plotnikov
zstd significantly reduces cluster compression time. It provides better compression performance maintaining the same level of the compression ratio in comparison with zlib, which, at the moment, is the only compression method available. The performance test results: Test compresses and decompresses qemu qcow2 image with just installed rhel-7.6 guest. Image cluster size: 64K. Image on disk size: 2.2G The test was conducted with brd disk to reduce the influence of disk subsystem to the test results. The results is given in seconds. compress cmd: time ./qemu-img convert -O qcow2 -c -o compression_type=[zlib|zstd] src.img [zlib|zstd]_compressed.img decompress cmd time ./qemu-img convert -O qcow2 [zlib|zstd]_compressed.img uncompressed.img compression decompression zlib zstd zlib zstd ------------------------------------------------------------ real 65.5 16.3 (-75 %) 1.9 1.6 (-16 %) user 65.0 15.8 5.3 2.5 sys 3.3 0.2 2.0 2.0 Both ZLIB and ZSTD gave the same compression ratio: 1.57 compressed image size in both cases: 1.4G Signed-off-by: Denis Plotnikov <dplotnikov@virtuozzo.com> QAPI part: Acked-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200507082521.29210-4-dplotnikov@virtuozzo.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-05-13qcow2: rework the cluster compression routineDenis Plotnikov
The patch enables processing the image compression type defined for the image and chooses an appropriate method for image clusters (de)compression. Signed-off-by: Denis Plotnikov <dplotnikov@virtuozzo.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20200507082521.29210-3-dplotnikov@virtuozzo.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-05-13qcow2: introduce compression type featureDenis Plotnikov
The patch adds some preparation parts for incompatible compression type feature to qcow2 allowing the use different compression methods for image clusters (de)compressing. It is implied that the compression type is set on the image creation and can be changed only later by image conversion, thus compression type defines the only compression algorithm used for the image, and thus, for all image clusters. The goal of the feature is to add support of other compression methods to qcow2. For example, ZSTD which is more effective on compression than ZLIB. The default compression is ZLIB. Images created with ZLIB compression type are backward compatible with older qemu versions. Adding of the compression type breaks a number of tests because now the compression type is reported on image creation and there are some changes in the qcow2 header in size and offsets. The tests are fixed in the following ways: * filter out compression_type for many tests * fix header size, feature table size and backing file offset affected tests: 031, 036, 061, 080 header_size +=8: 1 byte compression type 7 bytes padding feature_table += 48: incompatible feature compression type backing_file_offset += 56 (8 + 48 -> header_change + feature_table_change) * add "compression type" for test output matching when it isn't filtered affected tests: 049, 060, 061, 065, 082, 085, 144, 182, 185, 198, 206, 242, 255, 274, 280 Signed-off-by: Denis Plotnikov <dplotnikov@virtuozzo.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> QAPI part: Acked-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200507082521.29210-2-dplotnikov@virtuozzo.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2020-05-12Merge remote-tracking branch ↵Peter Maydell
'remotes/stefanberger/tags/pull-tpm-2020-05-08-1' into staging Merge tpm 2020/05/08 v3 # gpg: Signature made Tue 12 May 2020 16:50:34 BST # gpg: using RSA key B818B9CADF9089C2D5CEC66B75AD65802A0B4211 # gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211 * remotes/stefanberger/tags/pull-tpm-2020-05-08-1: hw/tpm: fix usage of bool in tpm-tis.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-12hw/tpm: fix usage of bool in tpm-tis.cJafar Abdi
Clean up wrong usage of FALSE and TRUE in places that use "bool" from stdbool.h. FALSE and TRUE (with capital letters) are the constants defined by glib for being used with the "gboolean" type of glib. But some parts of the code also use TRUE and FALSE for variables that are declared as "bool" (the type from <stdbool.h>). Signed-off-by: Jafar Abdi <cafer.abdi@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2020-05-11Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200511' into staging target-arm queue: aspeed: Add boot stub for smp booting target/arm: Drop access_el3_aa32ns_aa64any() aspeed: Support AST2600A1 silicon revision aspeed: sdmc: Implement AST2600 locking behaviour nrf51: Tracing cleanups target/arm: Improve handling of SVE loads and stores target/arm: Don't show TCG-only CPUs in KVM-only QEMU builds hw/arm/musicpal: Map the UART devices unconditionally target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA # gpg: Signature made Mon 11 May 2020 14:33:14 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200511: (34 commits) target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA hw/arm/musicpal: Map the UART devices unconditionally target/arm: Restrict TCG cpus to TCG accel target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[] target/arm: Make set_feature() available for other files target/arm/kvm: Inline set_feature() calls target/arm: Remove sve_memopidx target/arm: Reuse sve_probe_page for gather loads target/arm: Reuse sve_probe_page for scatter stores target/arm: Reuse sve_probe_page for gather first-fault loads target/arm: Use SVEContLdSt for contiguous stores target/arm: Update contiguous first-fault and no-fault loads target/arm: Use SVEContLdSt for multi-register contiguous loads target/arm: Handle watchpoints in sve_ld1_r target/arm: Use SVEContLdSt in sve_ld1_r target/arm: Adjust interface of sve_ld1_host_fn target/arm: Add sve infrastructure for page lookup target/arm: Drop manual handling of set/clear_helper_retaddr ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)Richard Henderson
DUP (indexed) can duplicate 128-bit elements, so using esz unconditionally can assert in tcg_gen_gvec_dup_imm. Fixes: 8711e71f9cbb Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20200507172352.15418-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLARichard Henderson
Now that we can pass 7 parameters, do not encode register operands within simd_data. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200507172352.15418-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11hw/arm/musicpal: Map the UART devices unconditionallyPhilippe Mathieu-Daudé
I can't find proper documentation or datasheet, but it is likely a MMIO mapped serial device mapped in the 0x80000000..0x8000ffff range belongs to the SoC address space, thus is always mapped in the memory bus. Map the devices on the bus regardless a chardev is attached to it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jan Kiszka <jan.kiszka@web.de> Message-id: 20200505095945.23146-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Restrict TCG cpus to TCG accelPhilippe Mathieu-Daudé
A KVM-only build won't be able to run TCG cpus. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200504172448.9402-6-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUsPhilippe Mathieu-Daudé
As IDAU is a v8M feature, restrict it to the Aarch32 CPUs. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200504172448.9402-5-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]Philippe Mathieu-Daudé
Use ARRAY_SIZE() to iterate over ARMCPUInfo[]. Since on the aarch64-linux-user build, arm_cpus[] is empty, add the cpu_count variable and only iterate when it is non-zero. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200504172448.9402-4-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Make set_feature() available for other filesThomas Huth
Move the common set_feature() and unset_feature() functions from cpu.c and cpu64.c to cpu.h. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200504172448.9402-3-philmd@redhat.com Message-ID: <20190921150420.30743-2-thuth@redhat.com> [PMD: Split Thomas's patch in two: set_feature, cpu_register] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm/kvm: Inline set_feature() callsPhilippe Mathieu-Daudé
We want to move the inlined declarations of set_feature() from cpu*.c to cpu.h. To avoid clashing with the KVM declarations, inline the few KVM calls. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200504172448.9402-2-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Remove sve_memopidxRichard Henderson
None of the sve helpers use TCGMemOpIdx any longer, so we can stop passing it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Reuse sve_probe_page for gather loadsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Reuse sve_probe_page for scatter storesRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Reuse sve_probe_page for gather first-fault loadsRichard Henderson
This avoids the need for a separate set of helpers to implement no-fault semantics, and will enable MTE in the future. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Use SVEContLdSt for contiguous storesRichard Henderson
Follow the model set up for contiguous loads. This handles watchpoints correctly for contiguous stores, recognizing the exception before any changes to memory. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Update contiguous first-fault and no-fault loadsRichard Henderson
With sve_cont_ldst_pages, the differences between first-fault and no-fault are minimal, so unify the routines. With cpu_probe_watchpoint, we are able to make progress through pages with TLB_WATCHPOINT set when the watchpoint does not actually fire. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Use SVEContLdSt for multi-register contiguous loadsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Handle watchpoints in sve_ld1_rRichard Henderson
Handle all of the watchpoints for active elements all at once, before we've modified the vector register. This removes the TLB_WATCHPOINT bit from page[].flags, which means that we can use the normal fast path via RAM. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Use SVEContLdSt in sve_ld1_rRichard Henderson
First use of the new helper functions, so we can remove the unused markup. No longer need a scratch for user-only, as we completely probe the page set before reading; system mode still requires a scratch for MMIO. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Adjust interface of sve_ld1_host_fnRichard Henderson
The current interface includes a loop; change it to load a single element. We will then be able to use the function for ld{2,3,4} where individual vector elements are not adjacent. Replace each call with the simplest possible loop over active elements. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Add sve infrastructure for page lookupRichard Henderson
For contiguous predicated memory operations, we want to minimize the number of tlb lookups performed. We have open-coded this for sve_ld1_r, but for correctness with MTE we will need this for all of the memory operations. Create a structure that holds the bounds of active elements, and metadata for two pages. Add routines to find those active elements, lookup the pages, and run watchpoints for those pages. Temporarily mark the functions unused to avoid Werror. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Drop manual handling of set/clear_helper_retaddrRichard Henderson
Since we converted back to cpu_*_data_ra, we do not need to do this ourselves. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fnRichard Henderson
Use the "normal" memory access functions, rather than the softmmu internal helper functions directly. Since fb901c905dc3, cpu_mem_index is now a simple extract from env->hflags and not a large computation. Which means that it's now more work to pass around this value than it is to recompute it. This only adjusts the primitives, and does not clean up all of the uses within sve_helper.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11accel/tcg: Add endian-specific cpu_{ld, st}* operationsRichard Henderson
We currently have target-endian versions of these operations, but no easy way to force a specific endianness. This can be helpful if the target has endian-specific operations, or a mode that swaps endianness. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11accel/tcg: Add probe_access_flagsRichard Henderson
This new interface will allow targets to probe for a page and then handle watchpoints themselves. This will be most useful for vector predicated memory operations, where one page lookup can be used for many operations, and one test can avoid many watchpoint checks. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11accel/tcg: Adjust probe_access call to page_check_rangeRichard Henderson
We have validated that addr+size does not cross a page boundary. Therefore we need to validate exactly one page. We can achieve that passing any value 1 <= x <= size to page_check_range. Passing 1 will simplify the next patch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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