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QEMU is a generic and open source machine & userspace emulator and virtualizer
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Author
2019-09-20
ipmi: Add an SMBus IPMI interface
Corey Minyard
2019-09-20
ipmi: Add PCI IPMI interfaces
Corey Minyard
2019-09-20
smbios:ipmi: Ignore IPMI devices with no fwinfo function
Corey Minyard
2019-09-20
ipmi: Allow a size value to be passed for I/O space
Corey Minyard
2019-09-20
ipmi: Split out BT-specific code from ISA BT code
Corey Minyard
2019-09-20
ipmi: Split out KCS-specific code from ISA KCS code
Corey Minyard
2019-09-20
ipmi: Add a UUID device property
Corey Minyard
2019-09-20
qdev: Add a no default uuid property
Corey Minyard
2019-09-20
tests:ipmi: Fix IPMI BT tests
Corey Minyard
2019-09-20
ipmi: Generate an interrupt on watchdog pretimeout expiry
Corey Minyard
2019-09-20
ipmi: Fix the get watchdog command
Corey Minyard
2019-09-20
ipmi: Fix watchdog NMI handling
Corey Minyard
2019-09-19
Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190919-pull-request' i...
Peter Maydell
2019-09-19
Merge remote-tracking branch 'remotes/kraxel/tags/ati-20190919-pull-request' ...
Peter Maydell
2019-09-19
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' int...
Peter Maydell
2019-09-19
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-sf1-v3...
Peter Maydell
2019-09-19
ati: use vga_read_byte in ati_cursor_define
Gerd Hoffmann
2019-09-19
vga: move access helpers to separate include file
Gerd Hoffmann
2019-09-18
trace: Forbid event format ending with newline character
Philippe Mathieu-Daudé
2019-09-18
trace: Remove trailing newline in events
Philippe Mathieu-Daudé
2019-09-18
loader: Trace loaded images
Alexey Kardashevskiy
2019-09-17
gdbstub: riscv: fix the fflags registers
KONRAD Frederic
2019-09-17
target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
Alistair Francis
2019-09-17
target/riscv: Fix mstatus dirty mask
Alistair Francis
2019-09-17
target/riscv: Use both register name and ABI name
Atish Patra
2019-09-17
riscv: sifive_u: Update model and compatible strings in device tree
Bin Meng
2019-09-17
riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
Bin Meng
2019-09-17
riscv: sifive_u: Fix broken GEM support
Bin Meng
2019-09-17
riscv: sifive_u: Instantiate OTP memory with a serial number
Bin Meng
2019-09-17
riscv: sifive: Implement a model for SiFive FU540 OTP
Bin Meng
2019-09-17
riscv: roms: Update default bios for sifive_u machine
Bin Meng
2019-09-17
riscv: sifive_u: Change UART node name in device tree
Bin Meng
2019-09-17
riscv: sifive_u: Update UART base addresses and IRQs
Bin Meng
2019-09-17
riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
Bin Meng
2019-09-17
riscv: sifive_u: Add PRCI block to the SoC
Bin Meng
2019-09-17
riscv: sifive_u: Generate hfclk and rtcclk nodes
Bin Meng
2019-09-17
riscv: sifive: Implement PRCI model for FU540
Bin Meng
2019-09-17
riscv: sifive_u: Update PLIC hart topology configuration string
Bin Meng
2019-09-17
riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
Bin Meng
2019-09-17
riscv: sifive_u: Set the minimum number of cpus to 2
Bin Meng
2019-09-17
riscv: hart: Add a "hartid-base" property to RISC-V hart array
Bin Meng
2019-09-17
riscv: hart: Extract hart realize to a separate routine
Bin Meng
2019-09-17
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
Bin Meng
2019-09-17
riscv: sifive_e: Drop sifive_mmio_emulate()
Bin Meng
2019-09-17
riscv: sifive_e: prci: Update the PRCI register block size
Bin Meng
2019-09-17
riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
Bin Meng
2019-09-17
riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
Bin Meng
2019-09-17
riscv: sifive_u: Remove the unnecessary include of prci header
Bin Meng
2019-09-17
riscv: roms: Remove executable attribute of opensbi images
Bin Meng
2019-09-17
riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
Bin Meng
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