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2019-02-18qapi: make query-cpu-model-expansion depend on s390 or x86Marc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-14-armbru@redhat.com>
2019-02-18qapi: make query-gic-capabilities depend on TARGET_ARMMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-13-armbru@redhat.com>
2019-02-18target.json: add a note about query-cpu* not being s390x-specificMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-12-armbru@redhat.com>
2019-02-18qapi: make s390 commands depend on TARGET_S390XMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-11-armbru@redhat.com>
2019-02-18qapi: make rtc-reset-reinjection and SEV depend on TARGET_I386Marc-André Lureau
Move rtc-reset-reinjection and SEV in target.json and make them conditional on TARGET_I386. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-10-armbru@redhat.com>
2019-02-18qapi: New module target.jsonMarkus Armbruster
We can't add appropriate target-specific conditionals to misc.json, because that would make all of misc.json unusable in target-independent code. To keep misc.json target-independent, we need to split off target-dependent target.json. This commit doesn't actually split off anything, it merely creates the empty module. The next few patches will move stuff from misc.json there. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20190214152251.2073-9-armbru@redhat.com>
2019-02-18build: Deal with all of QAPI's .o in qapi/Makefile.objsMarkus Armbruster
Adding QAPI's .o to util-obj-y, common-obj-y and obj-y is spread over three places: Makefile.objs takes care of target-independent generated code, Makefile.target of target-dependent generated code, and qapi/Makefile.objs of (target-independent) hand-written code. Do everything in qapi/Makefile.objs. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20190214152251.2073-8-armbru@redhat.com>
2019-02-18build-sys: move qmp-introspect per targetMarc-André Lureau
The following patches are going to introduce per-target #ifdef in the schemas. The introspection data is statically generated once, and must thus be built per-target to reflect target-specific configuration. Drop "do_test_visitor_in_qmp_introspect(&qmp_schema_qlit)" since the schema is no longer in a common object. It is covered by the per-target query-qmp-schema test instead. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-7-armbru@redhat.com>
2019-02-18qapi: Generate QAPIEvent stuff into separate filesMarkus Armbruster
Having to include qapi-events.h just for QAPIEvent is suboptimal, but quite tolerable now. It'll become problematic when we have events conditional on the target, because then qapi-events.h won't be usable from target-independent code anymore. Avoid that by generating it into separate files. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20190214152251.2073-6-armbru@redhat.com>
2019-02-18qapi: Prepare for system modules other than 'builtin'Markus Armbruster
The next commit wants to generate qapi-emit-events.{c.h}. To enable that, extend QAPISchemaModularCVisitor to support additional "system modules", i.e. modules that don't correspond to a (user-defined) QAPI schema module. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20190214152251.2073-5-armbru@redhat.com>
2019-02-18qapi: Clean up modular built-in code generation a bitMarkus Armbruster
We neglect to call .visit_module() for the special module we use for built-ins. Harmless, but clean it up anyway. The tests/qapi-schema/*.out now show the built-in module as 'module None'. Subclasses of QAPISchemaModularCVisitor need to ._add_module() this special module to enable code generation for built-ins. When this hasn't been done, QAPISchemaModularCVisitor.visit_module() does nothing for the special module. That looks like built-ins could accidentally be generated into the wrong module when a subclass neglects to call ._add_module(). Can't happen, because built-ins are all visited before any other module. But that's non-obvious. Switch off code generation explicitly. Rename QAPISchemaModularCVisitor._begin_module() to ._begin_user_module(). New QAPISchemaModularCVisitor._is_builtin_module(), for clarity. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20190214152251.2073-4-armbru@redhat.com>
2019-02-18qapi: Fix up documentation for recent commit a95291007b2Markus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20190214152251.2073-3-armbru@redhat.com>
2019-02-18qapi: Belatedly document modular code generationMarkus Armbruster
We generate code for built-ins and sub-modules into separate files since commit cdb6610ae42 and 252dc3105fc (v2.12.0). Both commits neglected to update documentation. Do that now. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20190214152251.2073-2-armbru@redhat.com>
2019-02-15Merge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-20190215' ↵Peter Maydell
into staging qemu-openbios queue # gpg: Signature made Fri 15 Feb 2019 10:31:11 GMT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-openbios-20190215: Update OpenBIOS images to 3464681b built from submodule. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20190215' into staging target-arm queue: * gdbstub: Send a reply to the vKill packet * Improve codegen for neon min/max and saturating arithmetic * Fix a bug in clearing FPSCR exception status bits * hw/arm/armsse: Fix miswiring of expansion IRQs * hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 * MAINTAINERS: Remove Peter Crosthwaite from various entries * arm: Allow system registers for KVM guests to be changed by QEMU code * linux-user: support HWCAP_CPUID which exposes ID registers to user code * Fix bug in 128-bit cmpxchg for BE Arm guests * Implement (no-op) HACR_EL2 * Fix CRn to be 14 for PMEVTYPER/PMEVCNTR # gpg: Signature made Fri 15 Feb 2019 10:19:14 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190215: (25 commits) gdbstub: Send a reply to the vKill packet. target/arm: Add missing clear_tail calls target/arm: Use vector operations for saturation target/arm: Split out FPSCR.QC to a vector field target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] target/arm: Split out flags setting from vfp compares target/arm: Fix arm_cpu_dump_state vs FPSCR target/arm: Fix vfp_gdb_get/set_reg vs FPSCR target/arm: Remove neon min/max helpers target/arm: Use tcg integer min/max primitives for neon target/arm: Use vector minmax expanders for aarch32 target/arm: Use vector minmax expanders for aarch64 target/arm: Rely on optimization within tcg_gen_gvec_or hw/arm/armsse: Fix miswiring of expansion IRQs hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 MAINTAINERS: Remove Peter Crosthwaite from various entries arm: Allow system registers for KVM guests to be changed by QEMU code linux-user/elfload: enable HWCAP_CPUID for AArch64 target/arm: expose remaining CPUID registers as RAZ target/arm: expose MPIDR_EL1 to userspace ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15Update OpenBIOS images to 3464681b built from submodule.Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2019-02-15gdbstub: Send a reply to the vKill packet.Sandra Loosemore
Per the GDB remote protocol documentation https://sourceware.org/gdb/current/onlinedocs/gdb/Packets.html#index-vKill-packet the debug stub is expected to send a reply to the 'vKill' packet. At least some versions of GDB crash if the gdb stub simply exits without sending a reply. This patch fixes QEMU's gdb stub to conform to the expected behavior. Note that QEMU's existing handling of the legacy 'k' packet is correct: in that case GDB does not expect a reply, and QEMU does not send one. Signed-off-by: Sandra Loosemore <sandra@codesourcery.com> Message-id: 1550008033-26540-1-git-send-email-sandra@codesourcery.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Add missing clear_tail callsRichard Henderson
Fortunately, the functions affected are so far only called from SVE, so there is no tail to be cleared. But as we convert more of AdvSIMD to gvec, this will matter. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-13-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Use vector operations for saturationRichard Henderson
For same-sign saturation, we have tcg vector operations. We can compute the QC bit by comparing the saturated value against the unsaturated value. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-12-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Split out FPSCR.QC to a vector fieldRichard Henderson
Change the representation of this field such that it is easy to set from vector code. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-11-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]Richard Henderson
Given that we mask bits properly on set, there is no reason to mask them again on get. We failed to clear the exception status bits, 0x9f, which means that the wrong value would be returned on get. Except in the (probably normal) case in which the set clears all of the bits. Simplify the code in set to also clear the RES0 bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Split out flags setting from vfp comparesRichard Henderson
Minimize the code within a macro by splitting out a helper function. Use deposit32 instead of manual bit manipulation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Fix arm_cpu_dump_state vs FPSCRRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Fix vfp_gdb_get/set_reg vs FPSCRRichard Henderson
The components of this register is stored in several different locations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Remove neon min/max helpersRichard Henderson
These are now unused. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Use tcg integer min/max primitives for neonRichard Henderson
The 32-bit PMIN/PMAX has been decomposed to scalars, and so can be trivially expanded inline. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Use vector minmax expanders for aarch32Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Use vector minmax expanders for aarch64Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Rely on optimization within tcg_gen_gvec_orRichard Henderson
Since we're now handling a == b generically, we no longer need to do it by hand within target/arm/. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15hw/arm/armsse: Fix miswiring of expansion IRQsPeter Maydell
In commit 91c1e9fcbd7548db368 where we added dual-CPU support to the ARMSSE, we set up the wiring of the expansion IRQs via nested loops: the outer loop on 'i' loops for each CPU, and the inner loop on 'j' loops for each interrupt. Fix a typo which meant we were wiring every expansion IRQ line to external IRQ 0 on CPU 0 and to external IRQ 1 on CPU 1. Fixes: 91c1e9fcbd7548db368 ("hw/arm/armsse: Support dual-CPU configuration") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-02-15hw/intc/armv7m_nvic: Allow byte accesses to SHPR1Peter Maydell
The code for handling the NVIC SHPR1 register intends to permit byte and halfword accesses (as the architecture requires). However the 'case' line for it only lists the base address of the register, so attempts to access bytes other than the first one end up in the "bad write" default logic. This bug was added accidentally when we split out the SHPR1 logic from SHPR2 and SHPR3 to support v6M. Fixes: 7c9140afd594 ("nvic: Handle ARMv6-M SCS reserved registers") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> --- The Zephyr RTOS happens to access SHPR1 byte at a time, which is how I spotted this.
2019-02-15MAINTAINERS: Remove Peter Crosthwaite from various entriesPeter Maydell
Peter Crosthwaite hasn't had the bandwidth to do code review or other QEMU work for some time now -- remove his email address from MAINTAINERS file entries so we don't bombard him with patch emails. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190207181422.4907-1-peter.maydell@linaro.org
2019-02-15arm: Allow system registers for KVM guests to be changed by QEMU codePeter Maydell
At the moment the Arm implementations of kvm_arch_{get,put}_registers() don't support having QEMU change the values of system registers (aka coprocessor registers for AArch32). This is because although kvm_arch_get_registers() calls write_list_to_cpustate() to update the CPU state struct fields (so QEMU code can read the values in the usual way), kvm_arch_put_registers() does not call write_cpustate_to_list(), meaning that any changes to the CPU state struct fields will not be passed back to KVM. The rationale for this design is documented in a comment in the AArch32 kvm_arch_put_registers() -- writing the values in the cpregs list into the CPU state struct is "lossy" because the write of a register might not succeed, and so if we blindly copy the CPU state values back again we will incorrectly change register values for the guest. The assumption was that no QEMU code would need to write to the registers. However, when we implemented debug support for KVM guests, we broke that assumption: the code to handle "set the guest up to take a breakpoint exception" does so by updating various guest registers including ESR_EL1. Support this by making kvm_arch_put_registers() synchronize CPU state back into the list. We sync only those registers where the initial write succeeds, which should be sufficient. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Dongjiu Geng <gengdongjiu@huawei.com>
2019-02-15linux-user/elfload: enable HWCAP_CPUID for AArch64Alex Bennée
Userspace programs should (in theory) query the ELF HWCAP before probing these registers. Now we have implemented them all make it public. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190205190224.2198-6-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: expose remaining CPUID registers as RAZAlex Bennée
There are a whole bunch more registers in the CPUID space which are currently not used but are exposed as RAZ. To avoid too much duplication we expand ARMCPRegUserSpaceInfo to understand glob patterns so we only need one entry to tweak whole ranges of registers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190205190224.2198-5-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: expose MPIDR_EL1 to userspaceAlex Bennée
As this is a single register we could expose it with a simple ifdef but we use the existing modify_arm_cp_regs mechanism for consistency. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190205190224.2198-4-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: expose CPUID registers to userspaceAlex Bennée
A number of CPUID registers are exposed to userspace by modern Linux kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's user-mode emulation we don't need to emulate the kernels trap but just return the value the trap would have done. To avoid too much #ifdef hackery we process ARMCPRegInfo with a new helper (modify_arm_cp_regs) before defining the registers. The modify routine is driven by a simple data structure which describes which bits are exported and which are fixed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190205190224.2198-3-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: relax permission checks for HWCAP_CPUID registersAlex Bennée
Although technically not visible to userspace the kernel does make them visible via a trap and emulate ABI. We provide a new permission mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust the minimum permission check accordingly. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190205190224.2198-2-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_beCatherine Ho
The lo,hi order is different from the comments. And in commit 1ec182c33379 ("target/arm: Convert to HAVE_CMPXCHG128"), it changes the original code logic. So just restore the old code logic before this commit: do_paired_cmpxchg64_be(): cmpv = int128_make128(env->exclusive_high, env->exclusive_val); newv = int128_make128(new_hi, new_lo); This fixes a bug that would only be visible for big-endian AArch64 guest code. Fixes: 1ec182c33379 ("target/arm: Convert to HAVE_CMPXCHG128") Signed-off-by: Catherine Ho <catherine.hecx@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1548985244-24523-1-git-send-email-catherine.hecx@gmail.com [PMM: added note that bug only affects BE guests] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Implement HACR_EL2Peter Maydell
HACR_EL2 is a register with IMPDEF behaviour, which allows implementation specific trapping to EL2. Implement it as RAZ/WI, since QEMU's implementation has no extra traps. This also matches what h/w implementations like Cortex-A53 and A57 do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190205181218.8995-1-peter.maydell@linaro.org
2019-02-15target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTRAaron Lindsay OS
This bug was introduced in: commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59 target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190205135129.19338-1-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-14Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-14-2019' ↵Peter Maydell
into staging MIPS queue for February 14th, 2019 # gpg: Signature made Thu 14 Feb 2019 16:48:39 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-feb-14-2019: tests/tcg: target/mips: Add tests for MSA logic instructions tests/tcg: target/mips: Add wrappers for MSA logic instructions tests/tcg: target/mips: Add tests for MSA interleave instructions tests/tcg: target/mips: Add wrappers for MSA interleave instructions tests/tcg: target/mips: Add tests for MSA bit counting instructions tests/tcg: target/mips: Add wrappers for MSA bit counting instructions tests/tcg: target/mips: Add a header with test utilities tests/tcg: target/mips: Add a header with test inputs tests/tcg: target/mips: Remove an unnecessary file target/mips: introduce MTTCG-enabled builds hw/mips_cpc: kick a VP when putting it into Run statewq target/mips: hold BQL in mips_vpe_wake() hw/mips_int: hold BQL for all interrupt requests target/mips: reimplement SC instruction emulation and use cmpxchg target/mips: compare virtual addresses in LL/SC sequence Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-14Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-pull-request' into staging - some configure updates (HAX/NetBSD, remove "wav", -Waddress-of-packed-member) - remove deprecated options - some trace and error cleanup - typo fixes # gpg: Signature made Thu 14 Feb 2019 10:46:50 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-pull-request: configure: improve usbfs check hw/sparc64: Explicitly set default_display = "std" hw/dma/i8257: Use qemu_log_mask(UNIMP) instead of fprintf wavcapture: Convert to error_report kvm: Add kvm_set_ioeventfd* traces HMP: Prepend errors with 'Error:' pckbd: Convert DPRINTF->trace configure: Make -Waddress-of-packed-member warnings be errors configure: Add HAX support in NetBSD configure: fix qemu-img name configure: remove handling of "wav" audio driver qemu-options: Remove deprecated option -clock qemu-deprecated: Remove -virtioconsole and -no-frame for good qapi: Fix qcow2 encryption doc typo Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-14tests/tcg: target/mips: Add tests for MSA logic instructionsAleksandar Markovic
Add tests for MSA logic instructions. This includes following instructions: * AND.V - logical AND * NOR.V - logical NOR * OR.V - logical OR * XOR.V - logical XOR Each test consists of 80 test cases, so altogether there are 320 test cases. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14tests/tcg: target/mips: Add wrappers for MSA logic instructionsAleksandar Markovic
Add wrappers for MSA logic instructions. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14tests/tcg: target/mips: Add tests for MSA interleave instructionsAleksandar Markovic
Add tests for MSA interleave instructions. This includes following instructions: * ILVEV.B - interleave even (bytes) * ILVEV.H - interleave even (halfwords) * ILVEV.W - interleave even (words) * ILVEV.D - interleave even (doublewords) * ILVOD.B - interleave odd (bytes) * ILVOD.H - interleave odd (halfwords) * ILVOD.W - interleave odd (words) * ILVOD.D - interleave odd (doublewords) * ILVL.B - interleave left (bytes) * ILVL.H - interleave left (halfwords) * ILVL.W - interleave left (words) * ILVL.D - interleave left (doublewords) * ILVR.B - interleave right (bytes) * ILVR.H - interleave right (halfwords) * ILVR.W - interleave right (words) * ILVR.D - interleave right (doublewords) Each test consists of 80 test cases, so altogether there are 1280 test cases. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14tests/tcg: target/mips: Add wrappers for MSA interleave instructionsAleksandar Markovic
Add wrappers for MSA interleave instructions. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14tests/tcg: target/mips: Add tests for MSA bit counting instructionsAleksandar Markovic
Add tests for MSA bit counting instructions. This includes following instructions: * NLOC.B - number of leading ones (bytes) * NLOC.H - number of leading ones (halfwords) * NLOC.W - number of leading ones (words) * NLOC.D - number of leading ones (doublewords) * NLZC.B - number of leading zeros (bytes) * NLZC.H - number of leading zeros (halfwords) * NLZC.W - number of leading zeros (words) * NLZC.D - number of leading zeros (doublewords) * PCNT.B - population count / number of ones (bytes) * PCNT.H - population count / number of ones (halfwords) * PCNT.W - population count / number of ones (words) * PCNT.D - population count / number of ones (doublewords) Each test consists of 80 test cases, so altogether there are 960 test cases. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14tests/tcg: target/mips: Add wrappers for MSA bit counting instructionsAleksandar Markovic
Add a header that contains wrappers around MSA instructions assembler invocations. For now, only bit counting instructions (NLOC, NLZC, and PCNT; each in four data format flavors) are supported. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14tests/tcg: target/mips: Add a header with test utilitiesAleksandar Markovic
Add a header that contains test utilities. For now, it contains only a function for checking and printing test results for bit counting and similar MSA instructions. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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