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AgeCommit message (Expand)Author
2020-10-17build: replace ninjatool with ninjaPaolo Bonzini
2020-10-17build: cleanups to MakefilePaolo Bonzini
2020-10-17add ninja to dockerfiles, CI configurations and test VMsPaolo Bonzini
2020-10-17dockerfiles: enable Centos 8 PowerToolsPaolo Bonzini
2020-10-17configure: move QEMU_INCLUDES to mesonPaolo Bonzini
2020-10-17tests: add missing generated sources to testqapiPaolo Bonzini
2020-10-17make: run shell with pipefailPaolo Bonzini
2020-10-17tests/Makefile.include: unbreak non-tcg buildsPaolo Bonzini
2020-10-17Makefile: Ensure cscope.out/tags/TAGS are generated in the source treeGreg Kurz
2020-10-17submodules: bump meson to 0.55.3Paolo Bonzini
2020-10-17target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)Philippe Mathieu-Daudé
2020-10-17MAINTAINERS: Remove duplicated Malta test entriesPhilippe Mathieu-Daudé
2020-10-17MAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton mailPhilippe Mathieu-Daudé
2020-10-17MAINTAINERS: Put myself forward for MIPS targetPhilippe Mathieu-Daudé
2020-10-17MAINTAINERS: Remove myselfAleksandar Markovic
2020-10-17docs/system: Update MIPS CPU documentationHuacai Chen
2020-10-17tests/acceptance: Add MIPS record/replay testsPavel Dovgalyuk
2020-10-17hw/mips: Remove exit(1) in case of missing ROMPavel Dovgalyuk
2020-10-17hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTONEduardo Habkost
2020-10-17hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)Philippe Mathieu-Daudé
2020-10-17hw/mips: Simplify loading 64-bit ELF kernelsPhilippe Mathieu-Daudé
2020-10-17hw/mips/malta: Use clearer qdev stylePhilippe Mathieu-Daudé
2020-10-17hw/mips/malta: Move gt64120 related code togetherPhilippe Mathieu-Daudé
2020-10-17hw/mips/malta: Fix FPGA I/O region sizePhilippe Mathieu-Daudé
2020-10-17target/mips/cpu: Display warning when CPU is used without input clockPhilippe Mathieu-Daudé
2020-10-17hw/mips/cps: Do not allow use without input clockPhilippe Mathieu-Daudé
2020-10-17hw/mips/malta: Set CPU frequency to 320 MHzPhilippe Mathieu-Daudé
2020-10-17hw/mips/boston: Set CPU frequency to 1 GHzPhilippe Mathieu-Daudé
2020-10-17hw/mips/cps: Expose input clock and connect it to CPU coresPhilippe Mathieu-Daudé
2020-10-17hw/mips/jazz: Correct CPU frequenciesPhilippe Mathieu-Daudé
2020-10-17hw/mips/mipssim: Correct CPU frequencyPhilippe Mathieu-Daudé
2020-10-17hw/mips/fuloong2e: Set CPU frequency to 533 MHzPhilippe Mathieu-Daudé
2020-10-17hw/mips/r4k: Explicit CPU frequency is 200 MHzPhilippe Mathieu-Daudé
2020-10-17target/mips/cpu: Introduce mips_cpu_create_with_clock() helperPhilippe Mathieu-Daudé
2020-10-17target/mips/cpu: Allow the CPU to use dynamic frequenciesPhilippe Mathieu-Daudé
2020-10-17target/mips/cpu: Make cp0_count_rate a propertyPhilippe Mathieu-Daudé
2020-10-17target/mips/cpu: Calculate the CP0 timer period using the CPU frequencyPhilippe Mathieu-Daudé
2020-10-17target/mips: Move cp0_count_ns to CPUMIPSStatePhilippe Mathieu-Daudé
2020-10-17target/mips/cp0_timer: Document TIMER_PERIOD originPhilippe Mathieu-Daudé
2020-10-17target/mips/cp0_timer: Explicit unit in variable namePhilippe Mathieu-Daudé
2020-10-17target/mips: Move cpu_mips_get_random() with CP0 helpersPhilippe Mathieu-Daudé
2020-10-17target/mips/op_helper: Log unimplemented cache opcodePhilippe Mathieu-Daudé
2020-10-17target/mips/op_helper: Document Invalidate/Writeback opcodes as no-opPhilippe Mathieu-Daudé
2020-10-17target/mips/op_helper: Convert multiple if() to switch casePhilippe Mathieu-Daudé
2020-10-17target/mips: Add loongson-ext lsdc2 group of instructionsJiaxun Yang
2020-10-17target/mips: Add loongson-ext lswc2 group of instructions (Part 2)Jiaxun Yang
2020-10-17target/mips: Add loongson-ext lswc2 group of instructions (Part 1)Jiaxun Yang
2020-10-17target/mips: Demacro helpers for <MAX|MAXA|MIN|MINA>.<D|S>Aleksandar Markovic
2020-10-17target/mips: Demacro helpers for M<ADD|SUB>F.<D|S>Aleksandar Markovic
2020-10-17target/mips: Demacro helpers for <ABS|CHS>.<D|S|PS>Aleksandar Markovic