slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2020-06-22	hw/rx: Honor -accel qtest	Richard Henderson
2020-06-22	hw/rx: RX62N microcontroller (MCU)	Yoshinori Sato
2020-06-22	hw/char: RX62N serial communication interface (SCI)	Yoshinori Sato
2020-06-22	hw/timer: RX62N compare match timer (CMT)	Yoshinori Sato
2020-06-22	hw/timer: RX62N 8-Bit timer (TMR)	Yoshinori Sato
2020-06-22	hw/intc: RX62N interrupt controller (ICUa)	Yoshinori Sato
2020-06-22	hw/timer/sh_timer: Remove unused 'qemu/timer.h' include	Philippe Mathieu-Daudé
2020-06-22	hw/sh4: Extract timer definitions to 'hw/timer/tmu012.h'	Philippe Mathieu-Daudé
2020-06-22	hw/sh4: Use MemoryRegion typedef	Philippe Mathieu-Daudé
2020-06-22	MAINTAINERS: Add an entry for common Renesas peripherals	Philippe Mathieu-Daudé
2020-06-22	MAINTAINERS: Cover sh_intc files in the R2D/Shix machine sections	Philippe Mathieu-Daudé
2020-06-22	Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...	Peter Maydell
2020-06-22	target/xtensa: drop gen_io_end call	Max Filippov
2020-06-21	tests/acceptance: record/replay tests with advcal images	Pavel Dovgalyuk
2020-06-21	tests/acceptance: add record/replay test for m68k	Pavel Dovgalyuk
2020-06-21	tests/acceptance: add record/replay test for ppc64	Pavel Dovgalyuk
2020-06-21	tests/acceptance: add record/replay test for arm	Pavel Dovgalyuk
2020-06-21	tests/acceptance: add record/replay test for aarch64	Pavel Dovgalyuk
2020-06-21	tests/acceptance: add kernel record/replay test for x86_64	Pavel Dovgalyuk
2020-06-21	tests/acceptance: add base class record/replay kernel tests	Pavel Dovgalyuk
2020-06-21	MAINTAINERS: Add an entry to review Avocado based acceptance tests	Philippe Mathieu-Daudé
2020-06-19	Merge remote-tracking branch 'remotes/kraxel/tags/audio-20200619-pull-request...	Peter Maydell
2020-06-19	qht: Fix threshold rate calculation	Richard Henderson
2020-06-19	hw/riscv: sifive_u: Add a dummy DDR memory controller device	Bin Meng
2020-06-19	hw/riscv: sifive_u: Sort the SoC memmap table entries	Bin Meng
2020-06-19	hw/riscv: sifive_u: Support different boot source per MSEL pin state	Bin Meng
2020-06-19	hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004	Bin Meng
2020-06-19	target/riscv: Rename IBEX CPU init routine	Bin Meng
2020-06-19	hw/riscv: sifive_u: Add a new property msel for MSEL pin state	Bin Meng
2020-06-19	hw/riscv: sifive_u: Rename serial property get/set functions to a generic name	Bin Meng
2020-06-19	hw/riscv: sifive_u: Add reset functionality	Bin Meng
2020-06-19	hw/riscv: sifive_gpio: Do not blindly trigger output IRQs	Bin Meng
2020-06-19	hw/riscv: sifive_u: Hook a GPIO controller	Bin Meng
2020-06-19	hw/riscv: sifive_gpio: Add a new 'ngpio' property	Bin Meng
2020-06-19	hw/riscv: sifive_gpio: Clean up the codes	Bin Meng
2020-06-19	hw/riscv: sifive_u: Generate device tree node for OTP	Bin Meng
2020-06-19	hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit	Bin Meng
2020-06-19	hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng
2020-06-19	hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng
2020-06-19	target/riscv: Use a smaller guess size for no-MMU PMP	Alistair Francis
2020-06-19	riscv/opentitan: Connect the UART device	Alistair Francis
2020-06-19	riscv/opentitan: Connect the PLIC device	Alistair Francis
2020-06-19	hw/intc: Initial commit of lowRISC Ibex PLIC	Alistair Francis
2020-06-19	hw/char: Initial commit of Ibex UART	Alistair Francis
2020-06-19	riscv/opentitan: Fix the ROM size	Alistair Francis
2020-06-19	target/riscv: Implement checks for hfence	Alistair Francis
2020-06-19	target/riscv: Move the hfence instructions to the rvh decode	Alistair Francis
2020-06-19	target/riscv: Report errors validating 2nd-stage PTEs	Alistair Francis
2020-06-19	target/riscv: Set access as data_load when validating stage-2 PTEs	Alistair Francis
2020-06-19	riscv: Keep the CPU init routine names consistent	Bin Meng