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2016-01-22seabios: fix submoduleGerd Hoffmann
Commit "36f96c4 target-i386: Add support to migrate vcpu's TSC rate" updates roms/seabios, appearently by mistake. Revert this. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 1453460391-7664-1-git-send-email-kraxel@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21Merge remote-tracking branch 'remotes/sstabellini/tags/xen-20160121' into ↵Peter Maydell
staging Xen 2016/01/21 # gpg: Signature made Thu 21 Jan 2016 16:58:50 GMT using RSA key ID 70E1AE90 # gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" * remotes/sstabellini/tags/xen-20160121: Xen PCI passthru: convert to realize() Add Error **errp for xen_pt_config_init() Add Error **errp for xen_pt_setup_vga() Add Error **errp for xen_host_pci_device_get() Xen: use qemu_strtoul instead of strtol Change xen_host_pci_sysfs_path() to return void xen-pvdevice: convert to realize() xen-hvm: Clean up xen_ram_alloc() error handling xen-hvm: Clean up xen_hvm_init() error handling xenfb.c: avoid expensive loops when prod <= out_cons MAINTAINERS: update Xen files Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21Xen PCI passthru: convert to realize()Cao jin
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2016-01-21Add Error **errp for xen_pt_config_init()Cao jin
To catch the error message. Also modify the caller Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2016-01-21Add Error **errp for xen_pt_setup_vga()Cao jin
To catch the error message. Also modify the caller Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2016-01-21Add Error **errp for xen_host_pci_device_get()Cao jin
To catch the error message. Also modify the caller Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-01-21Xen: use qemu_strtoul instead of strtolCao jin
No need to roll our own (with slightly incorrect handling of errno), when we can use the common version. Change signed parsing to unsigned, because what it read are values in PCI config space, which are non-negative. Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-01-21Change xen_host_pci_sysfs_path() to return voidCao jin
And assert the snprintf() error, because user can do nothing in case of snprintf() fail. Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-01-21Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell
staging X86 queue, 2016-01-21 # gpg: Signature made Thu 21 Jan 2016 15:08:40 GMT using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" * remotes/ehabkost/tags/x86-pull-request: target-i386: Add PKU and and OSPKE support target-i386: Add support to migrate vcpu's TSC rate target-i386: Reorganize TSC rate setting code target-i386: Fallback vcpu's TSC rate to value returned by KVM target-i386: Add suffixes to MMReg struct fields target-i386: Define MMREG_UNION macro target-i386: Define MMXReg._d field target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_* target-i386: Rename struct XMMReg to ZMMReg target-i386: Use a _q array on MMXReg too target-i386/ops_sse.h: Use MMX_Q macro target-i386: Rename optimize_flags_init() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21xen-pvdevice: convert to realize()Cao jin
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2016-01-21Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20160121' into staging target-arm queue: * connect SPI devices in Xilinx Zynq platforms * multiple-address-space support * use multiple-address-space support for ARM TrustZone * arm_gic: return correct ID registers for 11MPCore/v1/v2 GICs * various fixes for (currently disabled) AArch64 EL2 and EL3 support * add 'always-on' property to the virt board timer DT entry # gpg: Signature made Thu 21 Jan 2016 14:54:56 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20160121: (36 commits) target-arm: Implement FPEXC32_EL2 system register target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode target-arm: Implement remaining illegal return event checks target-arm: Handle exception return from AArch64 to non-EL0 AArch32 target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target target-arm: Pull semihosting handling out to arm_cpu_do_interrupt() target-arm: Use a single entry point for AArch64 and AArch32 exceptions target-arm: Move aarch64_cpu_do_interrupt() to helper.c target-arm: Properly support EL2 and EL3 in arm_el_is_aa64() arm_gic: Update ID registers based on revision hw/arm/virt: Add always-on property to the virt board timer hw/arm/virt: add secure memory region and UART hw/arm/virt: Wire up memory region to CPUs explicitly target-arm: Support multiple address spaces in page table walks target-arm: Implement cpu_get_phys_page_attrs_debug target-arm: Implement asidx_from_attrs target-arm: Add QOM property for Secure memory region qom/cpu: Add MemoryRegion property memory: Add address_space_init_shareable() exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21target-i386: Add PKU and and OSPKE supportHuaitong Han
Add PKU and OSPKE CPUID features, including xsave state and migration support. Signed-off-by: Huaitong Han <huaitong.han@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: squashed 3 patches together, edited patch description] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Add support to migrate vcpu's TSC rateHaozhong Zhang
This patch enables migrating vcpu's TSC rate. If KVM on the destination machine supports TSC scaling, guest programs will observe a consistent TSC rate across the migration. If TSC scaling is not supported on the destination machine, the migration will not be aborted and QEMU on the destination will not set vcpu's TSC rate to the migrated value. If vcpu's TSC rate specified by CPU option 'tsc-freq' on the destination machine is inconsistent with the migrated TSC rate, the migration will be aborted. For backwards compatibility, the migration of vcpu's TSC rate is disabled on pc-*-2.5 and older machine types. Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: Rewrote comment at kvm_arch_put_registers()] [ehabkost: Moved compat code to pc-2.5] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Reorganize TSC rate setting codeHaozhong Zhang
Following changes are made to the TSC rate setting code in kvm_arch_init_vcpu(): * The code is moved to a new function kvm_arch_set_tsc_khz(). * If kvm_arch_set_tsc_khz() fails, i.e. following two conditions are both satisfied: * KVM does not support the TSC scaling or it fails to set vcpu's TSC rate by KVM_SET_TSC_KHZ, * the TSC rate to be set is different than the value currently used by KVM, then kvm_arch_init_vcpu() will fail. Prevously, * the lack of TSC scaling never failed kvm_arch_init_vcpu(), * the failure of KVM_SET_TSC_KHZ failed kvm_arch_init_vcpu() unconditionally, even though the TSC rate to be set is identical to the value currently used by KVM. Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Fallback vcpu's TSC rate to value returned by KVMHaozhong Zhang
If no user-specified TSC rate is present, we will try to set env->tsc_khz to the value returned by KVM_GET_TSC_KHZ. This patch does not change the current functionality of QEMU and just prepares for later patches to enable migrating vcpu's TSC rate. Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Add suffixes to MMReg struct fieldsEduardo Habkost
This will ensure we never use the MMX_* and ZMM_* macros with the wrong struct type. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Define MMREG_UNION macroEduardo Habkost
This will simplify the definitions of ZMMReg and MMXReg. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Define MMXReg._d fieldEduardo Habkost
Add a new field and reorder MMXReg fields, to make MMXReg and ZMMReg field lists look the same (except for the array sizes). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_*Eduardo Habkost
They are helpers for the ZMMReg fields, so name them accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Rename struct XMMReg to ZMMRegEduardo Habkost
The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Use a _q array on MMXReg tooEduardo Habkost
Make MMXReg use the same field names used on XMMReg, so we can try to reuse macros and other code later. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386/ops_sse.h: Use MMX_Q macroEduardo Habkost
We have a MMX_Q macro in addition to MMX_{B,W,L}. Use it. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Rename optimize_flags_init()Eduardo Habkost
Rename the function so that the reason for its existence is clearer: it does x86-specific initialization of TCG structures. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-arm: Implement FPEXC32_EL2 system registerPeter Maydell
The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, and allows those exception levels to read and write the FPEXC register for a lower exception level that is using AArch32. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1453132414-8127-1-git-send-email-peter.maydell@linaro.org
2016-01-21target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM modePeter Maydell
The architecture requires that for an exception return to AArch32 the low bits of ELR_ELx are ignored when the PC is set from them: * if returning to Thumb mode, ignore ELR_ELx[0] * if returning to ARM mode, ignore ELR_ELx[1:0] We were only squashing bit 0; also squash bit 1 if the SPSR T bit indicates this is a return to ARM code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Implement remaining illegal return event checksPeter Maydell
We already implement almost all the checks for the illegal return events from AArch64 state described in the ARM ARM section D1.11.2. Add the two missing ones: * return to EL2 when EL3 is implemented and SCR_EL3.NS is 0 * return to Non-secure EL1 when EL2 is implemented and HCR_EL2.TGE is 1 (We don't implement external debug, so the case of "debug state exit from EL0 using AArch64 state to EL0 using AArch32 state" doesn't apply for QEMU.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Handle exception return from AArch64 to non-EL0 AArch32Peter Maydell
Remove the assumptions that the AArch64 exception return code was making about a return to AArch32 always being a return to EL0. This includes pulling out the illegal-SPSR checks so we can apply them for return to 32 bit as well as return to 64-bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Fix wrong AArch64 entry offset for EL2/EL3 targetPeter Maydell
The entry offset when taking an exception to AArch64 from a lower exception level may be 0x400 or 0x600. 0x400 is used if the implemented exception level immediately lower than the target level is using AArch64, and 0x600 if it is using AArch32. We were incorrectly implementing this as checking the exception level that the exception was taken from. (The two can be different if for example we take an exception from EL0 to AArch64 EL3; we should in this case be checking EL2 if EL2 is implemented, and EL1 if EL2 is not implemented.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()Peter Maydell
Handling of semihosting calls should depend on the register width of the calling code, not on that of any higher exception level, so we need to identify and handle semihosting calls before we decide whether to deliver the exception as an entry to AArch32 or AArch64. (EXCP_SEMIHOST is also an "internal exception" so it has no target exception level in the first place.) This will allow AArch32 EL1 code to use semihosting calls when running under an AArch64 EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21target-arm: Use a single entry point for AArch64 and AArch32 exceptionsPeter Maydell
If EL2 or EL3 is present on an AArch64 CPU, then exceptions can be taken to an exception level which is running AArch32 (if only EL0 and EL1 are present then EL1 must be AArch64 and all exceptions are taken to AArch64). To support this we need to have a single implementation of the CPU do_interrupt() method which can handle both 32 and 64 bit exception entry. Pull the common parts of aarch64_cpu_do_interrupt() and arm_cpu_do_interrupt() out into a new function which calls either the AArch32 or AArch64 specific entry code once it has worked out which one is needed. We temporarily special-case the handling of EXCP_SEMIHOST to avoid an assertion in arm_el_is_aa64(); the next patch will pull all the semihosting handling out to the arm_cpu_do_interrupt() level (since semihosting semantics depend on the register width of the calling code, not on that of any higher EL). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Move aarch64_cpu_do_interrupt() to helper.cPeter Maydell
Move the aarch64_cpu_do_interrupt() function to helper.c. We want to be able to call this from code that isn't AArch64-only, and the move allows us to avoid awkward #ifdeffery at the callsite. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()Peter Maydell
Support EL2 and EL3 in arm_el_is_aa64() by implementing the logic for checking the SCR_EL3 and HCR_EL2 register-width bits as appropriate to determine the register width of lower exception levels. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21arm_gic: Update ID registers based on revisionAlistair Francis
Update the GIC ID registers (registers above 0xfe0) based on the GIC revision instead of using the sames values for all GIC implementations. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Message-id: 629e7fa5d47f2800e51cc1f18d12635f1eece349.1453333840.git.alistair.francis@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21hw/arm/virt: Add always-on property to the virt board timerChristoffer Dall
The virt board has an arch timer, which is always on. Emit the "always-on" property to indicate to Linux that it can switch off the periodic timer and reduces the amount of interrupts injected into a guest. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1453204158-11412-1-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21hw/arm/virt: add secure memory region and UARTPeter Maydell
Add a secure memory region to the virt board, which is the same as the nonsecure memory region except that it also has a secure-only UART in it. This is only created if the board is started with the '-machine secure=on' property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21hw/arm/virt: Wire up memory region to CPUs explicitlyPeter Maydell
Wire up the system memory region to the CPUs explicitly by setting the QOM property. This doesn't change anything over letting it default, but will be needed for adding a secure memory region later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Support multiple address spaces in page table walksPeter Maydell
If we have a secure address space, use it in page table walks: when doing the physical accesses to read descriptors, make them through the correct address space. (The descriptor reads are the only direct physical accesses made in target-arm/ for CPUs which might have TrustZone.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Implement cpu_get_phys_page_attrs_debugPeter Maydell
Implement cpu_get_phys_page_attrs_debug instead of cpu_get_phys_page_debug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Implement asidx_from_attrsPeter Maydell
Implement the asidx_from_attrs CPU method to return the Secure or NonSecure address space as appropriate. (The function is inline so we can use it directly in target-arm code to be added in later patches.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Add QOM property for Secure memory regionPeter Maydell
Add QOM property to the ARM CPU which boards can use to tell us what memory region to use for secure accesses. Nonsecure accesses go via the memory region specified with the base CPU class 'memory' property. By default, if no secure region is specified it is the same as the nonsecure region, and if no nonsecure region is specified we will use address_space_memory. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21qom/cpu: Add MemoryRegion propertyPeter Crosthwaite
Add a MemoryRegion property, which if set is used to construct the CPU's initial (default) AddressSpace. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [PMM: code is moved from qom/cpu.c to exec.c to avoid having to make qom/cpu.o be a non-common object file; code to use the MemoryRegion and to default it to system_memory added.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21memory: Add address_space_init_shareable()Peter Crosthwaite
This will either create a new AS or return a pointer to an already existing equivalent one, if we have already created an AS for the specified root memory region. The motivation is to reuse address spaces as much as possible. It's going to be quite common that bus masters out in device land have pointers to the same memory region for their mastering yet each will need to create its own address space. Let the memory API implement sharing for them. Aside from the perf optimisations, this should reduce the amount of redundant output on info mtree as well. Thee returned value will be malloced, but the malloc will be automatically freed when the AS runs out of refs. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [PMM: dropped check for NULL root as unused; added doc-comment; squashed Peter C's reference-counting patch into this one; don't compare name string when deciding if we can share ASes; read as->malloced before the unref of as->root to avoid possible read-after-free if as->root was the owner of as] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_writePeter Maydell
In the watchpoint access routines watch_mem_read and watch_mem_write, find the correct AddressSpace to use from current_cpu and the memory transaction attributes, rather than always assuming address_space_memory. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21exec.c: Use cpu_get_phys_page_attrs_debugPeter Maydell
Use cpu_get_phys_page_attrs_debug() when doing virtual-to-physical conversions in debug related code, so that we can obtain the right address space index and thus select the correct AddressSpace, rather than always using cpu->as. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21exec.c: Add cpu_get_address_space()Peter Maydell
Add a function to return the AddressSpace for a CPU based on its numerical index. (Callers outside exec.c don't have access to the CPUAddressSpace struct so can't just fish it out of the CPUState struct directly.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right ASPeter Maydell
Pass the MemTxAttrs for the memory access to iotlb_to_region(); this allows it to determine the correct AddressSpace to use for the lookup. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21cputlb.c: Use correct address space when looking up MemoryRegionSectionPeter Maydell
When looking up the MemoryRegionSection for the new TLB entry in tlb_set_page_with_attrs(), use cpu_asidx_from_attrs() to determine the correct address space index for the lookup, and pass it into address_space_translate_for_iotlb(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21cpu: Add new asidx_from_attrs() methodPeter Maydell
Add a new method to CPUClass which the memory system core can use to obtain the correct address space index to use for a memory access with a given set of transaction attributes, together with the wrapper function cpu_asidx_from_attrs() which implements the default behaviour ("always use asidx 0") for CPU classes which don't provide the method. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21cpu: Add new get_phys_page_attrs_debug() methodPeter Maydell
Add a new optional method get_phys_page_attrs_debug() to CPUClass. This is like the existing get_phys_page_debug(), but also returns the memory transaction attributes to use for the access. This will be necessary for CPUs which have multiple address spaces and use the attributes to select the correct address space. We provide a wrapper function cpu_get_phys_page_attrs_debug() which falls back to the existing get_phys_page_debug(), so we don't need to change every target CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21exec-all.h: Document tlb_set_page_with_attrs, tlb_set_pagePeter Maydell
Add documentation comments for tlb_set_page_with_attrs() and tlb_set_page(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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