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2021-03-07esp: remove dma_counter from ESPStateMark Cave-Ayland
The value of dma_counter is set once at the start of the transfer and remains the same until the transfer is complete. This allows the check in esp_transfer_data to be simplified since dma_left will always be non-zero until the transfer is completed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-13-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: apply transfer length adjustment when STC is zero at TC load timeMark Cave-Ayland
Perform the length adjustment whereby a value of 0 in the STC represents a transfer length of 0x10000 at the point where the TC is loaded at the start of a DMA command rather than just when a TI (Transfer Information) command is executed. This better matches the description as given in the datasheet. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-12-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: introduce esp_get_stc()Mark Cave-Ayland
This function simplifies reading the STC register value without having to manually shift each individual 8-bit value. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-11-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: introduce esp_get_tc() and esp_set_tc()Mark Cave-Ayland
These functions simplify reading and writing the TC register value without having to manually shift each individual 8-bit value. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-10-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: determine transfer direction directly from SCSI phaseMark Cave-Ayland
The transfer direction is currently determined by checking the sign of ti_size but as this series progresses ti_size can be zero at the end of the transfer. Use the SCSI phase to determine the transfer direction as used in other SCSI controller implementations. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-9-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: add PDMA trace eventsMark Cave-Ayland
This will become more useful later when trying to debug mixed FIFO and PDMA requests. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-8-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: fix esp_reg_read() trace eventMark Cave-Ayland
Move the trace event to the end of the function so that it correctly reports the returned value if it doesn't come directly from the rregs array. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-7-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: add trace event when receiving a TI commandMark Cave-Ayland
This enables us to determine whether the command being issued is for a DMA or a non-DMA transfer. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-6-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: add vmstate_esp version to embedded ESPStateMark Cave-Ayland
The QOM object representing ESPState is currently embedded within both the SYSBUS_ESP and PCI_ESP devices with migration state handled by embedding vmstate_esp within each device using VMSTATE_STRUCT. Since the vmstate_esp fields are embedded directly within the migration stream, the incoming vmstate_esp version_id is lost. The only version information available is that from vmstate_sysbus_esp_scsi and vmstate_esp_pci_scsi, but those versions represent their respective devices and not that of the underlying ESPState. Resolve this by adding a new version-dependent field in vmstate_sysbus_esp_scsi and vmstate_esp_pci_scsi which stores the vmstate_esp version_id field within ESPState to be used to allow migration from older QEMU versions. Finally bump the vmstate_esp version to 5 to cover the upcoming ESPState changes within this patch series. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-5-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: QOMify the internal ESP device stateMark Cave-Ayland
Make this new QOM device state a child device of both the sysbus-esp and esp-pci implementations. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-4-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: rename existing ESP QOM type to SYSBUS_ESPMark Cave-Ayland
The existing ESP QOM type currently represents a sysbus device with an embedded ESP state. Rename the type to SYSBUS_ESP accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-3-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: checkpatch fixesMark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-2-mark.cave-ayland@ilande.co.uk>
2021-03-06target/hexagon/opcodes: Add missing varargs cleanupPhilippe Mathieu-Daudé
Fix a trivial incorrect usage of variable argument macros detected by Coverity (missing_va_end: va_end was not called for ap). Fixes: Coverity CID 1446720 (VARARGS) Fixes: e3c00c2ed75 ("Hexagon (target/hexagon) opcode data structures") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20210223111253.2831285-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06target/hexagon: Fix shift amount check in fASHIFTL/fLSHIFTRTaylor Simpson
Fixes: a646e99cb90 ("Hexagon (target/hexagon) macros") Eliminate the following Coverity CIDs (Bad bit shift operation) 325227 325292 325425 325526 325561 325564 325578 325637 325736 325748 325786 325815 325837 Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1614879425-9259-1-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06exec: Poison Hexagon target-specific definitionsPhilippe Mathieu-Daudé
Commit 3e7a84eeccc ("Hexagon build infrastructure") added Hexagon definitions that should be poisoned on target independent device code, but forgot to update "exec/poison.h". Do it now. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20210219135754.1968100-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06accel/tcg: Precompute curr_cflags into cpu->tcg_cflagsRichard Henderson
The primary motivation is to remove a dozen insns along the fast-path in tb_lookup. As a byproduct, this allows us to completely remove parallel_cpus. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06include/exec: lightly re-arrange TranslationBlockAlex Bennée
Lets make sure all the flags we compare when looking up blocks are together in the same place. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210224165811.11567-5-alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06accel/tcg: drop the use of CF_HASH_MASK and rename paramsAlex Bennée
We don't really deal in cf_mask most of the time. The one time it's relevant is when we want to remove an invalidated TB from the QHT lookup. Everywhere else we should be looking up things without CF_INVALID set. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210224165811.11567-4-alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06accel/tcg: move CF_CLUSTER calculation to curr_cflagsAlex Bennée
There is nothing special about this compile flag that doesn't mean we can't just compute it with curr_cflags() which we should be using when building a new set. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210224165811.11567-3-alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06accel/tcg: rename tb_lookup__cpu_state and hoist state extractionAlex Bennée
Having a function return either and valid TB and some system state seems excessive. It will make the subsequent re-factoring easier if we lookup the current state where we are. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210224165811.11567-2-alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge mov, not and neg operationsRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge bswap operationsRichard Henderson
This includes bswap16 and bswap32. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge extension operationsRichard Henderson
This includes ext8s, ext8u, ext16s, ext16u. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge basic arithmetic operationsRichard Henderson
This includes add, sub, mul, and, or, xor. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Reduce use of tci_read_r64Richard Henderson
In all cases restricted to 64-bit hosts, tcg_read_r is identical. We retain the 64-bit symbol for the single case of INDEX_op_qemu_st_i64. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r32sRichard Henderson
Use explicit casts for ext32s opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r32Richard Henderson
Use explicit casts for ext32u opcodes, and allow truncation to happen for other users. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r16sRichard Henderson
Use explicit casts for ext16s opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r16Richard Henderson
Use explicit casts for ext16u opcodes, and allow truncation to happen with the store for st16 opcodes, and with the call for bswap16 opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r8sRichard Henderson
Use explicit casts for ext8s opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r8Richard Henderson
Use explicit casts for ext8u opcodes, and allow truncation to happen with the store for st8 opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (load/store opcodes)Richard Henderson
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 5/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-6-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (conditional opcodes)Richard Henderson
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 4/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-5-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (deposit opcode)Richard Henderson
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 3/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-4-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (exchange opcodes)Richard Henderson
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 2/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-3-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (arithmetic opcodes)Richard Henderson
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 1/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg: Manage splitwx in tc_ptr_to_region_tree by handRichard Henderson
The use in tcg_tb_lookup is given a random pc that comes from the pc of a signal handler. Do not assert that the pointer is already within the code gen buffer at all, much less the writable mirror of it. Fixes: db0c51a3803 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg: Split out tcg_raise_tb_overflowRichard Henderson
Allow other places in tcg to restart with a smaller tb. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Use exec/cpu_ldst.h interfacesRichard Henderson
Use the provided cpu_ldst.h interfaces. This fixes the build vs the unconverted uses of g2h(), adds missed memory trace events, and correctly recognizes when a SIGSEGV belongs to the guest via set_helper_retaddr(). Fixes: 3e8f1628e864 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/aarch64: Fix generation of "scalar" vector operationsRichard Henderson
For some vector operations, "1D" is not a valid type, and there are separate instructions for the 64-bit scalar operation. Tested-by: Stefan Weil <sw@weilnetz.de> Buglink: https://bugs.launchpad.net/qemu/+bug/1916112 Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/aarch64: Fix I3617_CMLE0Richard Henderson
Fix a typo in the encodeing of the cmle (zero) instruction. Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/aarch64: Fix constant subtraction in tcg_out_addsub2Richard Henderson
An hppa guest executing 0x000000000000e05c: ldil L%10000,r4 0x000000000000e060: ldo 0(r4),r4 0x000000000000e064: sub r3,r4,sp produces ---- 000000000000e064 000000000000e068 sub2_i32 tmp0,tmp4,r3,$0x1,$0x10000,$0x0 after folding and constant propagation. Then we hit tcg-target.c.inc:640: tcg_out_insn_3401: Assertion `aimm <= 0xfff' failed. because aimm is in fact -16, but unsigned. The ((bl < 0) ^ sub) condition which negates bl is incorrect and will always lead to this abort. If the constant is positive, sub will make it negative; if the constant is negative, sub will keep it negative. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06hw/sh4/sh7750_regs: Replace link to license by its full contentPhilippe Mathieu-Daudé
This file is borrowed from the RTEMS source code, which comes with a GPL-2.0-or-later license with a header exception. Expand the GPL-2.0-or-later license in place to not be dependent on a 3rd party website. This also fix the misleading comment "The license and distribution terms for this file may be found in the file LICENSE in this distribution" referring to the RTEMS distribution and not to the QEMU one. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210222185605.2714192-1-f4bug@amsat.org>
2021-03-06hw/sh4: Remove now unused CONFIG_SH4 from KconfigPhilippe Mathieu-Daudé
As replaced the generic CONFIG_SH4 by more fine-grained selectors, we can remove this now unused config variable. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-9-f4bug@amsat.org>
2021-03-06hw/pci-host: Introduce SH_PCI Kconfig entryPhilippe Mathieu-Daudé
We want to be able to use the 'SH4' config for architecture specific features. Add more fine-grained selection by adding a CONFIG_SH_PCI selector for the SH4 PCI controller. Move the file with the other PCI host devices in hw/pci-host and add its missing MAINTAINERS entries. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-8-f4bug@amsat.org>
2021-03-06hw/block: Introduce TC58128 eeprom Kconfig entryPhilippe Mathieu-Daudé
Add more fine-grained selection by adding a CONFIG_TC58128 selector for the TC58128 eeprom. As this device is only used by the Shix machine, add an entry to the proper section in MAINTAINERS. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-7-f4bug@amsat.org>
2021-03-06hw/timer: Introduce SH_TIMER Kconfig entryPhilippe Mathieu-Daudé
We want to be able to use the 'SH4' config for architecture specific features. Add more fine-grained selection by adding a CONFIG_SH_TIMER selector for the SH4 timer control unit. Add the missing MAINTAINERS entries. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-6-f4bug@amsat.org>
2021-03-06hw/char: Introduce SH_SCI Kconfig entryPhilippe Mathieu-Daudé
We want to be able to use the 'SH4' config for architecture specific features. Add more fine-grained selection by adding a CONFIG_SH_SCI selector for the SH4 serial controller. Add the missing MAINTAINERS entries. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-5-f4bug@amsat.org>
2021-03-06hw/intc: Introduce SH_INTC Kconfig entryPhilippe Mathieu-Daudé
We want to be able to use the 'SH4' config for architecture specific features. Add more fine-grained selection by adding a CONFIG_SH_INTC selector for the SH4 interrupt controller. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-4-f4bug@amsat.org>
2021-03-06hw/sh4: Add missing Kconfig dependency on SH7750 for the R2D boardPhilippe Mathieu-Daudé
r2d_init() calls sh7750_init() so depends on SH7750.Harmless at the moment because nothing actually uses CONFIG_SH7750 (hw/sh4/meson.build always compiles sh7750.c and sh7750_regnames.c unconditionally). Fixes: 7ab58d4c841 ("sh4-softmmu.mak: express dependencies with Kconfig") Reported-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-3-f4bug@amsat.org>
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