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2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann
We now utilizes argument-sets of decodetree such that no manual decoding is necessary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann
trans_jalr() is the only caller, so move the code into trans_jalr(). Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann
we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann
this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-12Merge remote-tracking branch ↵Peter Maydell
'remotes/huth-gitlab/tags/pull-request-2019-03-12' into staging - qtest patches - One SD patch (with Reviewed-by from the maintainer) - One license fix patch # gpg: Signature made Tue 12 Mar 2019 09:03:58 GMT # gpg: using RSA key 2ED9D774FE702DB5 # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth-gitlab/tags/pull-request-2019-03-12: scripts/qemugdb: re-license timers.py to GPLv2 or later hw/sd/sdhci: Move PCI-related code into a separate file ahci-test: Drop dependence on global_qtest tests: test-announce-self: fix memory leak Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-12Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/python-next-pull-request' into staging qmp-shell: fix nested json regression One small bug fix. # gpg: Signature made Tue 12 Mar 2019 02:16:24 GMT # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/python-next-pull-request: qmp-shell: fix nested json regression Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-12Merge remote-tracking branch ↵Peter Maydell
'remotes/kraxel/tags/audio-20190312-pull-request' into staging audio: introduce -audiodev # gpg: Signature made Tue 12 Mar 2019 07:12:19 GMT # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/audio-20190312-pull-request: audio: -audiodev command line option: cleanup wavaudio: port to -audiodev config spiceaudio: port to -audiodev config sdlaudio: port to -audiodev config paaudio: port to -audiodev config ossaudio: port to -audiodev config noaudio: port to -audiodev config dsoundaudio: port to -audiodev config coreaudio: port to -audiodev config alsaaudio: port to -audiodev config audio: -audiodev command line option basic implementation audio: -audiodev command line option: documentation audio: use qapi AudioFormat instead of audfmt_e qapi: qapi for audio backends Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # qemu-deprecated.texi
2019-03-12Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine queue, 2019-03-11 * memfd fixes (Ilya Maximets) * Move nvdimms state into struct MachineState (Eric Auger) * hostmem-file: reject invalid pmem file sizes (Stefan Hajnoczi) # gpg: Signature made Tue 12 Mar 2019 00:57:41 GMT # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: memfd: improve error messages memfd: set up correct errno if not supported memfd: always check for MFD_CLOEXEC hostmem-memfd: disable for systems without sealing support machine: Move nvdimms state into struct MachineState nvdimm: Rename AcpiNVDIMMState into NVDIMMState hostmem-file: reject invalid pmem file sizes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-12Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20190311.0' ↵Peter Maydell
into staging VFIO updates 2019-03-11 - Resolution support for mdev displays supporting EDID interface (Gerd Hoffmann) # gpg: Signature made Mon 11 Mar 2019 19:17:39 GMT # gpg: using RSA key 239B9B6E3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [full] # gpg: aka "Alex Williamson <alex@shazbot.org>" [full] # gpg: aka "Alex Williamson <alwillia@redhat.com>" [full] # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" [full] # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * remotes/awilliam/tags/vfio-updates-20190311.0: vfio/display: delay link up event vfio/display: add xres + yres properties vfio/display: add edid support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-12Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-pull-request' into staging fw_cfg and thunk code clean up # gpg: Signature made Mon 11 Mar 2019 19:11:03 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-pull-request: hw/nvram/fw_cfg: Use the ldst API hw/arm/virt: Remove null-check in virt_build_smbios() hw/i386: Remove unused include hw/nvram/fw_cfg: Remove the unnecessary boot_splash_filedata_size thunk: improve readability of allocation loop Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-12Merge remote-tracking branch 'remotes/armbru/tags/pull-pflash-2019-03-11' ↵Peter Maydell
into staging Pflash and firmware configuration patches for 2019-03-11 # gpg: Signature made Mon 11 Mar 2019 21:59:12 GMT # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-pflash-2019-03-11: (27 commits) docs/interop/firmware.json: Prefer -machine to if=pflash pc: Support firmware configuration with -blockdev pc_sysfw: Pass PCMachineState to pc_system_firmware_init() pc_sysfw: Remove unused PcSysFwDevice pflash_cfi01: Add pflash_cfi01_get_blk() helper vl: Create block backends before setting machine properties vl: Factor configure_blockdev() out of main() vl: Improve legibility of BlockdevOptions queue sysbus: Fix latent bug with onboard devices vl: Fix latent bug with -global and onboard devices qom: Move compat_props machinery from qdev to QOM qdev: Fix latent bug with compat_props and onboard devices pflash: Clean up after commit 368a354f02b, part 2 pflash: Clean up after commit 368a354f02b, part 1 mips_malta: Clean up definition of flash memory size somewhat hw/mips/malta: Restrict 'bios_size' variable scope hw/mips/malta: Remove fl_sectors variable mips_malta: Delete disabled, broken DEBUG_BOARD_INIT code r2d: Fix flash memory size, sector size, width, device ID ppc405_boards: Don't size flash memory to match backing image ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-12Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190312' ↵Peter Maydell
into staging ppc patch queue for 2019-03-10 This pull requests supersedes ppc-for-4.0-20190310. Changes are: * Fixed a bunch of minor style problems * Suppressed warnings about Spectre/Meltdown mitigations with TCG * Added one more patch, a preliminary fix towards the not-quite-ready support for NVLink VFIO passthrough. This is a final pull request before the 4.0 soft freeze. Changes include: * A Great Renaming to use camel case properly in spapr code * Optimization of some vector instructions * Support for POWER9 cpus in the powernv machine * Fixes a regression from the last pull request in handling VSX instructions with mixed operands from the FPR and VMX parts of the register array * Optimization hack to avoid scanning all the (empty) entries on a new IOMMU window * Add FSL I2C controller model for E500 * Support for KVM acceleration of the H_PAGE_INIT hypercall on spapr * Update u-boot image for E500 * Enable Specre/Meltdown mitigations by default on the new machine type * Enable large decrementer support for POWER9 # gpg: Signature made Tue 12 Mar 2019 08:14:51 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-4.0-20190312: (62 commits) vfio: Make vfio_get_region_info_cap public Suppress test warnings about missing Spectre/Meltdown mitigations with TCG spapr: Use CamelCase properly target/ppc: Optimize x[sv]xsigdp using deposit_i64() target/ppc: Optimize xviexpdp() using deposit_i64() target/ppc: add HV support for POWER9 ppc/pnv: add a "ibm,opal/power-mgt" device tree node on POWER9 ppc/pnv: add more dummy XSCOM addresses ppc/pnv: activate XSCOM tests for POWER9 ppc/pnv: POWER9 XSCOM quad support ppc/pnv: extend XSCOM core support for POWER9 ppc/pnv: add a OCC model for POWER9 ppc/pnv: add a OCC model class ppc/pnv: add SerIRQ routing registers ppc/pnv: add a LPC Controller model for POWER9 ppc/pnv: add a 'dt_isa_nodename' to the chip ppc/pnv: add a LPC Controller class model ppc/pnv: lpc: fix OPB address ranges ppc/pnv: add a PSI bridge model for POWER9 ppc/pnv: add a PSI bridge class model ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-12scripts/qemugdb: re-license timers.py to GPLv2 or laterAlex Bennée
I'm the sole author (aside from a one line by Greg fixing encoding) and I was asked nicely on IRC to bring it into line with the rest of the files. Cc: Greg Kurz <groug@kaod.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-03-12hw/sd/sdhci: Move PCI-related code into a separate fileThomas Huth
Some machines have an SDHCI device, but no PCI. To be able to compile hw/sd/sdhci.c without CONFIG_PCI, we must not call functions like pci_get_address_space() and pci_allocate_irq() there. Thus move the PCI-related code into a separate file. This is required for the new Kconfig-like build system, e.g. it is needed if a user wants to compile a QEMU binary with just one machine that has SDHCI, but no PCI, like the ARM "raspi" machines for example. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-03-12ahci-test: Drop dependence on global_qtestEric Blake
Managing parallel connections to two different monitors via the implicit global_qtest makes it hard to copy-and-paste code to tests that are not aware of the implicit state; the management of global_qtest is even harder to follow because it was masked behind set_context(). Instead, explicitly pass QTestState* around (generally, by reusing the member already present in ahci->parent QOSState), and call explicit qtest_* functions on all places that interact with a monitor. We can assert that the conversion is correct by checking that global_qtest remains NULL throughout the test (a later patch that changes global_qtest to not be a public global variable will drop the assertions). Signed-off-by: Eric Blake <eblake@redhat.com> Acked-by: John Snow <jsnow@redhat.com> [thuth: rebased patch to current master branch] Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-03-12tests: test-announce-self: fix memory leakLi Qiang
Spotted by ASAN while running 'make check'. Fixes: 4b9b7000 ("tests: Add a test for qemu self announcements") Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Li Qiang <liq3ea@163.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-03-12vfio: Make vfio_get_region_info_cap publicAlexey Kardashevskiy
This makes vfio_get_region_info_cap() to be used in quirks. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Alex Williamson <alex.williamson@redhat.com> Message-Id: <20190307050518.64968-3-aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12Suppress test warnings about missing Spectre/Meltdown mitigations with TCGDavid Gibson
The new pseries-4.0 machine type defaults to enabling Spectre/Meltdown mitigations. Unfortunately those mitigations aren't implemented for TCG because we're not yet sure if they're necessary or how to implement them. We don't fail fatally, but we do warn in this case, because it is quite plausible that Spectre/Meltdown can be exploited through TCG (at least for the guest to get access to the qemu address space). This create noise in our testcases though. So, modify the affected tests to explicitly disable the mitigations to suppress these warnings. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12spapr: Use CamelCase properlyDavid Gibson
The qemu coding standard is to use CamelCase for type and structure names, and the pseries code follows that... sort of. There are quite a lot of places where we bend the rules in order to preserve the capitalization of internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR". That was a bad idea - it frequently leads to names ending up with hard to read clusters of capital letters, and means they don't catch the eye as type identifiers, which is kind of the point of the CamelCase convention in the first place. In short, keeping type identifiers look like CamelCase is more important than preserving standard capitalization of internal "words". So, this patch renames a heap of spapr internal type names to a more standard CamelCase. In addition to case changes, we also make some other identifier renames: VIOsPAPR* -> SpaprVio* The reverse word ordering was only ever used to mitigate the capital cluster, so revert to the natural ordering. VIOsPAPRVTYDevice -> SpaprVioVty VIOsPAPRVLANDevice -> SpaprVioVlan Brevity, since the "Device" didn't add useful information sPAPRDRConnector -> SpaprDrc sPAPRDRConnectorClass -> SpaprDrcClass Brevity, and makes it clearer this is the same thing as a "DRC" mentioned in many other places in the code This is 100% a mechanical search-and-replace patch. It will, however, conflict with essentially any and all outstanding patches touching the spapr code. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Optimize x[sv]xsigdp using deposit_i64()Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190309214255.9952-3-f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Optimize xviexpdp() using deposit_i64()Philippe Mathieu-Daudé
The t0 tcg_temp register is now unused, remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190309214255.9952-2-f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: add HV support for POWER9Cédric Le Goater
We now have enough support to boot a PowerNV machine with a POWER9 processor. Allow HV mode on POWER9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-16-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: add a "ibm,opal/power-mgt" device tree node on POWER9Cédric Le Goater
Activate only stop0 and stop1 levels. We should not need more levels when under QEMU. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-15-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: add more dummy XSCOM addressesCédric Le Goater
To improve OPAL/skiboot support. We don't need to strictly model these XSCOM accesses. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-14-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: activate XSCOM tests for POWER9Cédric Le Goater
We now have enough support to let the XSCOM test run on POWER9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-13-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: POWER9 XSCOM quad supportCédric Le Goater
The POWER9 processor does not support per-core frequency control. The cores are arranged in groups of four, along with their respective L2 and L3 caches, into a structure known as a Quad. The frequency must be managed at the Quad level. Provide a basic Quad model to fake the settings done by the firmware on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special BAR setting for the TIMA area of XIVE because it resides on the same address on all chips. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-12-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: extend XSCOM core support for POWER9Cédric Le Goater
Provide a new class attribute to define XSCOM operations per CPU family and add a couple of XSCOM addresses controlling the power management states of the core on POWER9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-11-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: add a OCC model for POWER9Cédric Le Goater
The OCC on POWER9 is very similar to the one found on POWER8. Provide the same routines with P9 values for the registers and IRQ number. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-10-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: add a OCC model classCédric Le Goater
To ease the introduction of the OCC model for POWER9, provide a new class attributes to define XSCOM operations per CPU family and a PSI IRQ number. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190307223548.20516-9-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: add SerIRQ routing registersCédric Le Goater
This is just a simple reminder that SerIRQ routing should be addressed. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-8-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: add a LPC Controller model for POWER9Cédric Le Goater
The LPC Controller on POWER9 is very similar to the one found on POWER8 but accesses are now done via on MMIOs, without the XSCOM and ECCB logic. The device tree is populated differently so we add a specific POWER9 routine for the purpose. SerIRQ routing is yet to be done. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: add a 'dt_isa_nodename' to the chipCédric Le Goater
The ISA bus has a different DT nodename on POWER9. Compute the name when the PnvChip is realized, that is before it is used by the machine to populate the device tree with the ISA devices. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-6-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: add a LPC Controller class modelCédric Le Goater
It will ease the introduction of the LPC Controller model for POWER9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190307223548.20516-5-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: lpc: fix OPB address rangesCédric Le Goater
The PowerNV LPC Controller exposes different sets of registers for each of the functional units it encompasses, among which the OPB (On-Chip Peripheral Bus) Master and Arbitrer and the LPC HOST Controller. The mapping addresses of each register range are correct but the sizes are too large. Fix the sizes and define the OPB Arbitrer range to fill the gap between the OPB Master registers and the LPC HOST Controller registers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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